JPH0784665A - Clock signal supply circuit with phase-locked loop multiplication circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To enable stable clock signal supply even when the clock signal used has a high frequency. [Structure] Master N times PLL multiplication circuit 2-1 is LSI 3-1
N slave PLL multiplying circuits 2-2 to 2-n near L
Place them near the SI3-2 to 2-n respectively to make the LSI3-1.
Output from the crystal oscillator 1 that oscillates the basic clock frequency of 1 / N of the clock frequency required by 3 to 3-n, and the N-ary counter 2 that only the master N-times PLL multiplier circuit 2-1 has
The output of 0 is input as a common comparison signal to the error detection circuits 21-1 to 21-n of all the PLL multiplication circuits 2-1 to 2-n, and the PLL multiplication circuits 2-1 to 2-n are input. After multiplying the frequency by N and raising it to the original clock frequency, LSI3-1
The clock signal is supplied to 2-n.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal supply circuit used in a digital logic circuit having a plurality of semiconductor chips that use a clock signal of a predetermined frequency.

[0002]

2. Description of the Related Art Generally, a digital logic circuit mounted on various computers such as minicomputers, engineering workstations, personal computers, etc., and various control devices using microprocessors has a plurality of circuits operating at the same clock frequency. ICs and LSIs are used.

Conventionally, in order to supply a clock signal of the same frequency to a plurality of ICs or LSIs used in this digital logic circuit, a wiring is routed from one crystal oscillator to the clock signal input of each IC or LSI. Was common. In this method, the clock signal of the oscillation frequency of the crystal oscillator is directly supplied to each IC and LSI.

[0004]

In the above-described conventional clock signal supply system, the routing of the clock signal wiring becomes long and complicated, and when the frequency of the clock signal used is high, the routing of the high frequency clock signal is performed. Therefore, there is a problem that noise is generated.

The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a clock signal supply circuit capable of supplying a stable clock signal even when the clock signal used is at a high frequency.

[0006]

According to the present invention, there is provided a clock signal supply circuit for use in a digital logic circuit having a plurality of semiconductor chips which use a clock signal of a predetermined frequency, wherein a first error detector and a first error detector are provided. Integrator, first
N-times PLL (Phase-Locked Loop), which is a master composed of a variable frequency oscillator and N-ary counter
A multiplication circuit (master N-times PLL multiplication circuit), a second error detector, a second integrator, and a second variable frequency oscillator, and at least one N-times PLL multiplication circuit (slave N). Double PLL multiplication circuit),
They are arranged in the vicinity of different semiconductor chips in a one-to-one correspondence, and are provided only for the output from the basic clock frequency oscillator that oscillates the basic clock frequency of 1 / N of the above-mentioned predetermined frequency and the master N-times PLL multiplication circuit. The output of the N-ary counter is used as a common comparison signal for the master N
Not only the first error detecting circuit in the double PLL multiplying circuit, but also the second error detecting circuits in all slave N-fold PLL multiplying circuits are input and multiplied by N in each PLL multiplying circuit to raise it to a predetermined frequency. Therefore, the configuration is such that the input is made to the corresponding semiconductor chip.

Further, according to the present invention, instead of arranging the PLL frequency multiplying circuit in the vicinity of the semiconductor chip which uses the clock signal generated by the circuit, the PLL frequency multiplying circuit is built in this semiconductor chip and the clock signal is handled. It is also characterized in that it is used as a clock signal inside the semiconductor chip.

[0008]

In the above structure, the N-ary counter in the master N-fold PLL multiplier circuit divides the frequency of the clock signal output from the first variable frequency oscillator in the same PLL multiplier circuit by N, as is well known. . The N-divided output of the N-ary counter is input to the first error detection circuit in the same PLL multiplication circuit together with the output from the basic clock frequency oscillator. The first error detection circuit compares the phase relationship between these two inputs and generates a positive or negative pulse corresponding to the error. The output of this first error detection circuit is integrated by the first integration circuit in the same PLL multiplication circuit. The first variable frequency oscillator controls the oscillator frequency, that is, the frequency of the clock signal that is the output of the oscillator, so that the output of the first integrator becomes zero.

As described above, the input frequency (basic clock frequency) of 1 / N of the predetermined frequency from the basic clock frequency oscillator is multiplied by N by the master N-times PLL multiplication circuit arranged in the vicinity of the semiconductor chip to be predetermined. Raised to the frequency. Then, since the clock signal of the frequency after the pulling up is input to the semiconductor chip and used in the semiconductor chip, it is possible to eliminate the routing of the wiring of the high frequency clock signal required in the semiconductor chip and to reduce noise. It is possible to reduce the occurrence of

In the above-mentioned configuration, unlike the master N-times PLL multiplying circuit, the second error detecting circuit of each slave N-times PLL multiplying circuit does not have an N-ary counter (necessary for constructing the PLL multiplying circuit). Is the master N times PLL
The N-divided output of the N-ary counter in the multiplication circuit is input as a common comparison signal together with the output of the basic clock frequency oscillator. Then, the output of the second error detection circuit corresponding to the errors of both the inputs is integrated by the second integrator, and further the output of the second integrator becomes zero so that the second variable frequency oscillator Output frequency, that is, the frequency of the clock signal that is the output of the oscillator is controlled.

As described above, in the second error detection circuit of each slave N-times PLL multiplier circuit, the output of the basic clock frequency oscillator input to the first error detection circuit of the master N-times PLL multiplier circuit and the master N-frequency oscillator are input. Since the N-divided output of the N-ary counter in the double PLL multiplier circuit is input as a common comparison signal, the phases of the outputs of the respective PLL multiplier circuits can be made uniform.

Further, the above-mentioned PLL multiplication circuits are not arranged in the vicinity of the semiconductor chip which uses the clock signal output from the circuit but are built in the semiconductor chip, so that the generation of noise is further improved. It is possible to decrease.

[0013]

1 is a block diagram showing the configuration of a digital logic circuit having a clock signal supply circuit according to an embodiment of the present invention. In the figure, 1 is X / N M
A basic clock frequency crystal oscillator that oscillates a basic clock frequency of Hz (hereinafter simply referred to as a crystal oscillator), 2-1
Is a master N-fold PLL (phase-locked loop) multiplier circuit that generates a clock signal of X MHz by multiplying the basic clock frequency of X / N MHz from the crystal oscillator 1 by N times, and 2-2 to 2-n are Similarly, X / NM from the crystal oscillator 1
The basic clock frequency of Hz is multiplied by N, and X MH
It is a slave N-times PLL (phase-locked loop) multiplier circuit for generating a clock signal of z. The crystal oscillator 1 and the PLL multiplying circuits 2-1 to 2-n form a clock signal supply circuit 10.

The master N-fold PLL multiplication circuit 2-1 has a well-known circuit configuration of an N-ary counter 20, an error detection circuit 21-1, an integrator 22-1 and a variable frequency oscillator 23-1. The slave N-times PLL multiplication circuits 2-2 to 2-n have error detection circuits 21-2 to 21-n, integrators 22-2 to 22-n and variable frequency oscillators 23-2 to 23-n. ing. Here, the slave N-times PLL multiplier circuits 2-2 to 2-n differ from the master N-times PLL multiplier circuit 2 in the N-ary counter (20).
Note that we do not have

The N-ary counter 20 is reset for each input pulse e _i of the basic clock frequency X / N MHz from the crystal oscillator 1, and the output pulse of the PLL multiplication circuit 2-1 (variable frequency oscillator 23-1 therein). It is used as an N frequency divider that generates a pulse each time N e _o1 is counted and outputs _a frequency divided output e _a .

The error detection circuits 21-1 to 21-n are connected to the above e _i.
And e _a are compared with each other to generate positive or negative pulses e _{b1 to} e _bn corresponding to the error. Integrator 22-1 ~
22-n integrates the outputs (pulses) e _{b1 to} e _bn of the error detection circuits 21-1 to 21-n and generates control signals e _{c1 to} e _cn as the integration result.

The variable frequency oscillators 23-1 to 23-n output the outputs (control signals) e _{c1 to} e _cn of the integrators 22-1 to 22-n so that the outputs e _o1 to The frequency of e _on (clock frequency) is controlled.

3-1, 3-2 ... 3-n are semiconductor chips, and are all existing LSIs operating at a clock frequency of X MHz. In this embodiment, the LSI 3-1 is C
The PU and LSI3-2 are FPUs (floating point units). The LSI 3-n is an I / O (input / output) controller. PLL multiplication circuits 2-1 to 2-n are arranged in the vicinity of the LSIs 3-1 to 3-n, and the clock frequency generated by the PLL multiplication circuits 2-1 to 2-n is X MHz. Signals are input to the LSIs 3-1 to 3-n.

Next, the operation of the configuration of FIG. 1 will be described with reference to the timing chart of FIG. Each PLL multiplication circuit 2
The variable frequency oscillator 23-j in -j (j = 1 to n) oscillates in synchronization with the input pulse e _i , and its oscillation frequency (cycle t) is proportional to the control signal e _cj from the integrator 22-j. .

A PLL multiplication circuit (master N times PL
The output (pulse) e _o1 of the variable frequency oscillator 23-1 in the L multiplication circuit 2-1 is an N-ary counter 20 as an N frequency divider.
Is counted by. The N-ary counter 20 is once reset for each pulse e _i of the input signal of the basic clock frequency X / N MHz (cycle T) from the crystal oscillator 1, and outputs a pulse each time N pulses of the output e _o1 are counted. The master N times PLL multiplication circuit 2-1 (in the error detection circuit 21
-1) of the other, slave N times PLL multiplier circuits 2-2 through 2-n (common to divide the output used in the error detection circuit 21-2~21-n) in the (common divider output) e _a obtain.

The common frequency division output e _a of the N-ary counter 20 in the master N-times PLL multiplication circuit 2-1 is used as a comparison signal.
In addition to the error detection circuit 21-1 in the PLL multiplication circuit 2-1, it is commonly input to the error detection circuits 21-2 to 21-n in the slave N-times PLL multiplication circuits 2-2 to 2-n. In addition, each of these error detection circuits 21-1 to 21-n has an X from the crystal oscillator 1.
A pulse (common input pulse) e _i of the input signal having the basic clock frequency of / N MHz (cycle T) is also input.

The error detection circuit 21-j in each PLL multiplication circuit 2-j (j = 1 to n) has a common frequency division output e _a from the N-ary counter 20 and X / N MHz from the crystal oscillator 1. Compare the phase relationship of the basic clock frequency with the common input pulse e _i . Then, the error detection circuit 21-j changes to positive or negative depending on the generation order (input order) of these two pulses e _a and e _i (in this example, if e _a is earlier, it becomes positive, and e pulse if _i is faster)
A pulse e _bj (j = 1 to 1) whose width changes according to the time difference
n) is generated.

The output pulse e _bj from the error detection circuit 21-j (j = 1 to n) is integrated by the integrator 22-j and the average value thereof is obtained. The integration result of e _bj by the integrator 22-j is input to the variable frequency oscillator 23-j as the control signal e _cj .

Variable frequency oscillator 23-j (j = 1 to n)
Controls the oscillation frequency (clock frequency) of its output e _{oj in} the direction that the control signal e _cj from the integrator 22-j always becomes zero. That is, the variable frequency oscillator 23-1 in the master N-fold PLL multiplication circuit 2-1 controls the oscillation frequency of its output e _{o1 so} that the control signal e _c1 from the integrator 22-1 always becomes zero. Also, each slave N-fold integrator 22-2 to 22-n
The variable frequency oscillators 23-2 to 23-n in the inside are integrators 22-2.
The oscillation frequencies of the outputs e _{o2 to} e _on are controlled so that the control signals e _{c2 to} e _cn from ~ 22-n always become zero.

As a result, in the master N-time PLL multiplication circuit 2-1, the frequency (clock signal output frequency) X MHz of the clock signal supplied to the LSI 3-1 is always the input frequency X / N from the crystal oscillator 1. It is automatically controlled to be N times MHz. Similarly, the slave N-fold integrator 22
-2 to 22-n is the frequency of the clock signal supplied to the LSIs 3-2 to 3-n (clock signal output frequency) X MHz
However, the input frequency from the crystal oscillator 1 is always X / N MHz
Is automatically controlled to be N times.

Here, the input pulse e from the crystal oscillator 1
divided output from _i and N-ary counter 20 e _a, the error detection circuit 2 of the PLL multiplier circuit 2-1 to 2-n as mentioned above
It is commonly input to 1-1 to 21-n. Therefore, the outputs e _{b1 to} e _{bn of} the error detection circuits 21-1 to 21-n and the control signals e _{c1 to} e _cn for the variable frequency oscillators 23-1 to 23-n have the same phase. Therefore, the clock signal outputs e _{o1 to} e _on from the variable frequency oscillators 23-1 to 23-n to the LSIs 3-1 to 3-n also have the same phase.

Therefore, each PLL multiplication circuit 2-1 to 2-n is
By arranging in the vicinity of the LSIs 3-1 to 3-n as described above, the routing of the wiring of the high frequency clock signal required by the LSIs 3-1 to 3-n is eliminated, and noise is generated due to the routing of the high frequency clock signal. Can be suppressed.

The case where one master N-times PLL multiplying circuit and n-1 slave N-times PLL multiplying circuits are arranged in the vicinity of respective existing LSIs requiring a clock signal have been described above. However, the present invention is not limited to this, and each PLL multiplication circuit may be incorporated in a corresponding LSI.

FIG. 3 shows an embodiment of the configuration of a digital logic circuit equipped with a novel LSI incorporating such a PLL multiplier circuit. The same parts as those in FIG. 1 are designated by the same reference numerals.

In FIG. 3, the clock signal supply circuit 10
1 is similar to FIG. 1 in that it is composed of a crystal oscillator 1, a master N times PLL multiplier circuit 2-1 and slave N times PLL multiplier circuits 2-2 to 2-n.

The configuration of FIG. 3 is different from that of FIG. 1 in that the master N-fold PLL multiplication circuit 2-1 is built in a new LSI 30-1 that uses the clock signal from the same circuit 2-1 and a slave PLL is used. The multiplication circuits 2-2 to 2-n are the same as the circuits 2-2 to 2-n.
LSIs 30-2 to 30-3 that use clock signals from
It is a point built into 0-n.

Therefore, the LSI 30-1 is a master N times PL
It is called LSI 30-1 with a built-in L multiplication circuit, and LSIs 30-2 to 30-3
0-n is a slave N times PLL multiplication circuit built-in LSI 30-2 ~
I'll call it 30-n.

In this embodiment, the master N-times PLL multiplication circuit built-in LSI 30-1 is operated by a clock signal having a frequency of X MHz supplied from the master N-times PLL multiplication circuit 2-1 built in the LSI 30-1. A CPU circuit 31 for controlling the slave N-times LSI 30-2 is provided in the slave N-times LSI 30-2.
An FPU circuit 32 that operates with a clock signal whose frequency is X MHz supplied from -2 is provided. Also,
The slave N-times LSI 30-n has an I / O operated by a clock signal having a frequency of X MHz supplied from a slave N-times PLL multiplication circuit 2-n built in the LSI 30-n.
A controller circuit 33 is provided.

The operation of the configuration shown in FIG.
Since the configuration is the same as that of FIG. 1, description thereof will be omitted. However,
In the configuration of FIG. 3, each PLL multiplication circuit 2-1 to 2-n
However, L that uses the clock signals from the circuits 2-1 to 2-n
Since the SIs 30-1 to 30-n are built in, the wiring of the clock signal can be further eliminated from the configuration of FIG. 1 to further suppress the generation of noise due to the routing of the clock signal.

[0035]

As described above in detail, according to the present invention,
One master N times PLL multiplication circuit and this master N
At least one slave N-times PLL multiplication circuit sharing the N-ary counter of the multiplication PLL multiplication circuit is provided near each semiconductor chip that requires a clock signal of a predetermined frequency.
An output from a basic clock frequency oscillator arranged to correspond to 1 and oscillating a basic clock frequency of 1 / N of the predetermined frequency, and an output of the N-ary counter provided only in the master N-times PLL multiplier circuit are provided. , As the common comparison signal, the error detection circuit of the master N times PLL multiplication circuit (first
The error detection circuit) is, of course, also input to the error detection circuits (2 error detection circuits) in all the slave N-fold PLL multiplication circuits, multiplied by N in each PLL multiplication circuit, and raised to a predetermined frequency. Since the configuration is such that the semiconductor chips are input, it is possible to reduce the generation of noise due to the high-frequency clock signal by eliminating the wiring of the high-frequency clock signal wiring required in each semiconductor chip. Moreover, the output of the N-ary counter provided only in the master N-times PLL multiplying circuit is used as a comparison signal for detecting an error between the output of the basic clock frequency oscillator and the slave N-times PL.
Since the L multiplier circuits are also used in common, the output clock signals from the respective PLL multiplier circuits can have the same phase, which is equivalent to supplying a common clock signal to each semiconductor chip.

Further, according to the present invention, the PLL frequency multiplying circuit is incorporated in the semiconductor chip instead of being arranged in the vicinity of the semiconductor chip using the clock signal generated by the circuit, and the clock signal is generated. By using as a clock signal inside the corresponding semiconductor chip, it is possible to further eliminate the routing of the high-frequency clock signal wiring required in each semiconductor chip,
It is possible to further reduce the occurrence of noise due to the high frequency clock signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital logic circuit including a clock signal supply circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment.

FIG. 3 is a block diagram showing the configuration of a digital logic circuit including a clock signal supply circuit according to another embodiment of the present invention.

[Explanation of symbols]

1 ... Basic clock frequency crystal oscillator (basic clock frequency oscillator), 2-1 ... Master N times PLL (phase lock loop) multiplier circuit, 2-2 to 2-n ... Slave N times PLL multiplier circuit, 3-1 to 3 -n ... LSI (semiconductor chip), 10 ... Clock signal supply circuit, 20 ... N-ary counter, 21-1 ... Error detection circuit (first error detection circuit), 21-2 to 22-n ...
Error detection circuit (second error detection circuit), 22-1 ... Integrator (first integrator), 22-2 to 22-n ... Integrator (second integrator), 23-1 ... Variable frequency Oscillator (first variable frequency oscillator), 23-2 to 23-n ... Variable frequency oscillator (second variable frequency oscillator), 30-1 ... Master N-times PLL multiplication circuit built-in LSI (semiconductor chip), 30-2 -30-n ... Slave N times PLL multiplication circuit built-in LSI (semiconductor chip).

Claims (2)

[Claims] 1. A clock signal supply circuit used in a digital logic circuit having a plurality of semiconductor chips using a clock signal of a predetermined frequency, wherein the basic clock frequency oscillator oscillates a basic clock frequency of 1 / N of the predetermined frequency. And one master N-times that multiplies the basic clock frequency from the basic clock frequency oscillator by N times to generate a clock signal of the predetermined frequency and supplies the clock signal to one of the plurality of semiconductor chips. A phase-locked loop multiplication circuit, which is an N-ary counter for dividing the frequency of the clock signal by N, compares the phase relationship between the frequency-divided output of this N-ary counter and the output of the basic clock frequency oscillator, and A first error detector for generating a positive or negative pulse corresponding to the error, and an output of the first error detector One master N-fold phase-locked loop multiplier consisting of a first integrator for integration and a first variable frequency oscillator for controlling the frequency of the clock signal such that the output of the first integrator is zero A circuit, and at least one that multiplies the basic clock frequency from the basic clock frequency oscillator by N times to generate a clock signal of the predetermined frequency and supplies the clock signal to another one of the plurality of semiconductor chips. Two slave N-times phase-locked loop multiplier circuits, comparing the phase relationship between the divided output of the N-ary counter and the output of the basic clock frequency oscillator in the master N-times phase-locked loop multiplier circuit A second error detector for generating a positive or negative pulse corresponding to, a second integrator for integrating the output of the second error detector, and At least one slave N-fold phase-locked loop multiplication circuit having a second variable frequency oscillator for controlling the frequency of the clock signal so that the output of the second integrator becomes zero; A clock signal supply circuit, wherein a lock loop multiplication circuit and the slave N-times phase lock loop multiplication circuit are arranged in the vicinity of the semiconductor chip to which the clock signal is supplied. 2. A clock signal supply circuit used in a digital logic circuit having a plurality of semiconductor chips using a clock signal of a predetermined frequency, wherein the basic clock frequency oscillator oscillates a basic clock frequency of 1 / N of the predetermined frequency. And one master N-times phase lock that multiplies the basic clock frequency from the basic clock frequency oscillator by N times to generate a clock signal of the predetermined frequency to be used as one internal clock signal of the plurality of semiconductor chips. A loop multiplication circuit, which is an N-ary counter for dividing the frequency of the clock signal by N, compares the phase relationship between the frequency-divided output of the N-ary counter and the output of the basic clock frequency oscillator, and determines the error. A first error detector for generating a corresponding positive or negative pulse, this first error detector One master N-times phase lock composed of a first integrator for integrating the output and a first variable frequency oscillator for controlling the frequency of the clock signal so that the output of the first integrator becomes zero A loop multiplication circuit, and at least one that multiplies the basic clock frequency from the basic clock frequency oscillator by N times to generate a clock signal of the predetermined frequency to be used as another one internal clock signal of the plurality of semiconductor chips. Two slave N-times phase-locked loop multiplier circuits, comparing the phase relationship between the divided output of the N-ary counter and the output of the basic clock frequency oscillator in the master N-times phase-locked loop multiplier circuit Error detector for generating a positive or negative pulse corresponding to the second error detector, and a second integral for integrating the output of the second error detector , And the output of the second integrator provided with at least one slave N times the phase-locked loop frequency multiplier circuit having a second variable frequency oscillator to control the frequency of the clock signal to be zero,
A clock signal supply circuit, wherein the master N-times phase lock loop multiplier circuit and the slave N-times phase lock loop multiplier circuit are respectively built in the corresponding semiconductor chips.