JPH0784884A - Virtual computer system - Google Patents

Abstract

PURPOSE:To immediately discriminate the level of a virtual computer in processing by providing a current execution level managing means which holds the current execution level of the virtual computer at all times. CONSTITUTION:This system is equipped with a current level discriminating device (CVML and current execution level managing means) which holds the execution level of the virtual computer (OS) which currently runs. Then the state of the virtual computer system is changed from a process state by the OS which currently runs to a process state by another OS which is different in level, an entry (discrimination information entry) of a VMID stack 104 where discrimination information regarding the transition OS is already registered is made effective and selected by using a VMID stack selecting circuit 103 if the discrimination information is registered, but when the information is not registered yet, a VM identifier and its execution level corresponding to the OS as the destination of the transition are newly registered in a VMIDS (VM identifier storage filed) 105 and a VML (execution level storage field) 106.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a virtual computer system, and more particularly to a virtual computer system for simultaneously controlling virtual computers of three or more levels.

[0002]

2. Description of the Related Art Conventionally, a virtual machine control program (Virtual Machine Control Program,
(Hereinafter abbreviated as “VMCP”)
Multiple operating systems (OS) under control of P
There is known a virtual computer system that constructs a plurality of virtual computers by simultaneously executing.

Generally, in an information processing apparatus using a virtual memory system, a logical address designated when a virtual computer accesses an instruction or data in the virtual memory is stored in a main memory provided in a real computer. It must be converted to an absolute address (hereinafter referred to as "physical address"). Therefore, in the above-mentioned conventional virtual computer system, a VMCP (hereinafter referred to as "LEVEL-
"OS") is an address conversion table (hereinafter "LEVEL-") showing the correspondence between a logical address in the virtual address space on LEVEL-OS (hereinafter "LEVEL-logical address") and a physical address. A virtual address space is generated by managing a "translation table"), and the OS of a virtual computer at a lower level on the virtual address space in the LEVEL-OS (hereinafter, "LEVEL-OS").
OS) and run LEVE.
The L-OS is an address conversion table (hereinafter referred to as “LEVEL-conversion”) showing a correspondence relationship between a logical address in the virtual address space on the LEVEL-OS (hereinafter referred to as “LEVEL-logical address”) and a LEVEL-logical address. table"
Is described) and a virtual address space is generated. That is, in order to perform the conversion between the LEVEL-logical address and the physical address, it is necessary to perform the address conversion using the two sets of address conversion tables of the LEVEL-conversion table and the LEVEL-conversion table. For example, I
"IBM System / 370 Extended Architecture" issued by BM
In "Interpretive Execution" (SA22-7095), a method of realizing this two-stage address conversion by hardware is introduced.

The address translation information (physical address information corresponding to each individual logical address) obtained by using the above-mentioned address translation table is stored in the address translation buffer (Tr.
anslation Lookaside Buffer, hereinafter referred to as "TLB"). Prior arts related to TLB are disclosed in Japanese Patent Publication No. Sho 61-22825, Japanese Patent Publication No. 58-8073, and Japanese Unexamined Patent Publication No.
It is disclosed in Japanese Patent No. 163838.

In the virtual computer system disclosed in Japanese Patent Publication No. Sho 61-22825, an entry (LEVEL-address conversion information indicating correspondence between a logical address and a physical address) related to the LEVEL-OS is currently running on a single TLB. LEVEL-
Only two types of entries of the OS-related entries (LEVEL-address conversion information indicating the correspondence between the logical address and the physical address) are held. In the virtual computer system disclosed in Japanese Patent Publication No. 58-8073, the TLB field is expanded so that the address translation information is LEVEL-OS or a plurality of LEVEL-Os.
By adding a virtual machine identifier (hereinafter referred to as “VM identifier”) for identifying which one of the S is related to LEVEL-OS and two or more LEVEL-OSs on the TLB. It is possible to hold entries at the same time. Further, in the virtual computer system disclosed in Japanese Patent Laid-Open No. 1-163838, by providing a means for identifying whether or not the address translation information is held in the TLB, it is possible to efficiently perform the control related to the TLB. There is.

By the way, in recent years, LEVEL-OS (VMC
LEVEL-OS which is a virtual machine operating under control of P)
By using VMCP as a type of LEVEL-
Under the control of OS (VMCP), a virtual machine, namely LEVEL-
A technique for further operating the OS is disclosed in, for example, Japanese Patent Laid-Open No. 4-856.
No. 42 publication.

[0007]

[Problems to be Solved by the Invention] Japanese Patent Publication No. 58-80
In the virtual computer system disclosed in Japanese Patent Laid-Open No. 73 or Japanese Patent Laid-Open No. 1-163838, a LEVEL-OS and a plurality of LEVEs are installed on the TLB.
It is possible to simultaneously hold two or more types of entries (address translation information) related to the L-OS. However, when the virtual machine, that is, LEVEL-OS is further operating under the control of LEVEL-OS (VMCP),
No consideration was given to how to process the address translation information registered in the TLB.

For example, when the OS invalidates all address translation information relating to the OS, the purge TLB that invalidates all the entries registered in the TLB.
An instruction (hereinafter referred to as "PTLB instruction") is issued. At this time, the LEVEL-O issued the PTLB instruction.
If S, only the entry corresponding to the LEVEL-OS on the TLB is invalidated. If the LEVEL-OS issued the PTLB command, the LEVEL-OS on the TLB is issued.
Invalidate all entries including. This is LEVEL-
Address conversion information that indicates the individual correspondence between logical addresses and physical addresses is provided in the LEVEL-conversion table and
LEVEL-Because it is generated by referring to the conversion table, LEVE
This is because if the L-logical address is invalidated, the LEVEL-logical address indicating the virtual address space in the LEVEL-OS which is a virtual computer operating under the control of the LEVEL-OS must also be invalidated. By thus rewriting the contents of the TLB so that there is no contradiction, the normal operation of the conventional virtual computer system is guaranteed.

However, VMC as LEVEL-OS
When P is used and the entry (address translation information) corresponding to the LEVEL-OS operating under the control is registered in the TLB, the LEVEL-OS (VMCP) is the PTL.
Issuing the B command invalidates only the entry corresponding to the LEVEL-OS in the TLB, and the LEVEL-OS in question
Since the entry corresponding to the LEVEL-OS operating under the control of the above will remain valid, the content of the TLB after the PTLB instruction is executed is inconsistent and the normal operation of the virtual computer system is guaranteed. There was a problem that I could not do it.

Therefore, an object of the present invention is to solve the above problems and to provide one or more LEVEL- under the control of LEVEL-OS.
OS (more than one LEVEL-OS, LEVEL-OS
When operating the LEVEL-OS (LEVEL-O)
S, LEVEL-OS) is provided with a TLB capable of holding a mixture of entries (address conversion information) corresponding to
Even if the TLB-related processing such as the LB instruction is executed, the TLB is
The normal operation of the virtual computer system is guaranteed so that the contents of the LEVEL-OS and LEVEL-OS are not changed.
It is an object of the present invention to provide a virtual computer system that maintains the same processing performance as in the past when only the entry corresponding to is registered in the TLB.

[0011]

[Means for Solving the Problems]

(1) In order to achieve the above object, the virtual computer system of the present invention has a virtual computer control means for controlling a plurality of the virtual computers generated over one level or more on a real computer or a virtual computer. In a computer system, a current execution level management means for always holding a current execution level that is read and written by a control device that controls the real computer and indicates which level of the virtual computer is currently being processed on the real computer. It is configured to include.

(2) In addition to the configuration of (1), an identifier for identifying the virtual computer and its execution level for each of the virtual computers that are read and written by the control device and simultaneously exist on the real computer. And an identification information selection unit that selects the identification information entry to be read and written by the control device.

(3) Further, in addition to the configuration of (2), the identifier, the logical address designated on the virtual computer, which is read and written by the address translation buffer control device which operates according to an instruction from the control device, An address translation buffer entry consisting of address translation information consisting of three of the physical addresses on the real computer corresponding to the logical address and a registered flag indicating the validity of the address translation information is provided for each of the virtual computers. The above-mentioned address translation buffer and the address translation buffer selection means for selecting the address translation buffer entry to be read and written by the address translation buffer control device are provided.

(4) In addition to the configuration of (1), the identifier, the logical address specified on the virtual computer, which is read and written by the address translation buffer control device which operates according to an instruction from the control device, A physical address on the real computer corresponding to a logical address, address translation / execution level information consisting of four execution levels of the virtual computer indicated by the identifier, and registered indicating the validity of the address translation / execution level information. An address translation buffer that holds one or more address translation buffer entries each of which includes a flag, and an address translation buffer selection unit that selects the address translation buffer entry to be read and written by the address translation buffer controller. And is configured to include.

[0015]

The operation based on the above configuration will be described.

(1) In the virtual computer system of the present invention, in the virtual computer system having virtual computer control means for controlling each of the plurality of virtual computers generated over one level or more on the real computer or the virtual computer, A configuration comprising a current execution level management means for always holding a current execution level which is read and written by a control device for controlling a real computer and indicates which level of the virtual computer is currently being processed on the real computer; Therefore, the control device can immediately identify the level (current execution level) of the virtual computer being processed by referring to the current execution level management means at any time.

(2) In addition to the configuration of (1), an identifier for identifying the virtual computer and its execution level for each of the virtual computers that are read and written by the control device and are simultaneously present on the real computer. Since it is configured to include an identification information holding unit that holds an identification information entry consisting of, and an identification information selection unit that selects the identification information entry to be read and written by the control device,
Referring to the identification information holding means using the identification information selection means,
By obtaining the identifier corresponding to the execution level that matches the current execution level identified by the current execution level management means as described above, it is possible to specify the virtual computer being processed.

(3) Further, in addition to the configuration of (2), the identifier, the logical address specified on the virtual computer, which is read and written by the address translation buffer control device which operates according to an instruction from the control device, An address translation buffer entry consisting of address translation information consisting of three of the physical addresses on the real computer corresponding to the logical address and a registered flag indicating the validity of the address translation information is provided for each of the virtual computers. Since the address translation buffer is held and the address translation buffer selection means for selecting the address translation buffer entry to be read and written by the address translation buffer control device is provided, the virtual machine under processing specified by the above For a computer (eg LEVEL-OS), one or more corresponding ads Scan conversion buffer entry (i.e., identifier entry indicating LEVEL-OS) with automatically performs processes such as selection and read-write and invalidate to this, the in process virtual machine (LEVEL-
Virtual machine (LEVEL-OS, which is created on the OS)
Similarly, for LEVEL-OS, ..., the address translation buffer entry (that is, the identifier is LEVEL-OS,
LEVEL-OS, etc.) is automatically selected, and processing such as reading, writing, and invalidation is automatically performed to ensure normal operation of the virtual computer system so that the contents of the address translation buffer are not inconsistent. it can.
In addition, when the virtual machine is not created on the virtual machine (LEVEL-OS) being processed (that is, LEVEL-O)
In the case where only the address translation buffer entry corresponding to S and LEVEL-OS is registered), the processing performance similar to the conventional one can be maintained.

(4) In addition to the configuration of (1), the identifier, the logical address specified on the virtual computer, which is read and written by the address translation buffer controller that operates according to an instruction from the controller, A physical address on the real computer corresponding to a logical address, address translation / execution level information consisting of four execution levels of the virtual computer indicated by the identifier, and registered indicating the validity of the address translation / execution level information. An address translation buffer that holds one or more address translation buffer entries each of which includes a flag, and an address translation buffer selection unit that selects the address translation buffer entry to be read and written by the address translation buffer controller. Since the configuration is provided with, One or more address translation buffer entries containing execution levels that match the current execution level identified using the management means are selected as those that correspond to the virtual machine that is being processed, and processing such as read / write or invalidation for this is selected. It can be carried out. Further, for the virtual machine under processing (for example, LEVEL-OS) specified above, selection of one or more corresponding address translation buffer entries (that is, an entry whose identifier indicates LEVEL-OS) and reading / writing or invalidation thereof Etc. is automatically performed and the virtual machine (LEVEL-
Virtual machine (LEVEL-OS, which is created on the OS)
Similarly, for LEVEL-OS, ..., the address translation buffer entry (that is, the identifier is LEVEL-OS,
LEVEL-OS, etc.) is automatically selected, and processing such as reading, writing, and invalidation is automatically performed to ensure normal operation of the virtual computer system so that the contents of the address translation buffer are not inconsistent. it can.
In addition, when the virtual machine is not created on the virtual machine (LEVEL-OS) being processed (that is, LEVEL-O)
In the case where only the address translation buffer entry corresponding to S and LEVEL-OS is registered), the processing performance similar to the conventional one can be maintained.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a virtual computer system of the present invention will be described in detail below with reference to some drawings.

FIG. 1 is a functional block diagram showing the configuration of an embodiment of the virtual computer system of the present invention. 1 in the figure
01 is a control unit (CU) for controlling and managing other connected devices, data transfer, data processing, and the like, 102
Is an execution level identification device (CVML, current execution level management means) that holds the execution level of the currently running OS (virtual computer), and 104 is a VMID stack (identification information holding means) that manages the VM identifier (identification name). ), 103 is a VM that specifies which entry (identification information entry) in the VMID stack 104 to read / write.
ID stack selection circuit (identification information selection means), 109 is an address translation buffer (TLB), and 108 is TLB10.
9, an address translation buffer selection circuit (TLB selection circuit, address translation buffer selection means) for designating which entry (address translation buffer entry) in 9 is to be read or written, and 107 controls and manages the TLB selection circuit 108 and TLB 109. Address translation buffer controller (TLB controller) for reading and writing data
Is.

The current execution level in CVML 102 is
When a transition is made to the OS of each execution level, a value corresponding to the execution level of the OS is set. VMID
Each entry in the stack 104 has a VM identifier storage field (V
MIDS) 105 and an execution level storage field (VML) 106 in which the execution level of the OS is recorded. Each entry in the TLB 109 has a registered flag (V) 110 indicating whether or not the data recorded in the entry is valid, and a VM identifier storage field (VMIDT) 11 in which a VM identifier specifying the OS is recorded.
1. A logical address storage field (LA) 1 in which a logical address in the virtual address space on the OS is recorded
12, a physical address storage field (PA) 1 in which the physical address on the real computer corresponding to the logical address is recorded
The contents of each field are registered or updated when the address conversion is performed. Also, TL
The VMIDT 111 in B109 stores the contents of the VMIDS 105 selected by the VMID stack selection circuit 103, and when normal address translation is performed, the entry corresponding to the currently running OS is TLB.
It is selected by the selection circuit 108.

2 and 3 are explanatory views showing the processing of the PTLB instruction in the virtual computer system of FIG.
FIG. 2 shows an overall processing flow, and FIG. 3 shows a common processing flow. When the PTLB instruction is issued, the CU 101 refers to the CVML 102 in step 200, and the current OS, that is, the OS that issued the PTLB instruction.
Identify the level of and branch according to that level. In this embodiment, LEVEL-OS, LEVEL-OS, LEVEL-OS
It is assumed that three levels of OS, OS, are being executed at the same time.

(1) The OS that issued the PTLB instruction is LEVEL-
In the case of OS In this case, the process branches from step 200 to step 211. In step 211, all the TLB entries (address translation buffer entries) in the TLB 109 are transferred to the TLBCU 10 according to an instruction from the CU 101.
7 sequentially uses the TLB selection circuit 108 to select V11.
Reset 0. This invalidates all TLB entries.

(2) The OS that issued the PTLB instruction is LEVEL-
In the case of OS In this case, the process branches from step 200 to step 221. In step 221, all valid entries (identification information entries) in the VMID stack 104 are selected using the VMID stack selection circuit 103, and V
LE in TLB109 by searching ML106
It is identified whether or not the address translation information of VEL-OS is registered, and the process branches depending on the result.

(2) -a When the LEVEL-OS address translation information is not registered in the TLB 109 In this case, the process branches from step 221 to step 231. In step 231, a common process A whose details are shown in FIG. 3 is performed. In step 301 of the common processing A, the CU 101 determines that the VMID stack selection circuit 103
Is used to select an entry corresponding to the currently running LEVEL-OS from the entries (identification information entries) of the VMID stack 104, and the VMIDS 10 in the entry is selected.
The VM identifier registered in 5 is reported to the TLBCU 107. Then, in step 302, the CU 101
In response to the instruction from the TLBCU 107, the TLBCU 107 selects all the entries including the VMIDT 111 in which the VM identifier reported above is registered using the TLB selection circuit 108, and resets the V110 in the entry. As a result, only the address translation information corresponding to the currently running LEVEL-OS is invalidated.

(2) -b When the LEVEL-OS address conversion information is registered in the TLB 109 In this case, the process branches from step 221 to step 222. In step 222, LEVEL-O currently running
The common process A described above is performed for S. Step two
At 23, the CU 101 uses the VMID stack selection circuit 103 to select the LEVEL-O currently running from among the entries (identification information entries) of the VMID stack 104.
Select one of the entries corresponding to LEVEL-OS under the control of S (VMCP), and select the VMID in the entry.
The VM identifier registered in S105 is set to TLBCU10.
Report to 7. In step 224, the CU 101
In response to the instruction from the TLBCU 107, the TLBCU 107 selects all the entries including the VMIDT 111 in which the VM identifier reported above is registered using the TLB selection circuit 108, and resets the V110 in the entry. As a result, the LEVEL-OS (VMC currently running)
Only the address translation information corresponding to one of the LEVEL-OSs under the control of P) is invalidated. Step 22
5, the CU 101 uses the VMID stack selection circuit 103 to set the VML 10 in the VMID stack 104.
By retrieving 6, it is determined whether or not another LEVEL-OS is under the control of the LEVEL-OS (VMCP) currently running, and if it is present, the process returns to step 223 and the LEVEL-OS concerned is returned. The address translation information corresponding to the OS is invalidated. As a result, the LEVEL-OS currently running
The address translation information corresponding to all LEVEL-OSs under the control of (VMCP) is invalidated.

(3) The OS that issued the PTLB instruction is LEVEL-
In the case of OS In this case, the process branches from step 200 to step 231. In step 231, the LEVEL-O currently running
The common process A described above is performed for S.

FIG. 4 shows the VMID stack 104 shown in FIG.
FIG. 5 is an explanatory diagram showing a process of registering an identification information entry in the. In the figure, the LEVEL-OS is always activated in the virtual computer system in the initial state (for example, immediately after power-on). At this time, the CU 101 recognizes that the valid VMID stack entry in the VMID stack 104 is only one LEVEL-OS, and the VM concerned.
The VMIDS 150 and the VML 106 corresponding to the ID stack entry have V indicating that they are LEVEL-OS.
The M identifier and its execution level “1” are stored. This is the state of the VMID stack 104 at the "Start" point in the figure.

When the state of the virtual computer system transits from the processing state by the currently running OS (for example, LEVEL-OS) to the processing state by another OS of different level (for example, LEVEL-OS), Step 40
At 0, the CU 101 is about to transition O
It is determined whether or not the identification information regarding S (LEVEL-OS) is already registered in the entry (identification information entry) in the VMID stack 10, and if it is already registered, the VMID stack selection circuit is considered to be valid. Select using 103. If it is not registered yet, the OS (LE
VMIDS 105 and VML 106 for the VM identifier and its execution level (“2”) corresponding to VEL-OS).
Register anew to.

As described above, according to the present embodiment, the address translation information regarding virtual machines of a plurality of levels is TLB.
Even if it is registered in, the entry (address translation buffer entry) corresponding to the virtual machine being processed can be selected and the PTLB instruction can be executed for it. Further, also for the virtual machine created on the virtual machine being processed, the corresponding entry can be similarly selected and the PTLB instruction can be executed for this. Therefore, it is possible to improve the performance of the virtual computer system by avoiding the processing for the entry that does not need to be invalidated by the PTLB instruction.

Although only the processing of the PTLB instruction has been described in the present embodiment, the same effect can be obtained with other instructions relating to reading and writing of the address translation buffer entry. Although the VMID stack 104 and the TLB 109 are independently provided in this embodiment, the VMID stack 104 is not provided by including the information of the VML 106 in the VMID stack 104 in the TLB 109. You can also

[0033]

【The invention's effect】

(1) As described in detail above, according to the virtual computer system of the present invention, the virtual computer control means for controlling the plurality of virtual computers generated over one level or more on the real computer or the virtual computer is provided. In a virtual computer system, a current execution level management that is always read and written by a control device that controls the real computer and that always holds a current execution level indicating which level of the virtual computer is currently being processed on the real computer. Since the control device is configured to include the means, the control device can refer to the current execution level management means at any time,
The effect is that the level of the virtual machine being processed (current execution level) can be immediately identified.

(2) Then, in addition to the configuration of (1), an identifier for identifying the virtual computer and its execution level for each of the virtual computers that are read and written by the control device and simultaneously exist on the real computer. Since it is configured to include an identification information holding unit that holds an identification information entry consisting of, and an identification information selection unit that selects the identification information entry to be read and written by the control device,
Referring to the identification information holding means using the identification information selection means,
By obtaining the identifier corresponding to the execution level that matches the current execution level identified by using the current execution level management means as described above, it is possible to specify the virtual computer being processed.

(3) Further, in addition to the configuration of (2), the identifier, the logical address specified on the virtual computer, which is read and written by the address translation buffer control device which operates according to an instruction from the control device, An address translation buffer entry consisting of address translation information consisting of three of the physical addresses on the real computer corresponding to the logical address and a registered flag indicating the validity of the address translation information is provided for each of the virtual computers. Since the address translation buffer is held and the address translation buffer selection means for selecting the address translation buffer entry to be read and written by the address translation buffer control device is provided, the virtual machine under processing specified by the above For a computer (eg LEVEL-OS), one or more corresponding ads Scan conversion buffer entry (i.e., identifier entry indicating LEVEL-OS) with automatically performs processes such as selection and read-write and invalidate to this, the in process virtual machine (LEVEL-
Virtual machine (LEVEL-OS, which is created on the OS)
Similarly, for LEVEL-OS, ..., the address translation buffer entry (that is, the identifier is LEVEL-OS,
LEVEL-OS, etc.) is automatically selected, and processing such as reading, writing, and invalidation is automatically performed to ensure normal operation of the virtual computer system so that the contents of the address translation buffer are not inconsistent. The effect of being able to be obtained is obtained. In addition, the virtual machine (LEVE
If a virtual machine is not created on the L-OS) (that is, only the LEVEL-OS and the address translation buffer entry corresponding to the LEVEL-OS is registered), the same processing performance as the conventional one is maintained. The effect of being able to do is obtained.

(4) Further, in addition to the configuration of (1), the identifier, the logical address designated on the virtual machine, and the logical address read and written by the address translation buffer controller which operates according to an instruction from the controller, A physical address on the real computer corresponding to a logical address, address translation / execution level information consisting of four execution levels of the virtual computer indicated by the identifier, and registered indicating the validity of the address translation / execution level information. An address translation buffer that holds one or more address translation buffer entries each of which includes a flag, and an address translation buffer selection unit that selects the address translation buffer entry to be read and written by the address translation buffer controller. Since the configuration is provided with, One or more address translation buffer entries containing execution levels that match the current execution level identified using the management means are selected as those that correspond to the virtual machine that is being processed, and processing such as read / write or invalidation for this is selected. The effect that it can be obtained is obtained. Also, for the virtual machine under processing (for example, LEVEL-OS) identified by the above, one or more corresponding address translation buffer entries (that is, the identifier is LEVEL-O).
(The entry indicating S) and the processing such as reading, writing, and invalidation for the same are automatically performed, and the virtual machines (LEVEL-OS, LEVEL-OS) generated on the virtual machine (LEVEL-OS) being processed , ...) similarly for the address translation buffer entry (ie,
The virtual computer system is normally operated so that the contents of the address translation buffer are not inconsistent by automatically performing processing such as selection of an entry whose identifier is LEVEL-OS, LEVEL-OS, ... The effect is that the operation can be guaranteed. Also, when no virtual machine is created on the virtual machine (LEVEL-OS) being processed (that is, LEVEL-OS, LEVEL-OS).
In the case where only the address translation buffer entry corresponding to the OS is registered), it is possible to maintain the same processing performance as the conventional one.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing the configuration of an embodiment of a virtual computer system of the present invention.

FIG. 2 is an explanatory diagram showing the overall processing of a PTLB instruction in the virtual computer system of FIG.

FIG. 3 is an explanatory diagram showing common processing of PTLB instructions in the virtual machine system of FIG.

FIG. 4 is an explanatory diagram showing a process of registering an identification information entry in a VMID stack shown in FIG.

[Explanation of symbols]

101 Control Unit (CU) 102 Execution Level Identification Unit (CVML, Current Execution Level Management Means) 103 VMID Stack Selection Circuit (Identification Information Selection Means) 104 VMID Stack (Identification Information Holding Means) 107 Address Translation Buffer Control Unit (TLB Control Equipment) ) 108 address translation buffer selection circuit (TLB selection circuit, address translation buffer selection means) 109 address translation buffer (TLB)

Claims (4)

[Claims] 1. A virtual computer system having virtual computer control means for controlling a plurality of the virtual computers generated on one or more levels on a real computer or a virtual computer, wherein a controller for controlling the real computer is used. A virtual machine system characterized by comprising a current execution level management means for always holding a current execution level which is read and written and which level of the virtual machine is currently being processed on the real computer. . 2. An identification information holding unit which holds an identification information entry, which is read and written by the control device and which simultaneously exists on the real computer, for each virtual computer, the identification information including an identifier for identifying the virtual computer and its execution level. 2. The virtual computer system according to claim 1, further comprising: an identification information selection unit that selects the identification information entry to be read and written by the control device. 3. The identifier, a logical address specified on the virtual computer, which is read and written by an address translation buffer control device which operates according to an instruction from the control device,
An address translation buffer entry consisting of address translation information consisting of three of the physical addresses on the real computer corresponding to the logical address and a registered flag indicating the validity of the address translation information is provided for each of the virtual computers. 3. An address translation buffer for holding the above, and an address translation buffer selection means for selecting the address translation buffer entry to be read and written by the address translation buffer control device. Virtual computer system. 4. The identifier, a logical address specified on the virtual computer, which is read and written by an address translation buffer control device which operates according to an instruction from the control device,
A physical address on the real computer corresponding to the logical address, address translation / execution level information consisting of four execution levels of the virtual computer indicated by the identifier, and registration indicating the validity of the address translation / execution level information. Address translation buffer entry consisting of an address flag and one or more address translation buffer entries for each of the virtual machines, and address translation buffer selection for selecting the address translation buffer entry to be read and written by the address translation buffer controller. The virtual computer system according to claim 1, wherein the virtual computer system comprises a means.