JPH0785131A - Drawing method of integrated circuit for specific application - Google Patents

Abstract

(57) [Abstract] [Purpose] It is possible to automatically and accurately inspect the designed special purpose integrated circuit without visual inspection. [Structure] Logical data and test data of the designed application-specific integrated circuit are transferred from the data file 14 to the memory 1.
Loaded to 5. A signal that can be an input is extracted from the loaded logic data, test data corresponding to the signal is extracted, and when both “1” and “0” are described, it is determined as test data OK. Further, if the expected value set for the signal that can be output in the logical data is satisfied, the logical operation is determined to be OK. Also, the circuit scale of the application-specific integrated circuit is calculated as the number of equivalent gates, and the suitability of the test data is determined from the relationship with the number of steps of the test data. Further, a combination of input and output is extracted from the logical data, usable device candidates are selected from this combination, and a device having excellent cost performance is selected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is for testing whether or not an application specific integrated circuit or ASIC designed for a specific purpose by using a gate array or the like performs a desired function. Relates to a method for checking an integrated circuit for a specific application.

[0002]

2. Description of the Related Art Inspection of an application-specific integrated circuit such as a programmable logical device (PLD) is performed by, for example, CAD / CAE a waveform of test data formed for a designed application-specific integrated circuit. Etc. are displayed on the display screen, and visually inspected to see if they are formed as designed. The waveform displayed on this screen must be compared with the clock on the screen to see, for example, whether various input signals are generated at a predetermined timing with respect to the clock signal. The reality was that it was extremely difficult and had to rely primarily on the intuition of the operator.

[0003]

As described above, since the conventional inspection relies on human vision, it is difficult to sufficiently and accurately inspect the application-specific integrated circuit. It is therefore an object of the present invention to provide a drawing method for an application-specific integrated circuit, which can perform a sufficient and accurate drawing of the application-specific integrated circuit without depending on human vision.

[0004]

SUMMARY OF THE INVENTION A method of drawing an application-specific integrated circuit according to the present invention stores a logic data of a designed application-specific integrated circuit, and stores the designed application-specific integrated circuit. Storing test data for the test of, evaluating data of a predetermined attribute of the stored logical data, evaluating data of the predetermined attribute of the test data, the logical data and the test data At least one of the design content of the application specific integrated circuit and the content of the test data is evaluated based on the result of the evaluation.

Further, the drawing method of the application-specific integrated circuit of the present invention stores the logic data of the designed application-specific integrated circuit, and is used for testing the designed application-specific integrated circuit. Of the test data is stored, all the signals that can be input are extracted from the logic data, and the content of the test data corresponding to the extracted signal is set to the logic level "0".
It is characterized in that it is determined whether both "1" and "1" are included.

Further, the drawing method of the application-specific integrated circuit of the present invention stores the logic data of the designed application-specific integrated circuit, and is used for testing the designed application-specific integrated circuit. Test data is stored, all the signals that can be output are extracted from the logic data, and it is determined whether or not the content of the test data corresponding to the extracted signal includes an expected value. .

Further, the drawing method of the application-specific integrated circuit of the present invention stores the logic data of the designed application-specific integrated circuit, and is used for testing the designed application-specific integrated circuit. Test data is stored, the possible values of the output are extracted from the logic data, and it is judged whether or not the test data satisfies the extracted value for the corresponding signal.

Further, the drawing method of the application-specific integrated circuit of the present invention stores the logic data of the designed application-specific integrated circuit, and is used for testing the designed application-specific integrated circuit. Test data is stored, the circuit scale of the special purpose integrated circuit is calculated from the logic data, the number of test data steps is counted, and the number of test data steps is calculated with respect to the calculated circuit scale. It is characterized by calculating how much value it has and based on the calculated result, the quality of the application specific integrated circuit and the test data is judged.

Further, the drawing method of the application-specific integrated circuit according to the present invention stores the logic data of the designed application-specific integrated circuit to test the designed application-specific integrated circuit. Test data is stored, the number of equivalent gates of the application-specific integrated circuit is calculated from the logic data, the number of steps of test data is counted, and the number of steps of test data is calculated. It is characterized by calculating how many values it has with respect to the number of gates, and judging whether the integrated circuit for a particular application or the test data is good or bad based on the calculated result.

[0010]

According to the present invention, data having a predetermined attribute, for example, a signal that can be an input or an output, is extracted from the designed logic data of an application-specific integrated circuit, and the contents of test data corresponding to the extracted signal are extracted. Evaluating whether or not both logic levels “1” and “0” are included, or whether or not an expected value is included, or whether or not the test data satisfies the extracted value. In this way, the inspection of the integrated circuit for a specific application is performed.

According to the present invention, the circuit scale of the application specific integrated circuit, for example, the number of equivalent gates is calculated from the designed logic data of the application specific integrated circuit, and the number of steps of the test data is calculated. Is calculated, and whether the integrated circuit for a specific application or the test data is good or bad is determined based on the calculated result.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of a drawing inspection device used for implementing the drawing inspection method for an application-specific integrated circuit of the present invention. In Figure 1, CP
U11 is for controlling the operation of the whole drawing inspection device, and is directly connected to the CPU 11 via the bus 12.
Memory access (DMA) controller 13, large capacity data file 14, working memory 1
5, a keyboard 16 and a display device 17 are also connected.

The data file 14 stores, as data, a circuit diagram of the designed application-specific integrated circuit, as well as logical data of the application-specific integrated circuit and test data prepared for testing. It is stored. At the time of inspection of the application-specific integrated circuit, the data file 1 is operated by operating the keyboard 16 to obtain the logic data of the application-specific integrated circuit and its test data.
4 and stores it in the work memory 15, and the drawing process described later is executed on the work memory 15,
The result is returned to the data file 14.

FIG. 2 shows a block diagram of an example of a designed application specific integrated circuit 21 to be inspected. This application-specific integrated circuit 21 has a memory controller 22 as a main element, and has four input pins 21a, 21b, 21c,
21d and two output pins 21e and 21f. The clock signals CL are input to the input pins 21a-21d from the test data prepared in advance.
K, address signal ADS, memory enable signal M /
IO and read / write signal R / W are input, and output signals BRDY and RDY of the memory controller 22 are output to output pins 21e and 21f.

FIG. 3 is a timing chart showing an example of respective signal waveforms at the input / output pins 21a-21f of FIG. Hereinafter, the drawing inspection method of the present invention will be described in detail with reference to the flowcharts of FIGS. 4 to 10 and the block diagrams of FIGS.

FIG. 4 is a schematic flow chart of an application specific integrated circuit inspection drawing. Prior to the execution of the drawing inspection, for example, it is assumed that the application-specific integrated circuit having the configuration shown in FIG. 2 is designed, and its logical data and test data are stored in the data file 14. When the keyboard 16 is instructed to start drawing inspection while the configuration diagram of the application-specific integrated circuit shown in FIG. 2 is displayed on the display device 17 shown in FIG.
In response to this, 1 accesses the data file 14, reads the logical data in step S1 of FIG. 4, and stores it in a predetermined area of the memory 15. Next, in step S2, the test data previously created and stored in the data file 14 for the inspection of the ASIC 21 is read and loaded into the memory 15. When the logic data and the test data have been read from the file 14 into the memory 15, the process proceeds to the next step S3 and the drawing operation described in detail below is executed, and the result is stored in the file 14 in step S4. Output and save.

FIG. 5 is a flow chart showing the drawing inspection step S3 of FIG. 4 in detail.
First, in step S5, the input signal to the special purpose integrated circuit 21 is inspected, in the next step S6, the output signal from the special purpose integrated circuit 21 is inspected, and in the next step S7, the memory 15 is detected. The number of test data loaded in is checked, and in the last step S8, the device selection is performed in the order of validity of device selection. These steps S5
Details of -S8 will be described below.

FIG. 6 is a detailed flowchart of the input signal inspection in step S5 shown in FIG. Figure 6
In the first step S51, a signal that can be input to the application specific integrated circuit 21 is extracted from the logic data stored in the memory 15. In the example of FIG. 2, the signal groups CLK, ADS, supplied to the input pins 21a-21d,
M / IO and R / W are extracted as input signals. In the case of the configuration shown in FIG. 1, the algorithm used in the logic simulator is stored in the data file 14 in advance, and the signal that can be an input can be extracted by reading and executing the algorithm in step S51. You can

Next, the process proceeds to step S52 and step S52.
The test data corresponding to the signal that can be the input obtained at 51 is read from the memory 15. The input signals CLK, ADS, M / IO, R / W and the test data corresponding to them thus extracted are displayed on the display device 17 as shown in FIG. 3, for example.

Next, in step S53, each of the signals CLK, ADS, M / IO, and R / W that can be input is searched to determine whether or not there is a description of both "0" and "1". To check. As a result of this check, when both input signals include both "0" and "1" as in the case of FIG. 3, the process proceeds to step S54, and the result of "test input is OK" is obtained. And is recorded in the data file 14. On the contrary, if even one of the input signals does not satisfy the condition that both "0" and "1" are described, the process proceeds to step S55 and the result of "defective test input" is obtained. Will be recorded. In this way, the input signal is inspected.

FIG. 7 shows a detailed flow chart for detecting the output signal in step S6 of FIG. Here, as in the case of the input signal inspection in FIG. 6, the first step S
At 61, a signal which can be an output from the application specific integrated circuit 21 is first extracted from the logic data stored in the memory 15. In the example of FIG. 2, the signals BRDY and RDY appearing at the output pins 21e and 21f are extracted as output signals. An example of the waveforms of these output signals is shown in FIG.

Next, the process proceeds to step S62, and step S
It is checked whether or not each of the signals that can be the output obtained at 61 includes a predetermined expected value. The meaning of this expected value is the value of the output that the circuit element should take at a predetermined timing with respect to a predetermined input. For example, in a 2-input AND gate of a logic gate, H and L of two inputs are respectively set. It is one of two values H and L for the combination of values. Considering the case of the output signals BRDY and RDY in FIG. 3, at a predetermined time point t, the address signal ADS input to the memory 22 is "1", the memory I / O signal M / IO is "0", and the reading is performed. The output BRDY is "1" and the output RDY is "0" with respect to the input condition that the / write signal R / W is "0".

Next, in step S63, each of the test data BRDY and RDY that can be output is searched, and all possible values are extracted. For example AND
In the gate circuit, the values that the output can take are H and L, and in the 3-status circuit having the output enable input, H, L,
There are three values of Z. If the signal input is grounded here, L,
There are two values of Z. These possible values are determined by the constituent circuit elements of the designed application-specific integrated circuit,
It is stored in advance in the data file 14.

On the other hand, if there is no expected value in step S62, the process proceeds to step S64 and an error of "no expected value" is set, and the result is recorded in the data file 14.
Next, in step S65, each test data
The expected value of the data is searched and the pin 21e
Regarding whether there are both the possible values “L” and “H”, and regarding whether there is both the possible values “L” and “H” regarding the pin “21f”, and if both are satisfied, The result of "output signal OK" is obtained in step S66, and this is recorded in the data file 14. On the other hand, if the expected value is not within the range of possible values, step S67.
The error of "expected value deficiency" is output and is recorded in the data file 14.

FIG. 8 is a detailed flowchart showing the verification operation of the number of logical steps of the test data executed in step S7 of FIG. First, in step S71, the circuit scale of the application-specific integrated circuit designed from the logic data loaded in the memory 15 is calculated. As a factor representing the circuit scale, there is an equivalent gate number, for example. The number of equivalent gates can be easily calculated from the logical data stored in the memory 15, for example. The equivalent gate number calculated in this way is set to A and stored in the memory 15.

Next, in step S72, the memory 15
Valid test data from the test data loaded in
The number of data, that is, the number of all test steps.
It is set as B and stored in the memory 15.

Next, in step S73, the evaluation signal C is calculated from the values A and B. Here, it is assumed that C = B / A, where the equivalent gate number A and the required test step number B are proportional. Here, in the next step S74, the value of C is compared with a preset reference value. If C is greater than or equal to this reference value, the process proceeds to step S75 and the content of the test data O
The result of K is output and recorded in the data file 14. On the other hand, if C is less than or equal to the reference value, step S76.
Then, the result of the impossibility of the content of the test data is output and is recorded in the data file 14. For example, (1) A
Is 140 gates and B is 100 steps, C = 0.7
(2) If A has 100 gates and B has 150 steps, then C = 1.5. Here, if the reference value is set to 1.0, (1) fails and (2) passes.

FIG. 9 is a detailed flow chart for verifying device selection such as a gate array used in the designed application specific integrated circuit in step S8 of FIG. That is, the purpose is to select a device having a circuit scale that matches the circuit scale of the designed application-specific integrated circuit. If the circuit scale of the designed application-specific integrated circuit is significantly smaller than the circuit scale of the selected device, it causes waste and raises the cost, and if it is large, the device cannot be manufactured.

First, the memory 15 storing the logic data of the designed special purpose integrated circuit is accessed to access the number of input pins (the number of inputs) of the special purpose integrated circuit.
The number of output pins (output number) and the number of input / output pins (input / output number) are sequentially extracted in steps S81, S82, and S83. Next, in step S84, the number of equivalent gates indicating the circuit scale is calculated. This is step S71 in FIG.
It may be calculated in the same manner as.

Next, some device candidates that can be used for the application-specific integrated circuit designed in step S85 are selected, and then in steps S86 and S87, this step S8 is selected.
The optimum device is obtained from the input / output conditions and the equivalent gate number obtained in 1-S84. FIG. 10 is a table showing the relationship between a plurality of devices, their input / output conditions, and the number of equivalent gates. For example, assuming that the designed application-specific integrated circuit has 12 input pins, 6 output pins, and an equivalent gate number of 130 gates, device 2 and device 4 are used as devices satisfying all the conditions from FIG. It is possible. (I)
That is, it is found that the devices 1-4 can be used by first searching for a device having an equivalent gate number of 130 or more. (II) Next, when searching with 12 or more input pins, devices 2 and 4 are searched.
And is obtained. Therefore, when the logical product of the search results of (I) and (II) is taken, it can be seen that the devices 2 and 4 can be used. However, since the number of equivalent gates of the device 2 is half that of the device 4 and the number of output pins and the number of input / output pins are small, step S87 is performed from the viewpoint of cost performance.
In this case, the device 2 is set as the optimum device.

Next, in step S88, it is checked whether or not the specified device is the optimum device. If the device is the optimum device, the result is recorded as "device OK" in the data file 14 in step S89, and the result is recorded. If not, an instruction to "use device 2" is output via the display device 17 in step S90.

FIG. 11 is a block diagram showing the structure of an application specific integrated circuit 30 having three pins 31, 32 and 33. Of these, pin 31 is an input pin, pin 32 is an input / output pin, and 33 is an output pin. The application-specific integrated circuit 30 includes an AND circuit 34, a circuit 35, and a buffer circuit 3.
6 and the inverter 37, the pins 31 and 32 are detected when a signal which can be an input is extracted from the logic data in step S51 in the flowchart of the input signal inspection in FIG. Therefore, it is checked whether or not there is a description of "0" and "1" for all the signals that can be input of test data for these pins 31 and 32.

FIG. 12 shows five pins 41, 42, 43, 4
4 is a block diagram showing a configuration of an application-specific integrated circuit 40 having 4, 45. FIG. Of these, pins 41, 42, 43
Is an input pin, pin 44 is an input / output pin, and 45 is an output pin. The application-specific integrated circuit 40 includes a circuit 46, a buffer circuit 47, and an AND circuit 48. When a signal that can be output is extracted from the logic data in step S61 in the flowchart of the inspection of the output signal of FIG. Four
5 is detected. Therefore, it is checked whether or not there is an expected value for all the signals that can be the output of the test data for the pins 44 and 45.

Next, the signal output from the logical data
Extract the possible values for the output. The pin 44 has L and Z (high impedance) values, and the pin 45 has L and H values.

According to the above embodiment, the four processes S5-S8 are used in the flowchart of FIG. 5, but depending on the purpose of the drawing inspection, if one or two or more of these processes are executed, it can be used for a specific purpose. The target part of the integrated circuit can be determined. For example, it is possible to perform the inspection of the application-specific integrated circuit only by the inspection steps S5 and S6 of the input signal and the output signal.

Further, when all four processes S5-S8 are executed, the order of each need not be the same as the order of the embodiment described, and can be freely selected. Also, load the logical data and test data in the data file 14
I went to the internal memory from, but without using the data file,
For example, the necessary data may be read into the internal memory from an external database.

Further, in the verification of the number of test data shown in FIG. 8, the relationship between the number of steps of the test data and the number of equivalent gates was simply obtained as the ratio C between them by a linear operation, but the present invention is not limited to this. For example, it may be obtained by non-linear calculation.

In the device selection flow of FIG. 9, the device to be used is specified when the designated device is not the optimum device in step S89, but when the designated device is the optimum device, it is equivalent to the optimum device. If there is a device, it may be indicated as device compatibility.

[0039]

As described above in detail, according to the drawing method of the application-specific integrated circuit of the present invention, sufficient and accurate drawing can be automatically performed without depending on human senses.
It is possible to automate inspection, improve efficiency, and improve reliability.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a drawing inspection apparatus for executing a drawing inspection method according to the present invention.

FIG. 2 is a block diagram showing an example of an application-specific integrated circuit which is an object of inspection.

FIG. 3 is a signal waveform diagram of input / output signals of the application-specific integrated circuit of FIG. 2 and test data corresponding to them, which is loaded from a data file of FIG. 1 into a memory.

FIG. 4 is a flowchart showing an overall flow of a drawing inspection method of an application-specific integrated circuit.

FIG. 5 is a flowchart of a main part of a drawing inspection method.

FIG. 6 is a flowchart for inspecting input test data.

FIG. 7 is a flowchart for inspecting an output signal of an ASIC.

FIG. 8 is a flowchart for verifying the number of steps of test data of the designed application-specific integrated circuit.

FIG. 9 is a flowchart for verifying suitability for a specified device to realize a designed application-specific integrated circuit.

FIG. 10 is a diagram showing an example of a device selection table.

FIG. 11 is a block diagram illustrating another example of a designed application-specific integrated circuit.

FIG. 12 is a block diagram illustrating yet another example of a designed application-specific integrated circuit.

[Explanation of symbols]

11 ... CPU, 12 ... Bus, 13 ... DMA, 14 ... Data file, 15 ... Memory, 16 ... Keyboard, 17 ...
Display device, 21 ... Integrated circuit for specific application, 21a-21
d ... input pin, 21e-21f ... output pin, 22 ... memory controller, S3 ... inspection step, S5 ... input signal inspection, S6 ... output signal inspection, S7 ... test data number inspection, S8 ... Device selection inspection drawing, 30 ... Special purpose integrated circuit, 40 ... Special purpose integrated circuit.

Claims (6)

[Claims] 1. A logic data of a designed application-specific integrated circuit is stored, test data for testing the designed application-specific integrated circuit is stored, and among the stored logic data, Evaluate the data of the predetermined attribute, evaluate the data of the predetermined attribute of the test data, based on the results of the evaluation of the logical data and the test data, the design content and test data of the application-specific integrated circuit A method for inspecting an integrated circuit for a specific purpose, characterized in that at least one of the evaluations of the contents is performed. 2. The logic data of the designed application-specific integrated circuit is stored, test data for testing the designed application-specific integrated circuit is stored, and the test data can be an input from the logic data. Application specific integration characterized by extracting all signals and determining whether or not the contents of the test data corresponding to the extracted signals include both logic levels "0" and "1" Circuit inspection method. 3. The logic data of the designed application-specific integrated circuit is stored, test data for testing the designed application-specific integrated circuit is stored, and the test data can be output from the logic data. A method for detecting an application-specific integrated circuit, which comprises extracting all signals and determining whether or not an expected value is included in the content of the test data corresponding to the extracted signals. 4. The logic data of the designed application-specific integrated circuit is stored, test data for testing the designed application-specific integrated circuit is stored, and output from the logic data. Is extracted, and it is judged whether or not the test data satisfies the extracted value for the corresponding signal, and the drawing method of the application-specific integrated circuit. 5. The logic data of the designed application-specific integrated circuit is stored, and test data for testing the designed application-specific integrated circuit is stored, and the logic data is used to store the test data. The circuit scale of the application-specific integrated circuit was calculated, the number of steps of test data was counted, and how much the number of steps of test data had with respect to the calculated circuit scale was calculated. A method for inspecting an integrated circuit for specific purposes, which comprises determining whether the integrated circuit for specific applications and test data is good or bad based on the result. 6. The logic data of the designed application-specific integrated circuit is stored, test data for testing the designed application-specific integrated circuit is stored, and the logic data is used to store the test data. Calculate the number of equivalent gates of the application-specific integrated circuit, count the number of steps of test data, and determine how much the number of steps of test data has with respect to the calculated number of equivalent gates. A method for inspecting an application-specific integrated circuit, which comprises determining whether the application-specific integrated circuit and the test data are good or bad based on the calculated result.