JPH0785251B2 - Printed circuit board CAD system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention is a printed circuit board CAD (Computer Aided Design).
More specifically, the present invention relates to the structure of a wiring board model corresponding to surface mount components in automatic wiring.

[Prior Art] A so-called printed circuit board CAD system, which automatically designs wirings of a printed circuit board with the help of a computer, has been well known. This kind of printed circuit board CAD
In many of the automatic wiring processes of the system, when searching a path between two points between a certain component pin (start point) to be connected and another component pin (end point), a board model called a cell map is constructed, The open / closed state of cells on the way from the start point to the end point is sequentially examined, and it is determined whether or not there is a path through which the cells can reach the end point.

A cell is a small square-shaped area that is formed by equally dividing the wiring area of the printed circuit board vertically and horizontally at the wiring grid spacing (normally 2.54 / 5 mm spacing when two wirings pass between pins). Is the smallest unit of. Each cell has an existing wiring, a component pin, a through hole, a wiring prohibition or an empty state on the front and back of the printed circuit board.

[Problems to be Solved by the Invention] However, the board model in the automatic wiring of such a printed board CAD system was considered on the premise of a printed board on which a DIP type IC is mounted, and has been used recently. When the above-mentioned board model is applied to a printed circuit board on which surface mounted components (SMD) are mounted, the following problems occur, making it difficult to find a path.

1.27 mm, 0.8 mm, 0.6 mm, etc. between the component pins of surface mount components
Since it is different from the DIP type IC, it is not possible to maintain a predetermined clearance for wiring evenly divided cells on the entire printed circuit board.

In the surface mount component, the component pin does not ride on the center of the cell as shown in FIG. 9, so that lead-in wiring to the pin is not performed correctly (wiring separates from the pin).

Since the surface mount components can be attached to both surfaces of the printed circuit board at the same position, the conventional XY wiring technique using cells cannot be used as it is.

The object of the present invention is made in view of such a point, and in the case of constructing a wiring board model corresponding to a surface mount component in a printed circuit board mounting the surface mount component, and performing automatic wiring based on the model. Is to provide a printed circuit board CAD system that solves the above problems.

[Means for Solving the Problems] In order to achieve such an object, in the present invention, a means for creating a substrate model by the following procedure 1 or 2 and a substrate by the procedure 2 below. And a search means for searching by the model.

[Process 1] First, secure a data area for the wiring area of the board, determine the wiring conditions for the entire board from the board specifications, initialize all cell preambles under those conditions, and generate component pin string data from the graphic database. Then, it is extracted whether the component pin is a component pin row that is not on the wiring grid or a component pin row of a surface mount component, and the direction, spacing, component pin pad shape and clearance of the extracted component pin row are extracted. From, the wiring condition around the component pin is obtained, registered in the condition table, the wiring condition number is embedded in the cell preamble of all cells including the component pin row, and the above operation is repeated until the database search is completed. When the search is complete, scan the graphics database again and see if there are empty cells for all cells in the wiring area, or The state such as whether it is already occupied by another signal line or through hole is extracted, and that state is set in the wiring channel status and through hole indicator according to the cell preamble.

[Processing 2] The scanning point (x, y) is initialized (start point (x ₀ , y ₀ )).

The cell number of cell preassembly at the scanning point (x, y) is obtained.

The wiring condition number of the cell number is extracted from the cell preamble.

The wiring grid spacing, the wiring direction, etc. at the scanning point (x, y) are extracted from the wiring condition table.

Based on these data, the wiring board status data string indicates the board status of the channel with the scanning point (whether there is a failure)
Take out.

If there is no fault, the scanning point is updated according to the wiring direction, and the operation described above is performed.

Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings.
FIG. 1 is a diagram showing a board model structure in a printed board CAD system according to the present invention. The board model manages the wiring conditions and the wiring conditions for each of the front and back sides of the board in basic cell units that are created by dividing the wiring area of the actual board into basic grid intervals (usually 2.54 mm).

The cell wiring conditions are the conditions regarding the wiring grid spacing, the wiring grid origin, and the wiring direction for one basic cell. It is possible to have different wiring conditions locally on the substrate.

The wiring state of the cell indicates the position of the wiring and the through hole of the path discovered by the path failure and the search such as the component pin on the board and the existing wiring.

The board model consists of a cell preamble (for front and back) 10, wiring channel status (for front and back) 20, and a through-hole indicator 30.

In the cell preamble 10, areas having different wiring conditions are defined on the front surface and the back surface (hereinafter referred to as A surface and B surface).

In the wiring channel status 20, according to the wiring condition given by the cell preamble, the inside of the basic cell is divided into strips at a wiring grid interval (this is called a wiring channel) as shown in FIG. And the search path is managed.

The through hole indicator 30 is marked with the position of the through hole found by the path search.

FIG. 3 is a diagram showing the data structure of the cell preamble. As shown in FIG. 3 (a), wiring condition numbers are assigned to each of the basic cells (i, j) in the basic lattice spacing unit on each of the A surface and the B surface (FIG. (B)). The address of the wiring condition data record 12 is stored in the wiring condition table 11 (FIG. 6C) pointed by the condition number.

Each wiring condition data record 12 has a structure as shown in FIG. That is, the wiring basic lattice spacing,
Wiring grid origin X coordinate, wiring grid origin Y coordinate, wiring grid division number, wiring direction (horizontal or vertical), number of wiring channels,
Wiring channel start address (starting address of the memory storing the contents of the wiring channel), component pin pad shape number, and the like.

A procedure for constructing such a board model will be described. FIG. 4 is a construction flow.

First, a data area for the wiring area of the board is secured.

The wiring conditions for the entire board are obtained from the board specifications, and all cell preambles are initialized under the conditions.

The component pin string data is generated from the graphic database, and the data that meets the following conditions is extracted.

(A) Component pins are not on the wiring grid, (b) Surface mount components The wiring conditions around the component pins are determined from the direction, spacing, pin pad shape and clearance of the extracted pin row, and the conditions Register in the table.

The maximum / minimum coordinates (this is called min-max) of the component pin row are obtained, and the wiring condition number is embedded in the cell preamble of that portion.

The above operation is repeated until the database search is completed.

When the search is completed, the figure database magic is scanned again, and the component pins, through holes, and existing wiring data are extracted.
Build wiring channel status, through-hole indicator according to cell preamble.

The board model is constructed by the above procedure. Then, the system performs a path search based on the created board model. The operation of the path search in one direction will be described below. FIG. 5 is a flow of one-way route search.

The scanning point (x, y) is initialized (start point (x ₀ , y ₀ )).

The cell number of cell preassembly at the scanning point (x, y) is obtained.

The wiring condition number of the cell number is extracted from the cell preamble.

The wiring grid spacing, the wiring direction, etc. at the scanning point (x, y) are extracted from the wiring condition table.

Based on these data, the wiring board status data string indicates the board status of the channel with the scanning point (whether there is a failure)
Take out.

If there is no fault, the scanning point is updated according to the wiring direction, and the operation described above is performed.

If there is a failure, this search ends.

A heterogeneous wiring grid board model can be created as described above, and automatic wiring work can be performed based on this board model.

FIG. 6 is an explanatory view for explaining the printed wiring design process designed in this way. Fig. 7 shows Fig. 6 (d).
FIG. In the figure, dots 61 indicate grid points for through holes. Although the component pins of the surface mount component SMD do not lie on the standard wiring grid points, it is easy to see how the wiring has been successfully drawn into the center of the component pins.

[Effects of the Invention] As described above, according to the present invention, it is possible to create a heterogeneous wiring grid board model, and the following effects are obtained by using the created board model in automatic wiring. To be

In automatic wiring of a printed circuit board on which surface mount components are mounted, (a) component pins do not violate clearance even if they are off-grid (when they are not on the wiring grid points given as the board specifications). Wiring can be drawn in the center.

(B) Even if the pin row 1 of the component is orthogonal to the wiring direction (arrow) as shown in FIG. 8 (a), wiring is made to the pins according to the pin row direction as shown in FIG. 8 (b). Can be retracted.

(C) Wiring is easy for the same reason as the above (b) even if different portions are on the same surface and opposite surfaces.

mm pitch connector and DI on off-grid
Wiring can be easily performed for P-shaped parts as well.

[Brief description of drawings]

FIG. 1 is a diagram showing a substrate model structure in a printed circuit board CAD system according to the present invention, FIG. 2 is an explanatory diagram for explaining a case where different types of wiring grids are mixed, and FIG. 3 is a data structure of a cell preamble. FIG. 4, FIG. 4 is a flow chart for constructing a board model, FIG. 5 is a flow path search flow, and FIG.
FIG. 7 is an explanatory view for explaining the design process of the printed wiring according to the present invention, FIG. 7 is a partially enlarged view of FIG.
The figure shows the relationship between the direction of component pins and the wiring direction.
The figure shows the relationship between the wiring grid and the component pin spacing. 10 …… Cell preamble, 20 …… Wiring channel status, 30 …… Through hole indicator, 11 …… Wiring condition table, 12 …… Wiring condition data record.

Claims (1)

[Claims] 1. A printed circuit board CAD for constructing a board model, checking whether or not there is a failure in each cell, and judging whether or not there is a path capable of connecting between two points, and performing automatic wiring processing. In the system, a printed circuit board is provided with a means for creating a board model by the procedure of the following processing 1 and a searching means for performing a wiring path search by the board model by the procedure of the processing 2 below. CAD system. [Process 1] First, secure a data area for the wiring area of the board, determine the wiring conditions for the entire board from the board specifications, initialize all cell preambles under those conditions, and generate component pin string data from the graphic database. Then, it is extracted whether the component pin is a component pin row that is not on the wiring grid or a component pin row of a surface mount component, and the direction, spacing, component pin pad shape and clearance of the extracted component pin row are extracted. From, the wiring condition around the component pin is obtained, registered in the condition table, the wiring condition number is embedded in the cell preamble of all cells including the component pin row, and the above operation is repeated until the database search is completed. When the search is complete, scan the graphics database again and see if there are empty cells for all cells in the wiring area, or The state such as whether it is already occupied by another signal line or through hole is extracted, and that state is set in the wiring channel status and through hole indicator according to the cell preamble. [Process 2] scanning point (x, y) to initialize (as a starting point (x0, y _0)). The cell number of cell preassembly at the scanning point (x, y) is obtained. The wiring condition number of the cell number is extracted from the cell preamble. The wiring grid spacing, the wiring direction, etc. at the scanning point (x, y) are extracted from the wiring condition table. Based on these data, the wiring board status data string indicates the board status of the channel with the scanning point (whether there is a failure)
Take out. If there is no fault, the scanning point is updated according to the wiring direction, and the operation described above is performed.