JPH0785686A - Fuse circuit and redundant memory circuit - Google Patents

Abstract

(57) [Summary] [Object] To provide a fuse circuit capable of generating a reliable redundant control signal without increasing a through current when a fuse element is not cut. [Structure] A resistor R1, a fuse element f, and a resistor R2 are connected in series between a high potential side power source VCC and a low potential side power source VSS. The nodes C and D at both ends of the fuse element f are
It is connected to the input side of Ex-OR 12. And Ex-OR
The redundancy control signal S is output from the output side of 12. When the fuse element f is not cut, its resistance RF is equal to the resistance R1,
The resistance R1 is set to be sufficiently smaller than the resistance R2, and the resistance R1 is set to be sufficiently larger than the resistance R2 (R
F << R2 << R1).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fuse circuit and a redundant memory circuit. In recent years, with the increase in capacity of semiconductor memories, the importance of redundant circuit technology has been increasing. Although the redundant circuit technology includes a spare decoder, a fuse circuit is generally used for the spare decoder. The fuse circuit is required to generate a reliable signal when the fuse element is cut and to reduce the through current when the fuse element is not cut.

[0002]

2. Description of the Related Art With the increase in capacity of semiconductor memories, it is rapidly becoming difficult to manufacture a memory cell array having no defective bits at all. In particular, when a memory developed using a new circuit technology is mass-produced, the defect level of the initial lot is inevitably high, so that the yield is greatly reduced.

Therefore, a redundant circuit in which a proper number of redundant rows and columns are added to a normal memory cell array in advance and the defective rows are repaired by replacing the redundant rows and columns with defective rows and columns. Technology is adopted.

In a general redundant circuit technology, in addition to redundant rows and columns, a spare decoder for selecting the redundant rows and columns is provided. That is, the row address redundancy circuit is composed of an appropriate number of redundancy rows and a spare decoder for selecting the redundancy rows. Further, the column address redundancy circuit is composed of an appropriate number of redundancy columns and a spare decoder for selecting the redundancy column.

The spare decoder is programmed so that when a normal memory cell array has a defective bit, a selection operation is performed on an address signal corresponding to that row (or column). Therefore, when an address including a defective bit (defective address) is input, the spare decoder outputs a selection prohibition signal (redundancy control signal) to a regular row (or column) decoder. Then, based on the selection prohibition signal, the row (or column) decoder selects a redundant row (or column) instead of the normal row (or column), so that the defective address is relieved.

Programming of such a spare decoder is generally performed using a fuse circuit. In FIG.
1 shows a conventional fuse circuit.

The fuse circuit 51 is composed of a fuse element f, a resistor r, and a buffer formed by a CMOS inverter 52. One end of the fuse element f has a high potential side power source V
Connected to CC and the other end through resistor r
It is connected to the. A node A between the fuse element f and the resistor r is connected to the input side of the inverter 52. The inverter 52 is composed of a PMOS transistor 53 and an NMOS transistor 54, and is connected to the high potential side power supply VCC and the low potential side power supply VSS. Then, from the node B on the output side of the inverter 52, the redundant control signal S
Is output.

Here, when the fuse element f is not cut,
The resistance RF is set to be sufficiently smaller than the resistance r (RF << r). Therefore, the fuse element f
When not disconnected, as shown in FIG. 9, the node A is pulled to the high potential side power supply VCC and becomes H level, and the node B, that is, the redundancy control signal S becomes L level.

On the other hand, when the fuse element f is cut, the resistance RF of the fuse element f becomes almost infinite (r <<
RF ≈∞), as shown in FIG. 9, the node A is pulled down to the L level by the low potential side power supply VSS, and the node B, that is, the redundancy control signal S goes to the H level.

For example, when RF ≈∞, r = 1 MΩ, and the threshold voltage Vth = 1 V of each MOS transistor 53, 54 of the inverter 52, each node A, B and each power supply voltage VC
The relationship between C and VSS is as shown in FIG.

As described above, based on the H level redundancy control signal S generated when the fuse element f is cut, as described above, the row (or column) decoder replaces a normal row (or column) with a redundant signal. The row (or column) is selected and the defective address is relieved.

[0012]

By the way, there are two methods of cutting the fuse element f: a method of supplying a large current (electrical fuse) and a method of using a laser (laser fuse). The element f may not be completely cut. In this case, when the resistance RF when the fuse element f is cut close to the resistance r (RF ≈r), the level of the node A becomes a level determined by resistance division by the resistances RF and r, as shown in FIG. .

Then, as shown in FIG. 11, the voltage of the node A rises with the rise of the high-potential-side power supply voltage VCC, and when the high-potential-side power supply voltage VCC is below a predetermined value VP, the node B is at the L level ( = VSS). When the high-potential-side power supply voltage VCC is equal to or higher than the predetermined value VP, both MOS transistors 5
When both 3 and 54 are turned on, the level of the node B becomes indefinite (RF = r = 1MΩ, Vth = 1V).

The level of the node B, that is, the redundancy control signal S
When becomes undefined, the row (or column) decoder cannot perform the selection operation, and thus the defective address cannot be relieved.

In order to solve this problem, the resistance r should be made sufficiently smaller than the resistance RF when the fuse element f is cut. However, if the resistance r is reduced, there is a problem that a through current that flows from the high potential side power supply VCC to the low potential side power supply VSS via the fuse element f and the resistance r increases when the fuse element f is not cut.

The present invention has been made to solve the above problems, and an object thereof is to generate a reliable redundant control signal without increasing a through current when a fuse element is not cut. It is to provide a fuse circuit which can be performed.

[0017]

According to a first aspect of the present invention, there is provided a first resistor, a fuse element, and a first resistor connected in series between a high potential side power source and a low potential side power source. The gist of the present invention is to include a second resistor having a lower resistance, and an exclusive OR circuit in which nodes at both ends of the fuse element are connected to the input side and the presence or absence of fuse blown is output from the output side.

[0018]

Therefore, when the fuse element is not cut, the through current flowing from the high potential side power source to the low potential side power source through the first resistor, the fuse element and the second resistor can be suppressed to a small value.

Further, when the fuse element is not cut, the nodes at both ends of the fuse element are pulled to the low potential side power supply and become L level, and the output of the exclusive OR circuit becomes L level. On the other hand, when the fuse element is completely blown, its resistance becomes almost infinite.
Each node at both ends of the fuse element is connected to the high-potential side power source and the low-potential side power source, respectively. It becomes L level, and the output of the exclusive OR circuit becomes H level. Further, even when the fuse element is not completely blown when the fuse element is blown and its resistance becomes close to the first resistance, as in the case where the fuse element f is completely blown, the exclusive OR circuit The output goes high. Also, when the fuse element is cut,
When the fuse element is not completely cut and its resistance becomes close to the second resistance, the output of the exclusive OR circuit becomes the L level as in the case where the fuse element is not cut.

Therefore, even if the fuse element is not completely blown, the output of the exclusive OR circuit (that is, whether or not the fuse is blown) does not become indefinite.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A fuse circuit according to an embodiment of the present invention will be described below with reference to FIG. In this embodiment, the same components as those of the fuse circuit 51 of the conventional example shown in FIGS. 8 to 11 have the same reference numerals, and detailed description thereof will be omitted.

The fuse circuit 11 of this embodiment comprises a fuse element f, resistors R1 and R2, and an Ex-OR 12. Between the high potential side power supply VCC and the low potential side power supply VSS,
The resistor R1, the fuse element f, and the resistor R2 are connected in series. Nodes C and D at both ends of the fuse element f are Ex-O
It is connected to the input side of R 12. And Ex-OR 12
The redundant control signal S is output from the output side of the.

Here, when the fuse element f is not cut,
The resistance RF is set to be sufficiently smaller than the resistances R1 and R2, and the resistance R1 is set to be sufficiently larger than the resistance R2 (RF << R2 << R1). Therefore, when the fuse element f is not cut, the high potential side power supply VCC
Through the resistor R1, the fuse element f, and the resistor R2, the through current flowing to the low-potential-side power supply VSS can be suppressed.

In the fuse circuit 11, when the fuse element f is not cut off, both nodes C and D are pulled to the L level by the low potential side power supply VSS, and the output of the Ex-OR 12, that is, the redundancy control signal S is at the L level. become.

On the other hand, when the fuse element f is completely blown when the fuse element f is blown, its resistance RF becomes almost infinite (R2 << R1 << RF≈∞), so that the node C has a high potential. It is pulled to the H level by the side power supply VCC, and the node D is pulled to the L level by the low potential power supply VSS. As a result, the output of the Ex-OR 12, that is, the redundancy control signal S is H
Become a level.

Further, when the fuse element f is cut off, the fuse element f is not completely cut off and its resistance RF is changed to the resistance R1.
Even when the voltage is close to (RF ≈ R1), the node C is connected to the high-potential-side power source V as in the case where the fuse element f is completely cut.
The node D is pulled to the H level and the node D is pulled to the low potential side power supply VSS to be the L level. As a result, Ex-OR 12
Output, that is, the redundancy control signal S becomes H level.

Further, when the fuse element f is cut off, the fuse element f is not completely cut off and its resistance RF is changed to the resistance R2.
(RF.apprxeq.R2), both nodes C and D are pulled to the low potential side power supply VSS and become L level, and the redundancy control signal S becomes L level, as in the case where the fuse element f is not cut.

Therefore, even if the fuse element f is not completely cut, the redundancy control signal S does not become indefinite. As described above, in the fuse circuit 11 of this embodiment, the through current when the fuse element is not cut does not increase, and the indefinite redundancy control signal S is not generated.

FIG. 2 shows the fuse circuit 11 shown in FIG.
A circuit embodied by an OS transistor is shown. still,
2, the same components as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

The node D is connected to the gate of the NMOS transistor 21, and the node C is connected to the NMOS transistor 22.
Is connected to the gate. The nodes C and D are connected to the node E via the MOS transistors 21 and 22. The node E is connected to the low-potential-side power supply VSS via the resistor R3 and also connected to the node F via the latch circuit 23. The latch circuit 23 is composed of CMOS inverters 23a and 23b whose input and output are connected. Then, the redundancy control signal S is output from the node F.

Here, the resistance R3 is determined to be sufficiently smaller than the resistance R2 (R3 << R2 << R
1). Therefore, when the fuse element f is completely blown and its resistance RF becomes almost infinite (R3 << R2 << R1 << RF≈∞) when the fuse element f is cut, each node C, D and each power supply The relationship between the voltages Vcc and Vss is as shown in FIGS. 3 and 4 (note that RF ≈∞, R1 = 1 MΩ,
R2 = 500 kΩ, the threshold voltage Vth = 1 V of each MOS transistor forming the MOS transistors 21 and 22 and the inverters 23a and 23b.

Further, when the fuse element f is cut off, the fuse element f is not completely cut off and its resistance RF is changed to the resistance R1.
(RF≈R1), the levels of the nodes C and D become levels determined by resistance division by the resistors R1, RF and R2, as shown in FIG.

At this time, as shown in FIG. 5, the level difference between the nodes C and D depends on the MOS transistors 21 and 2.
If the threshold voltage Vth is equal to or lower than the threshold voltage Vth of 2 (= 1 V), the node E is pulled to the H level by the high-potential-side power supply VCC by the resistor R3, and the node F, that is, the redundancy control signal S goes to the L level. RF ≒ ∞, R1 = 1MΩ, R2 = 500
kΩ, the threshold voltage Vth of each MOS transistor constituting each MOS transistor 21, 22 and each inverter 23a, 23b Vth = 1V).

As shown in FIG. 5, each node C, D
When the level difference between the MOS transistors 21 and 22 becomes equal to or higher than the threshold voltage Vth (= 1 V) of the MOS transistors 21 and 22, the NMOS transistor 22 is turned on and the nodes D and E become the same level. S becomes H level.

Therefore, even if the fuse element f is not completely blown, the redundancy control signal S is always at the H or L level and does not become indefinite. The present invention is not limited to the above embodiment, but may be carried out as follows.

1) As shown in FIG. 6, each resistor R1, R2
Are constituted by NMOS transistors 31 and 32.
That is, the on-resistances of the NMOS transistors 31 and 32 having their gates and drains connected to each other are used as the resistors R1 and R2.

2) As shown in FIG. 7, the resistors R1 and R2 are
Are constituted by PMOS transistors 41 and 42.
That is, the on-resistances of the PMOS transistors 41 and 42 having their gates and drains connected to each other are used as the resistors R1 and R2.

[0038]

As described above in detail, according to the present invention, it is possible to provide a fuse circuit capable of generating a reliable redundant control signal without increasing the through current when the fuse element is not cut. It has the excellent effect that

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment embodying the present invention.

FIG. 2 is a circuit diagram in which the embodiment shown in FIG. 1 is embodied by a MOS transistor.

FIG. 3 is an explanatory diagram for explaining the operation of the embodiment shown in FIG.

FIG. 4 is a characteristic diagram showing characteristics of the embodiment shown in FIG.

5 is a characteristic diagram showing characteristics of the embodiment shown in FIG.

FIG. 6 is a diagram showing an example in which resistors R1 and R2 of the embodiment shown in FIG.
It is the circuit diagram which replaced with the S transistor.

FIG. 7 is a diagram showing a case where resistors R1 and R2 of one embodiment shown in FIG.
It is the circuit diagram which replaced with the S transistor.

FIG. 8 is a circuit diagram of a conventional example.

FIG. 9 is an explanatory diagram for explaining the operation of the conventional example.

FIG. 10 is a characteristic diagram showing characteristics of a conventional example.

FIG. 11 is a characteristic diagram showing characteristics of a conventional example.

[Explanation of symbols]

 VCC High-potential side power supply VSS Low-potential side power supply R1 First resistor R2 Second resistor 12 Exclusive OR circuit (Ex-OR) f Fuse element S Redundancy selection signal C, D node

Claims (2)

[Claims] 1. A first resistor (R1) connected in series between a high potential side power source (VCC) and a low potential side power source (VSS).
, A fuse element (f), a second resistor (R2) having a lower resistance than the first resistor (R1), and nodes (C, D) at both ends of the fuse element (f) are connected to the input side and output Exclusive OR circuit (12) that outputs whether or not the fuse is blown from the side
And a fuse circuit. 2. The fuse circuit according to claim 1 is prepared for the number of bits of an address, a defective address is recorded depending on whether or not the fuse element (f) of each fuse circuit is cut, and the exclusive address of each fuse circuit is recorded. A redundant memory circuit characterized by outputting a defective address by using the output of the logical sum circuit (12).