JPH0786105A - Ultrafine semiconductor device - Google Patents

Abstract

PURPOSE:To prevent erroneous determination of chip position due to erroneous recognition of a chip by providing identification patterns different from those of neighboring chips at the opposite ends of the chip. CONSTITUTION:Each chip 1a, 1b, 1c having elongated ultrathin profile is provided, in the vicinity on the opposite short sides thereof, with identification patterns 2, 3. The identification pattern can be formed simultaneously with wiring by photolithography or dry etching using an aluminium film. Alphanumeric character, figure, symbol, etc., may be employed as the identification pattern so long as they are different for each chip. Different identification patterns 2, 3 are preferably spaced apart as far as possible from each other. This arrangement allow positive identification of chip in a short time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a long semiconductor device in which the entire image cannot be recognized by a single image processing, and in particular, it is an extremely fine semiconductor device capable of distinguishing adjacent chips when a sheet is expanded after dicing. The present invention relates to a semiconductor device.

[0002]

2. Description of the Related Art In the process of assembling a semiconductor device, a wafer is diced, a sheet is expanded and separated into individual chips, and then the chips are mounted on a package or a lead frame. At that time, the image processing apparatus is used to recognize the individual chips arranged in the wafer, and the position (X,
It is necessary to correct (Y, θ), but in the case of a long chip (for example, 50 mm × 0.5 mm) as in the case of a one-dimensional CCD image sensor, the entire image can be grasped by one image processing. Since it cannot be done, the image processing is performed in multiple times.

That is, as shown in FIG.
Identification patterns 2 and 3 are provided on both left and right ends of each chip 1a, 1b, 1c, and the identification pattern 2 of the chip 1a is recognized in the recognition area 4 by the first image processing.
The camera of the image processing apparatus is moved, and in the second image processing, the recognition pattern 3 provided at the right end of the chip is recognized in the recognition area 4 as shown in FIG. Y, θ) was corrected.

By the way, when different types of chips are formed on the same wafer, different identification patterns may be formed for each chip in order to identify each chip (for example, Japanese Patent Laid-Open No. 61-142734). Issue).

[0005]

As shown in FIG. 5, in the general chip 1d, the influence of the deviation in the θ direction is negligible [y _{1 in} (a) of FIG. 5], but In the case of elongated chips 1 having greatly different dimensional ratios (for example, 1: 100), the influence of the deviation in the θ direction becomes very large [y _{2 in} (b) of FIG. 5], and therefore, FIG.
As shown in (b), the first image processing and the second image processing may be performed on different chips. However, in the conventional technique, the same pattern is given to all the chips, and in such a case, it is not possible to recognize that the chips are adjacent chips, and it is determined that θ correction is not necessary. As a result, the device is mounted in the state of θ deviation, which causes defective products. In order to eliminate such inconvenience, it has been attempted to increase the recognition area per chip, but such a method increases man-hours and deteriorates workability. Was not.

Further, the means disclosed in Japanese Patent Application Laid-Open No. 61-142734 gives different types of patterns to different types of chips, and it is only necessary to give one pattern to one chip. Therefore, it is impossible to detect the positional deviation of a long chip by this conventional technique.

[0007]

In order to solve the above problems, according to the present invention, both ends of a chip are distinguished from other chips adjacent to each other so that they can be distinguished from other chips on the wafer. Provided is an ultrafine semiconductor device having an application pattern.

[0008]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a plan view showing a first embodiment of the present invention. As shown in the figure, each chip is provided in the vicinity of both ends on the short side of the chips 1a, 1b, 1c, ... Having an extremely fine and long shape so that each chip can be distinguished from other chips. Further, identification patterns 2 and 3 different from those of other chips are formed. These identification patterns are, for example, using an aluminum film for forming wiring,
It can be formed at the same time as the wiring by the photolithography method and the dry etching method. The shape of the identification pattern may be any of alphanumeric characters, figures, symbols, etc. as long as it is different for each chip. Further, the positions of the two identification patterns 2 and 3 are preferably separated as far as possible in order to detect the θ deviation of the chip with the highest possible accuracy, but they are not necessarily formed at the extreme ends of the chip. do not have to.

Next, with reference to FIG. 2, a method of aligning the semiconductor chip of this embodiment will be described. In the present embodiment, it is assumed that the chip is elongated and that only a part of the chip falls within the visual field of the recognition area. First, the identification pattern 2 at one end of the chip is captured in the recognition area 4 and is recognized [(a) in FIG. 2]. Next, the optical recognition means is moved to the other end side of the chip to recognize the identification pattern 3 [(b) of FIG. 2]. If this recognition pattern 3 is the same as the above identification pattern 2, there is no deviation in the θ direction,
One chip has been correctly identified. When the chip has a deviation in the θ direction, different identification patterns are recognized in 2 and 3 as shown in FIG. In this case, both ends of different chips are recognized, and θ correction is performed on the chip or the chip mounting device side so that the same identification pattern as the identification pattern 2 is recognized [(c) of FIG. 2]. Recognition ends.

It is actually difficult to give different identification patterns to all the chips in the wafer as the number of chips increases. However, when it is clear that the amount of deviation in the θ direction is within a certain range, it is possible to reduce the types of identification patterns by repeatedly forming the identification patterns in a range slightly wider than this range. For example up to 4
If there is a possibility that a chip shift in the θ direction may occur, the identification pattern may be repeated every five or more chips that are larger than this.

FIG. 3 is a plan view showing a second embodiment of the present invention. In this embodiment, the identification pattern 2 at one end and the identification pattern 3 at the other end are different for each chip. Further, the identification patterns are made different between chips whose long sides are adjacent to each other. With this configuration, it is possible to obtain the same effect as in the case of the previous embodiment, and it is possible to easily identify right and left in each chip alone. Further, between chips whose short sides are adjacent to each other, the identification patterns given to the adjacent ends can be made different. By doing so, it is possible to eliminate erroneous recognition between chips whose short sides are in contact with each other.

[0012]

As described above, in the semiconductor device according to the present invention, the identification pattern different for each chip is formed at both ends of the short side of the elongated chip. Recognize each identification pattern,
By determining whether or not the two identification patterns belong to the same chip, it is possible to surely identify the chips in a short time, and prevent erroneous determination of the chip position due to erroneous chip recognition. become. At present, for example, in a one-dimensional CCD image sensor, the number of pixels tends to make the chip more slender, but the present invention addresses this tendency. The above configuration improves productivity and greatly improves yield. Can be planned.

[Brief description of drawings]

FIG. 1 is a plan view of a first embodiment of the present invention.

FIG. 2 is a plan view for explaining a positioning operation for the first embodiment of the present invention.

FIG. 3 is a plan view of the second embodiment of the present invention.

FIG. 4 is a plan view of a conventional example.

FIG. 5 is a plan view for explaining the problems of the conventional example.

FIG. 6 is a plan view for explaining the problems of the conventional example.

[Explanation of symbols]

 1, 1a, 1b, 1c, 1d Chip 2 Identification pattern 3 Identification pattern 4 Recognition area

Claims (4)

[Claims] 1. An ultrafine semiconductor device, wherein an identification pattern different from that of another chip whose long sides are adjacent to each other on the wafer is provided on both ends of the chip. 2. The ultrafine semiconductor device according to claim 1, wherein the identification patterns at both ends of the same chip are different from each other. 3. The chip having the same identification pattern appears every few chips on the wafer.
The ultrafine semiconductor device described. 4. The ultrafine semiconductor according to claim 1, wherein, on the wafer, between chips whose ends on the shorter side are adjacent to each other, the identification patterns at the adjacent ends are different from each other. apparatus.