JPH0786519A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the capacitance of a capacitive element from fluctuation owing to variability of a wafer process in a semiconductor device wherein the capacitive element is formed on the basis of many unit capacitive elements formed on a chip. CONSTITUTION:A plurality of unit capacitive elements Cu are formed in a capacitor formation area A, and a plurality of the unit capacitive elements Cu are connected to form a predetermined capacitance capacitive element C. The plurality of the unit capacitive elements Cu constituting the capacitive element C are disposed such that they are uniformly dispersed to the center CE of the capacitor formation area A.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a plurality of capacitors formed on a chip.

In recent years, semiconductor devices have become more highly integrated,
A large number of active and passive devices are arranged on the chip.
Further, in such a semiconductor device, there is an increasing demand for higher accuracy in its operation. For this reason, it is necessary to improve the accuracy of the passive elements formed in large numbers on the chip.

[0003]

2. Description of the Related Art An example of a 4-bit charge redistribution type A / D converter will be described with reference to FIG. Capacity 8C, 4C, 2C,
1C has its capacity value set by weighting by 2,
The ratio of the capacitance values is set to 8: 4: 2: 1.

That is, the capacity 8C is composed of 8 unit capacities, the capacity 4C is composed of 4 unit capacities, and the capacity 2
C is composed of two unit capacitors, and the capacitor 1C is composed of one unit capacitor.

One terminal of each of the capacitors 8C, 4C, 2C and 1C is connected to the chopper type comparator 1. The chopper type comparator 1 is composed of an inverter circuit 2 and an N-channel MOS transistor Trc connected in parallel with the inverter circuit 2. Then, the on / off operation of the transistor Trc is controlled based on the operation of the successive approximation control unit (not shown).

The other terminals of the capacitors 8C to 1C have switching circuits 3a to 3c controlled by the successive approximation control unit.
3d, each of which is switched so that the reference power supply voltage AVR, the analog input signal Ain that fluctuates between the reference power supply voltage AVR and the level of the ground G, or the level of the ground G is input. .

The operation of the A / D converter configured as described above will be described. First, the switching circuits 3a to 3d are controlled by the analog input signal Ain based on the control of the successive approximation control unit.
And the sampling operation is performed, and each capacitor 8C to
A charge corresponding to the capacitance value is stored in 1C.

At this time, the transistor Trc is turned on, and the terminals of the capacitors 8C to 1C on the side of the chopper type comparator 1 are maintained at the threshold value Vth of the chopper type comparator 1. Each of the capacitors 8C to 1C has the threshold value Vth,
Charged based on the voltage difference between the analog input signal Ain,
Negative charges are accumulated on the electrodes of the capacitors 8C to 1C on the chopper type comparator 1 side.

Next, the transistor Trc is turned off, and the switching circuits 3a to 3d are sequentially switched under the control of the successive approximation control unit. At that time, the level of the input terminal of the inverter circuit 2 is changed, whereby the inverter circuit is changed. The output signal OUT output from 2 becomes a 4-bit digital signal.

In the A / D converter as described above, the capacitors C8 to C1 are required to perform 4-bit A / D conversion, and the capacitors 8C to 1C are laid out as shown in FIG.

That is, 16 unit capacitors are arranged on the chip 4 in a grid pattern and occupy a half of the area.
The unit capacity of 8 pieces constitutes the capacity 8C. In addition, capacity 8C
Adjacent to, the unit capacity 4C is formed by four unit capacities arranged in the vertical direction.

A capacitor 2C composed of two unit capacitors and a capacitor 1C composed of one unit capacitor are arranged adjacent to the capacitor 4C. In addition, 1 adjacent to the capacitor 1C
The individual unit capacitance is the dummy capacitance D.

Each of the capacitors has a well formed on the substrate and a poly-S formed on the well via an oxide film.
and i layer.

[0014]

As one means for improving the conversion accuracy of the A / D converter as described above, the capacitance value of each of the capacitors 8C to 1C formed on the chip 4 is exactly 8: It may be set to 4: 2: 1.

The capacitances 8C to 1C formed on the chip 4 can be easily set to the above capacitance ratio if the unit capacitances have the same value. However, due to variations in the wafer process, the capacitance value of each unit capacitance was
It may fluctuate from one to the other, increasing or decreasing. For example, when variations occur such that the capacitance value of each unit capacitance increases from the right direction to the left direction on the chip 4, the capacitance value of the capacitance 8C becomes smaller than the set value, and the capacitance values of the capacitances 1C and 2C. Is larger than the set value.

Then, it becomes difficult to accurately set the capacitance value of each capacitance 8C to 1C to the capacitance ratio. As a result,
There is a problem that the conversion accuracy of the A / D converter is lowered.

An object of the present invention is to provide a semiconductor device which forms a capacitance based on a large number of unit capacitances formed on a chip, and which can suppress the variation of the capacitance value of the capacitance due to variations in wafer process. To do.

[0018]

FIG. 1 is a diagram for explaining the principle of the present invention. That is, a plurality of unit capacitance elements Cu are formed in the capacitance forming area A, and a plurality of the unit capacitance Cu are connected to form a capacitance element C having a predetermined capacitance value. The plurality of unit capacitance elements Cu forming the capacitance element C are arranged so as to be evenly distributed with respect to the center CE of the capacitance formation region A.

In addition, as shown in FIG.
The plurality of unit capacitance elements 8C1 to 8C8 constituting the above are arranged point-symmetrically with respect to the center CE of the capacitance forming region A1.

[0020]

Function: A plurality of unit capacitance elements Cu constituting the capacitance element C
Are arranged so as to be evenly distributed with respect to the center CE of the capacitance forming region A, so that variations in the capacitance value of each unit capacitive element Cu due to variations in the wafer process are offset.

[0021]

FIG. 2 shows a first embodiment embodying the present invention. Sixteen unit capacitors are formed in a grid pattern in the capacitor forming area A1 located in the central portion of the chip 4, and each unit capacitor constitutes a capacitor 8C, 4C, 2C, 1C. 1
The six unit capacitors are arranged in a substantially uniform range around the center CE of the chip 4.

The capacitor 8C is composed of eight unit capacitors 8C1-8C.
It is composed of C8, and the capacity 4C is four unit capacity 4C1.
.About.4C4, and the capacitance C2 is two unit capacitances 2
It is composed of C1 and 2C2, and the capacity C1 is composed of one unit capacity.

The unit capacitors 8C1 to 8C8 are arranged so that two units are located symmetrically with respect to the center CE, for example, the unit capacitors 8C1 and 8C8.
The unit capacitors 8C1 to 8C8 are connected in parallel by wiring (not shown) to form the capacitor 8C.

The unit capacitors 4C1 to 4C4 are arranged such that two units are located symmetrically with respect to the center CE, such as unit capacitors 4C1 and 4C4.
The unit capacitors 4C1 to 4C4 are connected in parallel by wiring (not shown) to form the capacitor 4C.

The unit capacitances 2C1 and 2C2 are the center C
The unit capacitors 2C1 and 2C2 are arranged in point symmetry with respect to E, and the unit capacitors 2C1 and 2C2 are connected in parallel by wiring (not shown) to form the capacitor 2C.

The capacitor 1C is arranged adjacent to the center CE, and the dummy capacitor D is arranged at a point symmetrical position with respect to the center CE of the capacitor 1C. Therefore, each capacity 8C
1C are arranged so that the respective unit capacitors constituting them are distributed point-symmetrically with respect to the center CE.

With such a configuration, even if variations occur in the capacitance value of the unit capacitance from one side of the chip 4 to the other side due to variations in the wafer process, the unit capacitances in the respective capacitances 8C to 2C are Since the chips 4 are arranged so as to be evenly distributed with respect to the center CE of the chip 4, the fluctuation of the capacitance value of each unit capacitance is such that the capacitances of the unit capacitances 8C1 and 8C8 complement each other. Offset.

Further, since the capacitance 1C is arranged adjacent to the center CE, the variation of the capacitance value due to the variation of the wafer process is small. Therefore, even if variations occur in the wafer process, it becomes easy to accurately set the capacitance values of the capacitors 8C to 1C. If each of these capacitors 8C to 1C is used in the A / D converter, A
The / D conversion accuracy can be improved.

Next, a second embodiment embodying the present invention will be described with reference to FIG. Capacitance forming areas A2 and A3 are arranged on both sides of the center CE of the chip 4. In each of the capacity forming areas A2 and A3, eight unit capacitors are arranged in two columns in the vertical direction. 4C, 2C, 1
C is constructed.

The capacitance 8C is composed of eight unit capacitances 8C1-8C.
It is composed of C8, and the capacity 4C is a unit capacity 4C1 to 4C.
4 and the capacitance C2 is a unit capacitance 2C1, 2C2.
The capacitor C1 is composed of one unit capacitor.

The unit capacitances 8C1 to 8C8 are arranged so as to be distributed point-symmetrically from the center CE in the capacitance forming regions A2 and A3, like the unit capacitances 8C1 and 8C8, respectively. 8C8 are connected in parallel by wiring (not shown) to form the capacitor 8C.

The unit capacitors 4C1 to 4C4 are arranged so as to be distributed point-symmetrically from the center CE in the capacitance forming regions A2 and A3, like the unit capacitors 4C1 and 4C4, respectively. 4C4 are connected in parallel by wiring (not shown) to form the capacitor 4C.

The unit capacitors 2C1 and 2C2 are arranged so as to be distributed point-symmetrically from the center CE in the capacitor forming regions A2 and A3, and the unit capacitors 2C1 and 2C2 are arranged.
Are connected in parallel by wiring (not shown), and the capacitance 2
C is constructed.

The capacitance 1C is the capacitance forming area A.
2, the dummy capacitor D is arranged in the vicinity of the center CE, and the dummy capacitor D is arranged in the capacitance forming region A3 at a point symmetrical position with respect to the center CE of the capacitor 1C.

Therefore, the capacitors 8C to 1C are arranged so that the unit capacitors forming them are distributed point-symmetrically with respect to the center CE. With such a configuration, even if variations occur in the capacitance value of the unit capacitance from one side to the other side of the chip 4 due to variations in the wafer process, each unit capacitance in each of the capacitances 8C to 2C
Since the chips are arranged in a point-symmetrical manner with respect to the center CE of the chip 4, for example, the unit capacitances 8C1 and 8C8 are the same.
Complement each other with the variation of the capacitance value, so that the variation of the capacitance value of each unit capacity is offset.

Further, since the capacitor 1C is arranged in the vicinity of the center CE, the variation of the capacitance value due to the variation of the wafer process is small. Therefore, even if variations occur in the wafer process, it becomes easy to accurately set the capacitance values of the capacitors 8C to 1C.

Next, a third embodiment embodying the present invention will be described with reference to FIG. In the capacity forming area A4 formed in the central portion of the chip 4, 64 unit capacitors are formed in a grid pattern, and each unit capacitor has a capacity of 32C, 16C, 8
C, 4C, 2C, 1C are configured. The 64 unit capacitors are arranged in a substantially equal range around the center CE of the chip 4.

The capacitor 32C is 32 unit capacitors 32C.
1 to 32C32, the capacity 16C is composed of 16 unit capacities 16C1 to 16C16, the capacity 8C is composed of 8 unit capacities 8C1 to 8C8, and the capacity 4C is composed of 4 unit capacities 4C1 to 4C4. And the capacitance C
2 is composed of two unit capacitors 2C1 and 2C2, and the capacitor C1 is composed of one unit capacitor.

The unit capacitors 32C1 to 32C32 are arranged in a point-symmetrical manner with respect to the center CE, such as the unit capacitors 32C1 and 32C32, and the unit capacitors 32C1 to 32C32 are wired (not shown). ) Are connected in parallel to form the capacitor 32C.

The unit capacitors 16C1 to 16C16 are arranged in a point-symmetrical manner with respect to the center CE, such as the unit capacitors 16C1 and 16C16, and the unit capacitors 16C1 to 16C16 are wired (not shown). ) Are connected in parallel to form the capacitor 16C.

The unit capacities 8C1 to 8C8 are arranged so as to be dispersed point-symmetrically with respect to the center CE, such as the unit capacities 8C1 and 8C8.
The capacitors 8C are formed by connecting C1 to 8C8 in parallel by wiring (not shown).

Similarly, the unit capacitors 4C1 to 4C4 are arranged so as to be dispersed point-symmetrically from the center CE, and the unit capacitors 4C1 to 4C4 are connected in parallel by wirings (not shown) to form the capacitor 4C. Is configured.

The unit capacitances 2C1 and 2C2 are the center C
The unit capacitors 2C1 and 2C2 are arranged so as to be distributed symmetrically with respect to E, and the unit capacitors 2C1 and 2C2 are connected in parallel by wiring (not shown) to form the capacitor 2C.

The capacitor 1C is arranged adjacent to the center CE, and the dummy capacitor D is arranged at a point symmetrical position with respect to the center CE of the capacitor 1C. Therefore, each capacity 32
C to 1C are arranged so that the respective unit capacities constituting them are distributed substantially evenly with respect to the center CE.

With such a configuration, even if the capacitance value of the unit capacitance fluctuates from one side of the chip 4 to the other side due to the variation of the wafer process, the unit capacitances of the respective capacitances 32C to 2C are reduced. Chip 4
Since they are arranged so as to be evenly distributed with respect to the center CE, the fluctuation of the capacitance value of each unit capacitance is offset.

Further, since the capacitance 1C is arranged adjacent to the center CE, the variation of the capacitance value due to the variation of the wafer process is small. Therefore, even if variations occur in the wafer process, it becomes easy to accurately set the capacitance values of the capacitors 32C to 1C. Then, if each of these capacitors 32C to 1C is used in an A / D converter having a 6-bit configuration, the A / D conversion accuracy can be improved.

In the above embodiment, the center CE of the chip 4 is
On the other hand, although the respective unit capacitors are arranged so as to be dispersed point-symmetrically, the center CE does not necessarily have to be the center of the chip 4, but may be the center of the capacitor formation region.

[0048]

As described above in detail, according to the present invention, in a semiconductor device in which a plurality of capacitive elements are formed based on a large number of unit capacitive elements formed on a chip, each capacitive element due to variations in wafer process It is possible to provide a semiconductor device capable of suppressing the variation of the capacitance value, which is an excellent effect.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a layout diagram of a unit capacitance showing the first embodiment.

FIG. 3 is a layout diagram of a unit capacitance showing a second embodiment.

FIG. 4 is a layout diagram of a unit capacitance showing a third embodiment.

FIG. 5 is a circuit diagram showing an example of a charge redistribution type A / D converter.

FIG. 6 is a layout diagram of a conventional unit capacitance.

[Explanation of symbols]

 A capacitance forming area C capacitance element Cu unit capacitance element CE center

Claims (2)

[Claims] 1. A capacitance element (C) having a predetermined capacitance value by forming a plurality of unit capacitance elements (Cu) in a capacitance forming region (A) and connecting a plurality of the unit capacitance elements (Cu). A semiconductor device to be formed, comprising a plurality of unit capacitance elements (C
u) is arranged so as to be evenly distributed with respect to the center (CE) of the capacitance forming region (A). 2. A plurality of unit capacitance elements (Cu) forming the capacitance element (C) are arranged in point symmetry with respect to the center (CE) of the capacitance formation region (A). The semiconductor device according to claim 1.