JPH0786548A - Image sensor - Google Patents

Abstract

(57) [Abstract] [Purpose] An image that can obtain a stable output signal with a small variation in the offset voltage included in the output signal.
Providing a sensor. A correction capacitor CA is provided between the drain of a transfer transistor TT arranged near the photodiode P and the gate of a reset transistor TR, and is arranged apart from the photodiode P. Of the adjacent transfer transistor TT and the reset transistor T
The shortage of the capacitance between the gate and the gate of R is compensated, while the source and the gate of the transfer transistor TT arranged apart from the photodiode P are provided. A correction capacitor CB is provided between them, and the amount of shortage is compensated for as compared with the capacitance between the source and gate of the adjacent transfer transistor TT arranged near the photodiode P. Therefore, the output signal does not differ for each pixel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image sensor used in an image reading apparatus such as a facsimile or an electronic copying machine, and more particularly to an image sensor having an improved offset level.

[0002]

2. Description of the Related Art Conventionally, as an image sensor of this type, a so-called 1 is constructed by arranging a plurality of light receiving elements in a straight line as disclosed in Japanese Patent Laid-Open No. 2-265362.
While forming a three-dimensional light receiving element array, several light receiving elements are set as one block, and the light receiving element array is made up of a plurality of blocks, and the light receiving elements are generated in each light receiving element according to the amount of reflected light from the document. One in which a readout transistor is connected in series to each light receiving element so that the charge is read out for each block, and a reset transistor for resetting the residual charge of the light receiving element is connected to the output side of the light receiving element. , Already known and well known.

FIG. 5 shows a circuit example of the conventional image sensor as described above, and FIG. 6 shows a timing chart for explaining the operation of the image sensor. Hereinafter, the image sensor will be generally described with reference to FIG. In this image sensor, when the image sensor receives the reflected light from the document and outputs a signal corresponding to the received light amount, in the so-called bright state, first, after the previous reset pulse ΦGR is output ( From the transfer pulse ΦGT (not shown) (see FIG. 6).
(See (a)) is applied to the transfer transistor TT, the photodiode P is in a state where charges corresponding to the amount of received light are generated (charge accumulation period), and the transfer transistor TT The drain potential of the drain voltage rises relatively rapidly as compared with the dark state described later (see FIG. 6C). Then, at the same time that the transfer pulse ΦGT is applied to the gate of the transfer transistor TT, the drain voltage of the transistor TT sharply rises by the voltage ΔV1 in synchronization with the rising of the transfer pulse ΦGT. This voltage ΔV1 is
This is called the feedthrough amount (or feedthrough voltage) and is due to the so-called feedthrough phenomenon which is well known in this type of circuit.

After that, the drain potential decreases exponentially until the drain and the source have the same potential, and the drain potential also corresponds to the feedthrough voltage in synchronization with the fall of the transfer pulse ΦGT. Then, the voltage drops abruptly and settles down to a constant voltage determined by the residual charge amount of the phototransistor P (see FIG. 6C). On the other hand, the transfer transistor T
The source potential of T gradually rises as the transfer pulse .PHI.GT rises, and sharply drops by the feedthrough voltage .DELTA.V3 when the transfer pulse .PHI.GT falls. After this,
When the reset transistor (not shown) provided inside the read IC 30 becomes conductive, the source potential temporarily drops to the GND potential (see FIG. 6D). After that, the source voltage of the transfer transistor TT rises from the previous GND potential by the feedthrough voltage .DELTA.V5 generated due to the reset transistor of the read IC 30 becoming non-conductive, and this voltage .DELTA.V5. Is the reference voltage of the output signal.

That is, the output voltage of the image sensor in the bright state is the voltage ΔV if the output voltage of the image sensor in the dark state is completely zero.
5 does not occur, the previous voltage ΔV5 is generated when the source potential Vs1 of the transfer transistor TT in consideration of the feedthrough voltage ΔV3 is taken after the transfer pulse ΦGT falls. Therefore, the output voltage of the image sensor includes Vs1-ΔV5 and so-called offset voltage. However, in reality, as will be described later, the output does not completely become zero even in the dark state. Therefore, if the output voltage in this dark state, that is, the offset voltage is VOF, the output value in the bright state is eventually , Vs1-ΔV5 minus the offset voltage VOF.

Then, when a reset pulse ΦGR is applied to the gate of the reset transistor TR and the residual charge of the photodiode P is cleared by conduction of the reset transistor TR, the drain voltage of the transfer transistor TT changes. It becomes GND potential, and then reset pulse ΦGR
With the falling edge of, the potential drops from the GND potential to the negative potential again (see FIG. 6C). Then, after this, the photodiode P returns to the charge storage state again, but if this charge storage state is the dark state (the state where no light is incident from the outside), the drain potential of the transfer transistor TT is set. Is gradually increased from the above-mentioned negative potential by the dark current of the photodiode P (a voltage change which is slower than the charge accumulation state in the bright state), and the transfer pulse ΦGT is transferred after an appropriate time. Gate of transistor TT
When the transfer pulse ΦGT rises, the drain potential changes to the feedthrough voltage ΔV.
A sharp rise of 2 (see FIG. 6C) causes a potential change to occur at the same timing as in the bright state described above, although there are differences in voltage level. The same applies to the source potential of the transfer transistor TT. Here, the output signal of the image sensor in the dark state is ideally zero, but in reality, some voltage is generated. This voltage is called an offset voltage, and in the example shown in FIG. 6, its magnitude VOF is VOF = Vs2−ΔV5
Becomes

By the way, the most important factor for determining the feedthrough amount is the gate-source capacitance CGS and the gate-drain in the transfer transistor TT and the reset transistor TR. Capacity between CGD
And the amplitude of the gate voltage, but especially the capacitance CG
S and CGD are greatly affected by the arrangement structure of the transfer transistor TT and the reset transistor TR. On the other hand, in the so-called line image sensor described above, if the resolution is relatively low, the physical arrangement of the photodiode P, the reset transistor TR and the transfer transistor TT is the same as in the equivalent circuit of FIG. Although they are arranged on substantially the same straight line, when a high-resolution image sensor is constructed, the interval between adjacent photodiodes P must be made as small as possible. Therefore, the reset transistor T having a relatively planar spread
If the R and the transfer transistor TT are made to have the same arrangement structure as the low-resolution image sensor, the adjacent reset transistor TR and transfer transistor TT must be partially overlapped with each other. For this reason,
In practice, a structure is adopted in which the reset transistors TR and the transfer transistors TR are arranged in a so-called zigzag pattern.

That is, referring to FIG. 5, assuming that the positions of the reset transistor TR and the transfer transistor TT of the photodiode P on the right end are the illustrated positions, the reset transistor of the photodiode P immediately adjacent to the left of the reset transistor TR and the transfer transistor TT. T
The R and the transfer transistor TT are arranged just below the positions where these two transistors TR and TT are shown in the figure, and the reset transistor TR and the transfer transistor TT immediately adjacent to the left side are arranged in the left-right direction ( In FIG. 5, in the left-right direction of the paper), the 2 at the right end described above
The two transistors TR and TT are arranged substantially the same as each other, and the reset transistor TR and the transfer transistor TT are arranged so that their positions in the vertical direction (vertical direction in the plane of FIG. 5) are different every other pixel.

[0009]

However, when the reset transistors TR and the transfer transistors TT are arranged in a zigzag manner as described above, the reset transistors T are arranged.
A signal line connecting the R and the transfer transistor TT and the photodiode P (a line for transmitting the charge output from the photodiode P), and a reset transistor TR.
And a gate connected to the gate of the transfer transistor TT.
The length of the line is different for each pixel. by the way,
The gate-drain capacitance and the gate-source capacitance explained above.
Since the inter-capacitance is almost determined by the so-called coupling between the signal line and the gate line described above, the fact that the lengths of the signal line and the gate line are different for each pixel is different from the gate.
This means that the drain capacitance and the gate-source capacitance differ from pixel to pixel. For this reason,
Since the drain voltage is different for each pixel, the offset voltage ΔVOF is different for each pixel, that is, the output signal of the image sensor is different for each pixel.
There is a problem that it cannot be used as an image signal unless the output signal is corrected.

The present invention has been made in view of the above circumstances, and provides an image sensor capable of obtaining a stable and reliable output signal with a small variation in offset voltage.

[0011]

According to a first aspect of the present invention, there is provided an image sensor having a light receiving element array including at least a plurality of light receiving elements, and a first storage for storing electric charges transferred from the light receiving elements. A capacitor, a first switching element that is provided in the same number as the plurality of light receiving elements and transfers charges generated in the light receiving element to the first storage capacitor, and a residual charge of the light receiving elements that is provided in the same number as the plurality of light receiving elements. An image sensor including a second switching element for discharging the electric charge, and a signal wiring extending from the first switching element for transmitting the electric charge of the light receiving element, and an electric wire extending from the second switching element. The correction capacitor is provided between the control wiring for transmitting the control signal for controlling the operation of the second switching element and the control wiring. In particular, it is preferable that the correction capacitor is formed by allowing the signal wiring and the control wiring to face each other in parallel.

An image sensor according to a third aspect of the present invention includes a light receiving element array including at least a plurality of light receiving elements and a first light receiving element for accumulating charges transferred from the light receiving elements.
Storage capacitors of the same number and the same number of the light receiving elements as the plurality of light receiving elements,
Of the plurality of light receiving elements, and a second switching element which is provided in the same number as the plurality of light receiving elements and discharges the residual charges of the light receiving elements, the image sensor extending from the first switching element. A compensation capacitor is provided between a signal wiring for transmitting electric charges and a control wiring extending from the first switching element and transmitting a control signal for controlling the operation of the first switching element. Is. In particular, it is preferable that the correction capacitor is formed by allowing the signal wiring and the control wiring to face each other in parallel.

An image sensor according to a fifth aspect of the present invention is a light receiving element array including at least a plurality of light receiving elements and a first light receiving element for accumulating charges transferred from the light receiving elements.
Storage capacitors of the same number and the same number of the light receiving elements as the plurality of light receiving elements, the first charge transferring the charges generated in the light receiving elements to the first storage capacitor.
Switching element and a second switching element provided in the same number as the plurality of light receiving elements and discharging residual charges of the light receiving elements, the light receiving element, the first switching element and the second switching element. The arrangement is such that the first and second switching elements connected to the light receiving element are arranged in the vicinity of the light receiving element, and the first and second switching elements connected to the light receiving element are the light receiving element. In an image sensor in which a pair of first and second switching elements and a plurality of elements which are arranged at an interval such that they can be arranged are alternately arranged adjacent to each other, the image sensor is arranged in the vicinity of the light receiving element. A signal wiring extending from the first switching element and transmitting the electric charge of the light receiving element, and a control extending from the second switching element to control the operation of the second switching element No. is made by providing a correction capacitance between the control wiring to be transmitted. In particular, it is preferable that the correction capacitor is formed by allowing the signal wiring and the control wiring to face each other in parallel.

According to a seventh aspect of the present invention, in an image sensor, at least a light-receiving element array including a plurality of light-receiving elements and a first light-receiving element for accumulating charges transferred from the light-receiving elements.
Storage capacitors of the same number and the same number of the light receiving elements as the plurality of light receiving elements,
Switching element and a second switching element provided in the same number as the plurality of light receiving elements and discharging residual charges of the light receiving elements, the light receiving element, the first switching element and the second switching element. The arrangement is such that the first and second switching elements connected to the light receiving element are arranged in the vicinity of the light receiving element, and the first and second switching elements connected to the light receiving element are the light receiving element. An image sensor in which a pair of first and second switching elements and a pair of first and second switching elements that are spaced apart from each other are alternately arranged adjacent to each other. A signal wire extending and transmitting a charge of the light-receiving element, and a control signal extending from the first switching element and transmitting a control signal for controlling the operation of the first switching element. Those formed by providing a correction capacitance between the use wiring. In particular, it is preferable that the correction capacitor is formed by allowing the signal wiring and the control wiring to face each other in parallel.

[0015]

In the image sensor according to the present invention, the correction capacitor is formed between the signal wiring and the control wiring so that the signal wiring and the control wiring are connected between the signal wiring and the control wiring. Since the correction capacitance is added to the capacitance originally formed in, the shortage of the capacitance before the addition of the correction capacitance is compensated for, and the output signal is reduced due to the shortage of capacitance. There will be no unevenness for each pixel.

In the image sensor according to the fifth and sixth aspects of the present invention, the signal wiring extending from the first switching element and the control wiring extending from the second switching element arranged near the light receiving element are provided. The correction capacitor provided therebetween is an electrostatic capacitance formed between the signal wiring extending from the first switching element and the control wiring extending from the second switching element, which are arranged near the light receiving element. However, the shortage due to the proximity to the light receiving element is compensated for as compared with the similar capacitances in the adjacent first and second switching elements, and therefore the adjacent capacitances due to the shortage of the capacitances are caused. The non-uniformity of the output signal with the pixel is eliminated.

In the image sensor according to the seventh and eighth aspects of the present invention, the first sensor is arranged apart from the light receiving element.
The correction capacitance provided between the signal wiring and the control wiring extending from the switching element is the signal wiring and the control wiring extending from the first switching element that is arranged apart from the light receiving element. The electrostatic capacity formed between the adjacent first switching element and the similar electrostatic capacity in the adjacent first switching element compensates for the shortage, and therefore, in the adjacent pixel due to the shortage of the electrostatic capacity. The unevenness of the output signal is eliminated.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An image sensor according to the present invention will be described below with reference to FIGS. Here, FIG. 1 is an equivalent circuit diagram of the image sensor according to the present invention, FIG. 2 is an equivalent circuit diagram of one pixel of the image sensor according to the present invention, and FIG. 3 shows an operation of the image sensor according to the present invention. FIG. 4 is a timing diagram for explaining, and FIG. 4 is a plan view showing an embodiment of the arrangement structure of the main part of the image sensor according to the present invention.

First, the circuit configuration of the image sensor according to the present invention will be described with reference to FIG. This image sensor includes a light-receiving element array 1, a charge transfer section 2, a charge reset section 3, a matrix wiring section 4, a common signal line 5, a gate pulse generating circuit 6, a reading IC 7, and a correction. The capacitors C A and C B are the main constituent elements. The light-receiving element array 1 is formed by arranging N photodiodes P as light-receiving elements linearly on a substrate (not shown) made of an insulating material such as glass to form one block. Is provided linearly.

A charge transfer section 2 and a charge reset section 3 are connected to the light receiving element array 1. This charge transfer unit 2
Is composed of the same number of transfer transistors TT as the above-mentioned photodiodes P, the drain of the transfer transistor TT is connected to the anode of the photodiode P, and the source of the transfer transistor TT is connected. Are connected to the matrix wiring section 4 described later. A thin film transistor is used as the transfer transistor TT.
Furthermore, each photodiode P has a charge reset unit 3
Are connected. That is, the charge reset unit 3
Is composed of the same number of reset transistors TR as the number of photodiodes P. The drain of the reset transistor TR is connected to the anode side of the photodiode P, while the source side is grounded. Has been done. A thin film transistor is used as the reset transistor TR.

In this embodiment, the transfer transistor T
The thin film transistors of T and the reset transistor TR have the same characteristics, and the W / L thereof is preferably about 8 to 18.

The matrix wiring section 4 connects the sources of the transfer thin film transistors TT at the same position in each block. For example, the first photodiode P (FIG. 1) of the first block is connected. The source of the transfer thin film transistor TT connected to the photodiode located at the right end of the block labeled "1st" in FIG.
First photo diode of another block (photo diode located at the rightmost end of each block in FIG. 1)
It is connected to P. The matrix wiring section 4 is connected to n common signal lines 5 equal to the number of blocks, and is connected to the reading IC 7 via the common signal lines 5. A wiring capacitance CL is provided between each common signal line 5 and the ground, and the photodiode P transferred through the transfer transistor TT is used.
The charge from is accumulated. In this embodiment, the wiring capacitance CL is 10 to 100 pF.
The degree is a suitable value.

The reading IC 7 reads the potential of the common signal line 5 generated by the accumulation of electric charges in the wiring capacitance CL, and selectively outputs it as an image signal acquired by each photodiode P in time series. To do. The gate pulse generation circuit 6 has a gate pulse Φ for making the transfer transistor TT and the reset transistor TR conductive.
GT and ΦGR are generated, and the gates of the transfer transistors TT are connected together in the same block to the output stage thereof, and the gates of the reset transistors TR are transferred. Similar to the transistor TT, the blocks are collectively connected to each block.

In this image sensor, the transfer transistors TT and the reset transistors TR are arranged every other pixel in a so-called zigzag pattern in the lateral direction of the paper in FIG. That is, assuming that the numbers of the transfer transistor TT and the reset transistor TR at the right end in FIG. 1 are 1, and the transfer transistor TT and the reset transistor TR which are adjacent to each other are sequentially numbered, odd-numbered transfer transistors TT and TT The reset transistor TR is arranged relatively close to the photodiode P, and the even-numbered transfer transistors TT and the reset transistor TR are arranged apart from the photodiode P. Between the photodiode T and the photodiode P, The space is provided so that a set of transfer transistor TT and reset transistor TR can be arranged just between the photodiode P (a specific arrangement example will be described later).

The correction capacitor CA is connected between the drains of the even-numbered transfer transistors TT and reset transistors TR and the gate of the reset transistor TR. The correction capacitor CB is connected between the source and the gate of the odd-numbered transfer transistor TT.

FIG. 2 shows an equivalent circuit per pixel in the above-mentioned image sensor, and the contents thereof will be briefly described below with reference to FIG. It should be noted that the description of the components already described in FIG. 2 will be omitted, and hereinafter, the components not shown in FIG. 1 will be mainly described. Photodiode P is
Since it has its own parasitic capacitance Cp,
It is shown as being connected between the anode of cathode P and the cathode. In this embodiment, the parasitic capacitance Cp is about 1 pF. Further, the reading IC 7 is an amplifier 8
Has a transfer transistor TT on its input side.
Source and the drain of the reset MOS transistor 9 are connected. The source side of the reset MOS transistor 8 is grounded, and a gate signal from a pulse signal generating circuit (not shown) is input to the gate to make it conductive so that the wiring capacitance CL is reduced. It is designed to discharge residual charges. In the figure, the gate-drain capacitance C
The letters TR or TT in parentheses after GD and the gate-source capacitance CGS represent the capacitance in the reset transistor TR or the transfer transistor TT, respectively. Is.

Next, an example of the specific arrangement structure of the image sensor will be described with reference to FIG. The photodiode P is sandwiched between the upper transparent electrode 10, a common lower electrode 11 facing the upper transparent electrode 10 and common to each photodiode P, and these two electrodes 10, 11. And a photoelectric conversion layer (not shown), and the common lower electrode 11 is bonded to the substrate. The reset transistor TR and the transfer transistor TT connected to the photodiode P on the right side of the paper in FIG. 4 are located at the lower side (lower side of the paper in FIG. 4) of the photodiode P and the reset transistor TR and the transfer transistor TT. Transistor TT
However, they are arranged at intervals such that they can be arranged one by one.

In FIG. 4, a connection wiring 12a formed in a straight line extends toward the reset transistor TR from the anode electrode 12 connected to the anode of the photodiode P on the right side of the drawing. The drain electrode portions 13a and 13b connected to the drains of the reset transistor TR and the transfer transistor TT are formed at the tip of the drain electrode portions 13a and 13b. On the other hand, the reset transistor T on the right side of FIG.
A source electrode 15 is arranged on the source region 14 of R. The source electrode 15 is extended to the channel region side (right side of the source electrode 15 in FIG. 4),
This extended portion serves as a channel light-shielding portion 16 so as to block light from entering the channel region.
Further, the channel light-shielding portion 16 is also extended to the lower side (lower side of the paper surface in FIG. 4) and also functions as the channel light-shielding portion of the transfer transistor TT. The channel light-shielding portion 16 extends below the transfer transistor TT and is connected to the ground wiring 17.

The reset transistor T on the right side of FIG.
The gate electrode 18 connected to the R gate is extended upward (upper surface of FIG. 4), and a gate electrode connecting line 19 is provided.
It is connected to the. This gate electrode connecting line 19 is shown in FIG.
Passing between the reset transistor TR and the transfer transistor TT which are adjacent to each other on the left side, and arranged in the left-right direction (left-right direction on the paper surface in FIG. 4), the gate of the reset transistor TR on the left side in FIG. 4 is also connected. Is. Further, the source electrode 20 connected to the source of the transfer transistor TT on the right side of FIG.
It is connected to a common signal line 5 arranged in the left-right direction (left-right direction on the paper in FIG. 4) on the lower side. Also,
The gate electrode 20 and the gate electrode connecting line 21 arranged in the left-right direction (the left-right direction of the paper in FIG. 4) below the transfer transistor TT and the gate electrode connection line 21 are constant in the front-back direction of the substrate (front-back direction of the paper in FIG. 4). It is in a state of intersecting at a substantially right angle with a gap of.

On the other hand, below the photodiode P located on the left side in FIG. 4, a reset transistor TR and a transfer transistor TT connected to the photodiode P are arranged. The anode electrode 12 of the photo diode P located on the left side extends downward and is connected to the drain electrode 22a of the reset transistor TR,
Further, the drain electrode 22a extends downward and is connected to the drain electrode 22b of the transfer transistor TT. The portion extending from the drain electrode 22a of the reset transistor TR to the drain electrode 22b of the transfer transistor TT is located below the reset transistor TR in the left-right direction (front-back direction in FIG. 4). The electrode connection wiring 19 intersects with the substrate 19 in a substantially right-angled state at regular intervals in the front-back direction of the substrate (the front-back direction of the paper in FIG. 4).

The reset transistor T on the left side of FIG.
The R source electrode 23 is extended to the gate side, and
It is similar to the source electrode 15 of the reset transistor TR on the right side that the channel light-shielding portion 24 is formed by extending to the gate side of the transfer transistor TT. Figure 4
The source electrode 25 of the transfer transistor TT on the left side is extended to the lower side (the lower side of the drawing in FIG. 4), and like the source electrode 20 of the transfer transistor TT on the right side of FIG. It is connected to the.

In the above structure, a part of the connection wiring 12a extending from the photodiode P on the right side of FIG. 4 and connected to the drain electrode 13a of the reset transistor TR and the gate of the reset transistor TR. Since it is parallel to the wiring portion B extending from (refer to the portion surrounded by the alternate long and two short dashes line in FIG. 4), electrostatic so-called coupling occurs, and electrostatic capacitance is formed in this portion. As a result, the gate-drain capacitance CGD of the reset transistor TR on the right side of FIG. 4 is smaller than that of the case where the reset transistor TR is arranged immediately below the photodiode P. It will only be big.

On the other hand, a portion c extending from the drain electrode 22a of the reset transistor TR to the drain electrode 22b of the transfer transistor TT on the left side of the paper of FIG. 4 and a portion having a portion parallel to this portion c intersect at a substantially right angle. -A correction capacitor CA is formed between the gate electrode connection line 19 and
This correction capacitance CA is added to the gate-drain capacitance CGD of the reset transistor TR on the left side of FIG. Although the correction capacitor CA is mainly formed by the above-mentioned portion, in FIG. 4, a drain portion 22b of the reset transistor TT on the left side and a wiring portion B extending from the gate electrode 18 of the reset transistor TR on the right side are formed. Capacitance is also generated by the parallel portion (see the area surrounded by the two-dot chain line in FIG. 4), and the correction capacitance C
Be part of A. The correction capacitance CA is set so as to be substantially equal to the amount by which the gate-drain capacitance CGD in the reset transistor TR on the right side of FIG. The gate-drain capacitance CGD is substantially equal.

Further, in FIG. 4, a part of the wiring extending from the source electrode 25 of the transfer transistor TT on the left side of the drawing to the common signal line 5 and the gate of this transfer transistor TT.
Capacitance is also formed by electrostatic coupling between the wiring portion e extending from the port (see the portion surrounded by the two-dot chain line in FIG. 4), and this capacitance is for transfer on the left side of FIG. It becomes a part of the gate-source capacitance CGS of the transistor TT. On the other hand, in FIG. 4, the wiring portion extending from the source electrode 20 of the transfer transistor TT on the right side of the paper to the common signal line 5 has a length on the left side of FIG.
Shorter than that of T. Therefore, the portion where this wiring portion and the portion extending from the gate electrode 26 of the transfer transistor TT on the right side of FIG. 4 to the gate electrode connecting line 21 are parallel to each other is extremely short, unlike the case of the above-mentioned left side of FIG. So
The formation of the electrostatic capacitance due to this is smaller than that of the transfer transistor TT on the left side, and the capacitance CGS between the gate and the source is also small accordingly. However, in this embodiment, a part of the wiring extending from the source electrode 20 of the transfer transistor TT on the right side to the common signal line 5 crosses the gate electrode connecting line 21 at a right angle. Compensation capacitance C by facing
B is formed, and the above-mentioned decrease in capacitance is compensated. Therefore, the transfer transistor TT on the right side
Between the gate-source capacitance CGS and the gate-source capacitance CGS of the left transfer transistor TT are almost equal.

The transfer transistor TT on the right side of FIG.
Source electrode 20 and the transfer transistor T on the left side of FIG.
Capacitance due to electrostatic coupling occurs also with a part of the wiring e extending from the gate of T, and forms a part of the correction capacitor CB (enclosed by a chain double-dashed line in FIG. 4). Range). FIG. 3 shows changes in the drain and source potentials of the transfer transistor TT when the correction capacitor CA is provided and when it is not provided.
The contents will be described with reference to FIG. First, for ease of understanding, this waveform diagram is shown focusing only on the correction capacitance CA. That is, the waveform diagram shown in FIG. 3 shows that the wiring capacitance (FIG. 4) below the two transfer transistors TT arranged in a staggered manner as shown in FIG. Assuming that there is no capacitance formed between the wirings a and b and the correction capacitance CB), the correction capacitance CA is shown in FIGS. 3 (c) and 3 (d).
3 (e) and 3 (f) show the change in the drain and source potentials of the transfer transistor TT when the gate transistor is not provided. The changes in the drain and source potentials of the transfer transistor TT in which CGD is increased (in FIG. 4, the transfer transistor TT on the right side of the drawing) are shown.

Comparing the drain potential shown in FIG. 3C with the drain potential shown in FIG.
The entire voltage level of (e) is shifted to the negative side as compared with the entire voltage level of (c), and the amount of change in drain voltage at the rise and fall of the reset pulse ΦGR, that is, the voltage The voltage is higher than that of (c). This is because the gate-drain capacitance CGD of the reset transistor TR is increased due to the wiring portions a and b in FIG. 4, and the feedthrough voltage is increased. Further, in this embodiment, by providing the correction capacitor CA, the change in the drain potential of the transfer transistor TT on the side where the correction capacitor CA is provided is the same as the change shown in FIG. The pixels are the same, and the so-called offset voltage VOF (see FIG. 3 (f)) does not differ for each pixel, but has substantially the same level. 3D is a waveform diagram showing a change in the source potential of the transistor TT when the change in the drain potential of the transfer transistor TT is the change shown in FIG. 3 (f) shows that the drain potential change of the transfer transistor TT is shown in FIG. 3 (e).
The same transistor T in the case of the change shown in FIG.
It is a wave form diagram which showed the source potential change of T.

In this embodiment, the correction capacitors CA and CB
Is a so-called parallel plate type in which wirings are opposed to each other in the front-back direction of the substrate, but the structure is not limited to this, and for example, two wirings are paralleled on the same plane,
Of course, a capacitor may be formed between the parallel wirings. In this case, as shown in FIG. 7, if the distance between the drain electrode B and the gate electrode C before correction is So and the length of the parallel portion of the drain electrode B and the gate electrode C is Lo. (See FIG. 7 (a)), the distance between the drain electrode a and the gate electrode c is changed to S1 (see FIG. 7 (b)), and the length of the parallel portion between the drain electrode a and the gate electrode c is changed. Can be adjusted to L1 (see FIG. 7C) to adjust the capacitance value. Incidentally, in FIG. 7, the reference numeral "b" is a source electrode.

[0038]

As described above, according to the invention described in claim 1, it is formed between the signal wiring extending from the first switching element and the control wiring extending from the second switching element. With the configuration in which the difference in electrostatic capacitance is compensated by the correction capacitance, the signal wiring extending from the first switching element in each pixel and the second wiring
Since the capacitances formed between the control wiring extending from the switching element and the control wiring are substantially equal to each other, the offset amount of the output signal is substantially uniform, and an image signal without variation in the output signal can be obtained. It is effective. According to the third aspect of the invention, the difference between the electrostatic capacitances formed between the signal wiring and the control wiring extending from the first switching element is compensated by the correction capacitance. As a result, the capacitance formed between the signal wiring and the control line extending from the first switching element in each pixel becomes substantially equal, so that the offset amount of the output signal becomes substantially uniform, and the output signal The effect is that an image signal without variation can be obtained. According to the invention described in claim 5, the capacitance formed between the signal wiring extending from the first switching element and the control wiring extending from the second switching element, which is arranged in the vicinity of the light receiving element, is reduced. , A signal extending from the first switching element in each pixel is configured by compensating for the shortage of the similar electrostatic capacitance in the adjacent first and second switching elements with the correction capacitance. Since the capacitance between the wiring and the control wiring extending from the second switching element becomes substantially equal, the offset amount of the output signal becomes substantially uniform, and an image signal without variations in the output signal can be obtained. That is the effect. According to the invention described in claim 7, the first device is arranged apart from the light receiving element.
The capacitance formed between the signal wiring extending from the switching element and the control wiring is insufficient by comparison with the similar capacitance in the adjacent first switching element by the correction capacitance. By configuring to supplement,
Since the capacitance formed between the signal wiring extending from the first switching element and the control wiring in each pixel is substantially equal to each other, the offset amount of the output signal is substantially uniform and the variation in the output signal is small. The effect is that an image signal that does not exist can be obtained.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of an image sensor according to the present invention. Is.

FIG. 2 is an equivalent circuit diagram for one pixel of the image sensor according to the present invention.

FIG. 3 is a timing diagram for explaining the operation of the image sensor according to the present invention.

FIG. 4 is a plan view showing an embodiment of the arrangement structure of the main part of the image sensor according to the present invention.

FIG. 5 is an equivalent circuit diagram showing an example of a conventional image sensor.

FIG. 6 is a timing diagram for explaining the operation of the image sensor shown in FIG.

FIG. 7 is a schematic explanatory diagram for explaining another method of forming a capacitance.

[Explanation of symbols]

2 ... Charge transfer section, 3 ... Charge reset section, 4 ... Matrix wiring section, 5 ... Common signal line, 13a, 13b,
22a, 22b ... Drain electrodes, 15, 20, 23,
25 ... Source electrode, 19, 21 ... Gate electrode connecting wire

Claims (8)

[Claims] 1. A light receiving element array comprising at least a plurality of light receiving elements, a first storage capacitor for storing charges transferred from the light receiving elements, and the same number of light receiving elements as the plurality of light receiving elements. A first switching element for transferring the accumulated electric charge to the first storage capacitor, and a second switching element provided in the same number as the plurality of light receiving elements for discharging the residual electric charge of the light receiving elements.
In the image sensor including the switching element, the signal wiring extending from the first switching element and transmitting the electric charge of the light receiving element; and the signal wiring extending from the second switching element An image sensor characterized in that a correction capacitor is provided between the control wiring for transmitting a control signal for controlling the operation and the control wiring. 2. The image sensor according to claim 1, wherein the correction capacitor is formed by parallelly opposing the signal wiring and the control wiring. 3. A light receiving element array comprising at least a plurality of light receiving elements, a first storage capacitor for storing charges transferred from the light receiving elements, and the same number of light receiving elements as the plurality of light receiving elements. A first switching element for transferring the accumulated electric charge to the first storage capacitor, and a second switching element provided in the same number as the plurality of light receiving elements for discharging the residual electric charge of the light receiving elements.
And an image sensor including the switching element of the first switching element, the signal wiring extending from the first switching element and transmitting the electric charge of the light receiving element, and the signal wiring extending from the first switching element. An image sensor characterized in that a correction capacitor is provided between the control wiring for transmitting a control signal for controlling the operation and the control wiring. 4. The image sensor according to claim 3, wherein the correction capacitor is formed by parallelly opposing the signal wiring and the control wiring. 5. A light receiving element array comprising at least a plurality of light receiving elements, a first storage capacitor for storing charges transferred from the light receiving elements, and the same number of light receiving elements as the plurality of light receiving elements. A first switching element for transferring the accumulated electric charge to the first storage capacitor, and a second switching element provided in the same number as the plurality of light receiving elements for discharging the residual electric charge of the light receiving elements.
A switching element, and the light receiving element,
The switching element and the second switching element are arranged such that the first and second switching elements connected to the light receiving element are arranged in the vicinity of the light receiving element, and the first and second switching elements connected to the light receiving element are An image in which the second switching element and the light receiving element are arranged alternately and adjacent to each other with a gap enough to arrange a pair of the first and second switching elements. In the ji sensor,
A signal wiring extending from the first switching element arranged in the vicinity of the light receiving element and transmitting the electric charge of the light receiving element;
An image sensor, characterized in that a correction capacitor is provided between the control wiring and a control wiring which extends from the second switching element and transmits a control signal for controlling the operation of the second switching element. 6. The image sensor according to claim 5, wherein the correction capacitor is formed by parallelly opposing the signal wiring and the control wiring. 7. A light-receiving element array including at least a plurality of light-receiving elements, a first storage capacitor for storing electric charges transferred from the light-receiving elements, and the same number of light-receiving elements as the plurality of light-receiving elements. A first switching element for transferring the accumulated electric charge to the first storage capacitor, and a second switching element provided in the same number as the plurality of light receiving elements for discharging the residual electric charge of the light receiving elements.
A switching element, and the light receiving element,
The switching element and the second switching element are arranged such that the first and second switching elements connected to the light receiving element are arranged in the vicinity of the light receiving element, and the first and second switching elements connected to the light receiving element are An image in which the second switching element and the light receiving element are arranged alternately and adjacent to each other with a gap enough to arrange a pair of the first and second switching elements. In the ji sensor,
A signal wiring extending from the first switching element and spaced apart from the light receiving element such that a pair of first and second switching elements can be disposed, and a signal wire for transmitting the charge of the light receiving element; An image sensor characterized in that a correction capacitor is provided between the first switching element and a control wiring for transmitting a control signal for controlling the operation of the first switching element. 8. The image sensor according to claim 7, wherein the correction capacitor is formed by parallelly opposing the signal wiring and the control wiring.