JPH0786884A - Pulse converting circuit - Google Patents
Pulse converting circuitInfo
- Publication number
- JPH0786884A JPH0786884A JP22423293A JP22423293A JPH0786884A JP H0786884 A JPH0786884 A JP H0786884A JP 22423293 A JP22423293 A JP 22423293A JP 22423293 A JP22423293 A JP 22423293A JP H0786884 A JPH0786884 A JP H0786884A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- pulse
- count
- circuit
- reference trigger
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Pulse Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、自動制御装置等の制御
時間の設定に関し、特に制御用ディジタル回路に使用す
るパルス変換回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to setting a control time of an automatic control device or the like, and more particularly to a pulse conversion circuit used in a control digital circuit.
【０００２】[0002]
【従来の技術】従来、基準トリガ信号から一定のパルス
幅を有するパルス信号に変換させるには、抵抗とコンデ
ンサによる充放電の時定数を利用した単安定型マルチバ
イブレータを使用し、抵抗とコンデンサの定数を設定す
ることにより所定のパルス幅を有するパルス信号を発生
させる方式がもちいられているのが現状であった。2. Description of the Related Art Conventionally, in order to convert a reference trigger signal into a pulse signal having a constant pulse width, a monostable multivibrator utilizing a time constant of charging and discharging by a resistor and a capacitor is used. At present, a method of generating a pulse signal having a predetermined pulse width by setting a constant has been used.
【０００３】[0003]
【発明が解決しようとする課題】この従来の方式では、
抵抗とコンデンサの定数による時定数でパルス幅が決ま
るため、素子の定数誤差及び温度等の環境条件の変化に
よる影響が受け易いため、精度の良いパルス幅を有する
パルス信号が得られない欠点があった。In this conventional method,
Since the pulse width is determined by the time constant based on the resistance and capacitor constants, it is easily affected by the constant error of the element and changes in environmental conditions such as temperature. It was
【０００４】[0004]
【課題を解決するための手段】本発明は、所定のパルス
幅を決定するのに精度のクロック信号を使用し、基準ト
リガ信号を外部から入力した時点からクロック信号をカ
ウントアップするカウンタ部と、所定のカウントアップ
の上限値を設定し、カウントアップ上限値を検知する比
較部とを有し、この検知信号にて基準トリガ信号にて信
号保持を行う保持回路をリセットすることにより、所定
のパルス幅を有するパルス信号を発生させるものであ
る。SUMMARY OF THE INVENTION The present invention uses a clock signal of precision to determine a predetermined pulse width, and a counter section that counts up the clock signal from the time when a reference trigger signal is externally input, By setting the upper limit value of the predetermined count-up, and having a comparator that detects the upper limit value of the count-up, and by resetting the holding circuit that holds the signal with the reference trigger signal by this detection signal, the predetermined pulse A pulse signal having a width is generated.
【０００５】[0005]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。Embodiments of the present invention will now be described with reference to the drawings.
【０００６】図１は、所定のパルス幅を有するパルス信
号を発生させるためのパルス変換回路の一実施例のブロ
ック図である。FIG. 1 is a block diagram of an embodiment of a pulse conversion circuit for generating a pulse signal having a predetermined pulse width.
【０００７】本図において、外部からの基準トリガ信号
により信号を保持する保持回路１と、同信号によりクロ
ック信号のカウントを開始し、カウントアップするカウ
ンタ部２と、このカウンタ部２のカウントアップ信号と
カウントアップ上限値とを比較し、一致したときに出力
を出す比較部３から成り、比較部３の一致出力信号によ
り保持回路１をリセットすることにより、保持回路１の
出力には基準トリガ信号を起点とする所定のパルス幅を
有するパルス信号が得られる。In the figure, a holding circuit 1 for holding a signal by an external reference trigger signal, a counter section 2 for starting and counting up a clock signal by the same signal, and a count-up signal for this counter section 2. And a count-up upper limit value are compared, and the comparison circuit 3 outputs an output when they match each other. By resetting the holding circuit 1 by the coincidence output signal of the comparison unit 3, the holding circuit 1 outputs the reference trigger signal. A pulse signal having a predetermined pulse width starting from is obtained.
【０００８】このとき、所定のパルス幅Ｔは次式により
求められる。At this time, the predetermined pulse width T is obtained by the following equation.
【０００９】Ｔ＝ｎ×１／ｆ ここで、ｎはカウントアップの上限値、ｆはクロック信
号の繰り返し周波数である。T = n × 1 / f where n is the upper limit value of the count-up, and f is the repetition frequency of the clock signal.
【００１０】[0010]
【発明の効果】以上説明したように本発明は、クロック
信号の繰り返し周波数ｆとカウントアップの上限値ｎと
で決まるパルス幅Ｔを有するパルス信号が得られるとい
う結果となる。従って、パルス幅Ｔの精度は、外部から
のクロック信号の繰り返し周波数の安定度のみで決まる
ために、本発明によるパルス変換回路では、パルス幅の
精度に影響しない効果がある。As described above, the present invention results in a pulse signal having a pulse width T determined by the repetition frequency f of the clock signal and the upper limit value n of the count-up. Therefore, since the accuracy of the pulse width T is determined only by the stability of the repetition frequency of the clock signal from the outside, the pulse conversion circuit according to the present invention has the effect of not affecting the accuracy of the pulse width.
【図１】本発明のパルス変換回路の一実施例のブロック
図。FIG. 1 is a block diagram of an embodiment of a pulse conversion circuit of the present invention.
１ 保持回路 ２ カウンタ部 ３ 比較部 1 holding circuit 2 counter unit 3 comparing unit
Claims (1)
して、信号を保持する保持回路と、同信号にてクロック
信号をカウントアップするカウンタ部と、カウントアッ
プ信号の上限値を検知する比較部とを備え、カウントア
ップの上限値を任意に設定することで、検知信号により
保持回路をリセットすると、基準トリガ信号により、任
意のパルス幅を有するパルス信号に変換することを特徴
とするパルス変換回路。1. A holding circuit for holding a signal by inputting a reference trigger signal from the outside, a counter section for counting up a clock signal by the signal, and a comparison for detecting an upper limit value of the count-up signal. A pulse converter having a section and setting a count-up upper limit value to reset a holding circuit by a detection signal, the pulse signal having a reference trigger signal is converted into a pulse signal having an arbitrary pulse width. circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22423293A JPH0786884A (en) | 1993-09-09 | 1993-09-09 | Pulse converting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22423293A JPH0786884A (en) | 1993-09-09 | 1993-09-09 | Pulse converting circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0786884A true JPH0786884A (en) | 1995-03-31 |
Family
ID=16810577
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22423293A Pending JPH0786884A (en) | 1993-09-09 | 1993-09-09 | Pulse converting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0786884A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115597184A (en) * | 2022-10-21 | 2023-01-13 | 珠海格力电器股份有限公司（Cn） | Protection method and device for preventing wrong wiring, air conditioner and storage medium |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5397119A (en) * | 1977-02-03 | 1978-08-25 | Nissan Motor Co Ltd | Temperature rise protecting device for float chamber |
-
1993
- 1993-09-09 JP JP22423293A patent/JPH0786884A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5397119A (en) * | 1977-02-03 | 1978-08-25 | Nissan Motor Co Ltd | Temperature rise protecting device for float chamber |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115597184A (en) * | 2022-10-21 | 2023-01-13 | 珠海格力电器股份有限公司（Cn） | Protection method and device for preventing wrong wiring, air conditioner and storage medium |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19960924 |