JPH0787449B2 - Phase synchronization circuit - Google Patents

Description

[Detailed Description of the Invention] [Overview] LAN (Local Area Network), ISDN (Integrated Server)
In a communication system in which a master station and a plurality of slave stations are connected in a bus form, such as a ces digital network), an appropriate delay is applied to the received frame phase, thereby resetting the counter circuit to achieve phase synchronization. In this way, the distance limitation of the bus form was expanded.

[Industrial application field]

The present invention relates to a phase synchronization circuit in a communication system in which a master station such as LAN and ISDN and a plurality of slave stations are connected in a bus form.

For example, as a user / network interface in ISDN, CCITT recommends I series recommendations,
There is what is called an I interface. This I
Layer 1 for basic access in the interface
The specifications of (I-430) are shown in Table I, and the frame structure on the transmission path is shown in FIG.

The characteristic of the I interface is that the lines are four lines and the connection form between the network terminal equipment (NT: Network Termination) which is the main station and a plurality of subscriber terminals (TE: Terminal Equipment) is a bus form. Further, as shown in the specifications, 100% AMI, which is a ternary code, is used as the transmission code, and violation is used as the frame signal.

Because of the bus form, in the up direction (TE → NT), as shown in Fig. 6, each terminal is at a different distance.
When the data is sent from the TE to the main station NT, a phase difference (corresponding to the round-trip propagation time 2Tpi) occurs in the pulse at the input end of the main station NT, and the opening of the eye pattern becomes narrow. When the phase difference 2Tpi is 1 time slot or more, the eye pattern opening is lost, and the main station NT cannot read the data from each terminal TE. In order for the master station NT side to stably read the data from each terminal TE, the round-trip propagation time 2Tpi between NT and TE must be shorter than one time slot. Therefore, it becomes necessary to limit the length of the bus, and the I interface defines the bus length for each of the three wiring configurations as shown in FIG. In other words, the distance from the main station to the furthest terminal in the (a) simple bus is
Within 150m, within 10m between terminal and bus, in the extended bus of (b), the distance from the main station to the farthest terminal is within 500m, between terminals is within 50m, between terminal and bus is within 10m , (C), the one-to-one (Point to Point) type, the distance between the main station and the terminal is within 1 km.

As for the phase synchronization method in the main station NT, in the case of a simple bus, the distance between the terminals TE is large (up to 150 m), and there is a large signal phase difference at the NT reception point.
In the e Locked Loop method, a large amount of clock jitter is generated and data cannot be read stably. Therefore, distance limitation (bus length = max.150m: Round Trip Delay = max.4μ
It is preferable to use s) and perform sampling at a fixed phase. In the case of a 1: 1 type with a long NT-TE distance or an extended bus, there is a delay of more than 1 time slot, so fixed phase cannot be adopted, but instead the TE distance is short (50m
(Below) Since the phase difference due to this can be ignored, the DPLL method is suitable. From the above, it is inconvenient and costly to prepare a master station NT with a different clock method when the connection types are different, so a phase synchronization circuit technology that can handle these connection types with a single NT Is desired. Further, if there is a bus length limitation as shown in FIG. 7, the system will be difficult for the user to use, so there is a demand for a technique for expanding the bus length limitation as much as possible.

[Conventional technology]

A fixed / adaptive automatic switching system has been proposed as a phase synchronization circuit technology for a master station that can support each connection form shown in FIG. The configuration of this system is shown in FIG. 8, and the time chart for explaining the configuration and operation of the shortest terminal distance identification circuit 10 in FIG. 8 is shown in FIG. In this method, the AMI violation is used as the frame bit, and the first violation phase received by the master station NT with respect to the frame phase SF sent from the master station NT is the received frame of FIG. If the phase difference between the outputs S ₂ and SF detected by the phase detection circuit 12 does not exceed a certain threshold S ₁ output from the mono-multi circuit MM as shown in FIG. 9 (b), the AND gate G The output of ₁ is "H", therefore the Q output S ₃ of the SR flip-flop FF ₁ is "H", and then the Q output SS of the D-type flip-flop FF ₂ , that is, the output (switching signal) of this shortest terminal distance identification circuit 10. Becomes “H”. Also, (c)
When S ₂ exceeds S ₁ , S ₃ is “L” and the output SS of the shortest terminal distance identification circuit 10 is also “L”. This switching signal SS is inputted to the selector shown in FIG. 8 as a selection signal. When this switching signal is "H", the selector selects and outputs the fixed phase clock CLKf output from the transmission control circuit 14. As a result, the retiming circuit 18 reads the data with the fixed phase clock. When this switching signal is "L", the adaptive phase clock CLKa output from DPLL is selected and output. As a result, data is read by the adaptive phase clock in the retiming circuit. By using this method, each wiring configuration as shown in FIG. 7 can be accommodated by one NT.

[Problems to be solved by the invention]

Figure 10 shows the limits of fixed and adaptive clocks. In the case of a fixed clock, the distance Ddiff between terminals can be made large because it is not affected by the jitter of received data, and the distance Ddiff between terminals and the distance between the master station and terminal Dtotal can be up to about 150 m. Since the adaptive clock extracts the timing from the received data, the distance Ddiff between terminals cannot be made large due to jitter, which is about 50 m. However, the terminal-main station distance Dtotal can be extended to the limit of the receiver circuit (500 m or 1 km). Therefore, in the fixed / adaptive switching method, both of them are the limit points of the distance.

However, considering an office or the like as an application target of this communication system, it is convenient if, for example, the master station is on the first floor (first floor) and a plurality of slave stations can be installed on the second floor, or the third floor, the fourth floor, or the like. Ddiff is 150m, Dtotal is 100m, 200m, 300
m, etc. are required. However, in the conventional phase locked loop circuit,
As shown in Fig. 0, when Dtotal is 200m, 300m, Ddiff
Can only extend about 50m.

Further, when Dtotal is around 150 m, the clock is fixed and is frequently switched to adaptive, which causes an error.

The present invention intends to improve these points, provide a large inter-terminal distance Ddiff, and provide a phase synchronization circuit capable of stable data reading.

[Means for solving problems]

FIG. 1 is a block diagram of the principle of the present invention, which comprises a frame phase detection circuit 20, a delay circuit 22, and a 1 / N counter 24.

[Action]

In the present invention, the frame phase RF is detected by the frame phase detection circuit 20 from the received data RD, the frame phase is delayed by an appropriate amount by the delay circuit 22, and the output clock
Phase synchronization is achieved by resetting the 1 / N counter 24 at an ideal position so that CLK can read the received data RD.

〔Example〕

FIG. 2 is a block diagram of a phase synchronization circuit when applied to a main station NT of an I interface as an embodiment of the present invention. FIG. 3 shows an operation time chart. Since the transmission code is a ternary AMI code, it is divided into + side RD + and − side RD− as received data from the receiver, and the frame phase detection circuit
Entered in 20. The frame phase detection circuit 20 detects the frame phase and outputs a pulse RF. In this embodiment, as shown in FIG. 3 RF, a pulse is output at the falling edge of the frame pulse (in the case of the I interface,
Since the violation is used as the frame, when the frame phase is detected at the rising edge, the frame phase is not known when the previous bit L of the frame is a pulse, so the frame phase is detected at the falling edge).
This pulse RF is input to the delay circuit 22 and given an appropriate delay. The output RST of the delay circuit 22 resets the 1/40 counter 24 which produces a clock CLK of 192 KHz which is a transmission rate from the master clock MCLK of 7.68 MHz and synchronizes it with the received frame.

The delay amount is calculated from the following. That is, as shown in FIG. 4, one time slot of transmission data is 5.2 μs, and the distance between terminals is Ddiff
About 80% of one time slot (4.0
μs, which is the maximum value of the round trip delay), the eye becomes 1.2 μs. Note that RFn in FIG. 4 is the received frame of the latest terminal and RFd is the received frame of the farthest terminal.
Therefore, in order to punch out the center of the eye with the clock, the counter may be reset so that the clock rises at a position 4.6 μs from the trailing edge of the reception frame pulse RFn of the terminal recently. However, since the low portion of the clock is 2.6 μs, the delay amount of the delay circuit is 4.6-2.
6 = 2.0 μs.

The present invention also has an influence of jitter, but this is not so large. That is, in the DPLL method, since the clock is adjusted to each received bit, a large jitter (4 μs) is generated, which causes the distance between terminals to be unable to be large. However, in the present invention, it is not adjusted to each bit but only to the frame bit. Is. At the receiving end of the main station, the transmission signals from each terminal enter in a combined form, but since the signal from a distant terminal is attenuated, the signal of the terminal has recently won, and the combined wave has recently risen to the frame beat F of the terminal. It takes a form of falling edge, and the jitter at this falling edge is almost equal to the jitter of the signal of the terminal recently. Therefore
It is much smaller than the DPLL method, which is the reason why the distance between terminals can be increased in the present invention.

〔The invention's effect〕

According to the present invention, there is no time limitation regarding the distance between the master station and the slave station, and the maximum distance between the slave station and the slave station is 1 at maximum.
It becomes possible to extend to a distance corresponding to about 80% of the time slot, and the bus length restriction can be relaxed.

[Brief description of drawings]

1 is a principle diagram of the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, FIG. 3 is an input / output waveform diagram of each part of FIG. 2, and FIG. 4 is an explanatory diagram of a delay amount calculation procedure. 5, FIG. 5 is an explanatory diagram showing a frame structure of the I interface, FIG. 6 is an explanatory diagram of timing of bus connection, FIG. 7 is an explanatory diagram of a bus form in the I interface, and FIG. 8 is fixed / adaptive automatic switching. FIG. 9 is an explanatory diagram of the method, FIG. 9 is an explanatory diagram of the shortest terminal distance identification circuit, and FIG. 10 is an explanatory diagram of the limit points in FIG.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Reference number within the agency FI Technical indication location H04L 12/40 (72) Inventor Kazuo Murano 1015 Uedoda, Nakahara-ku, Kawasaki-shi, Kanagawa Within Fujitsu Limited (72) Inventor Akihiko Takada 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Yasuyuki Okumura, 3-9-11 Midoricho, Musashino City, Tokyo Japan Telegraph and Telephone Corporation 1st Network Research Laboratories

Claims (1)

[Claims] 1. A phase synchronization circuit of a master station in a communication system in which one master station (NT) and a plurality of slave stations (TE) are connected in a bus form, and a frame phase detection circuit (20) and a delay circuit. (twenty two)
And a counter (24) that divides the data read clock from the master clock, delays the frame phase detected by the frame phase detection circuit with a delay circuit, and resets the counter with the obtained signal for phase synchronization. A phase-locked loop circuit characterized by being formed.