JPH0787513B2 - Photoelectric conversion device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a signal reading circuit of an integrated sensor in which a plurality of sensors are commonly connected in a matrix (line) switch group. This will be explained as an example.

[Conventional technology]

Conventional Example 1 As a conventional read-back sensor signal reading circuit, a scanning circuit as shown in FIGS. 4 and 5 of JP-A-59-11073 is used. The selection signal of the sensor is synchronized with a certain one-phase clock, and the selection pulse width is less than one cycle of the clock.

Conventional Example 2 A conventional optical line sensor has a plurality of CCD chips arranged in a zigzag pattern as shown in FIGS.
It was a method of forming an optical image with a converging rod lens array.

Conventional Example 3 A conventional optical line sensor adopts an optical system in which an image is formed by a converging rod lens array as shown in FIG. 1 of JP-A-59-67770, and the sensor array (photodiode array) is one chip and scans. The circuit consisted of one or more chips of a hybrid integrated circuit.

[Problems to be solved by the invention]

The contact image sensor is configured by the method as shown in Conventional Examples 2 and 3. The problem with the contact type is that the sensor length is long. Therefore, a multi-chip configuration is used, or only one sensor array is configured with one chip, and the scanning circuit is configured with multi-chip, which is naturally high in cost. Therefore, "Nikkei Electronics 1984-9-24 P128
~ P129 ", the scanning circuit and the photodiode array are integrated on the same substrate for the contact type one-dimensional sensor. When integrated on the same substrate, the cost can be reduced as the number of elements on the chip decreases. Therefore, it is necessary to simplify the scanning circuit more than the conventional one.

[Means for solving problems]

A photoelectric conversion device of the present invention includes a photoelectric conversion element array in which a plurality of series circuits each including a photoelectric conversion element and a switch unit are connected in parallel, a scanning circuit that selectively scans the switch unit in synchronization with a clock signal, and the photoelectric conversion element. The scanning circuit has one current-voltage converting means for converting the signal output from the array and integrating means for integrating the output of the current-voltage converting means, and the scanning circuit is time-series in one cycle of the clock signal. In the photoelectric conversion circuit that selects the two switches at the shifted timings, a signal having a phase opposite to the clock noise component included in the signal output from the current-voltage conversion means to the integration means is converted into the current-voltage conversion. It is characterized in that it has a clock noise suppressing means that overlaps with the signal output from the means.

[Action]

Since the scanning means of the present invention selects two sensors in a time series in one cycle of the clock, it is possible to selectively control two sensors with one shift register output of the conventional scanning means. Clock noise will increase. However, since the output signal from the current-voltage conversion unit has the clock noise suppression unit that superimposes the signal of the opposite phase of the clock noise, the photoelectric conversion device having an excellent S / N ratio can be obtained.

〔Example〕

FIG. 1 shows a circuit configuration of a signal reading circuit of a logarithmic sensor of the present invention, and FIG. 2 is a time chart for explaining its operation. In order to avoid complexity of explanation, only the circuit configuration is a 5-element line sensor, and the timing generator is omitted.

In FIG. 1, the scanning circuit 101 is composed of an inverter 1 and clocked gate inverters 2 and 3, and its operation is the second.
As shown in the figure, when the start pulse SP and the clock CL are applied, a time-series pulse (see S ₁ , S ₂ , S ₃ ) having a width of one clock cycle is generated every half cycle of the clock.

The photodiode array 102 is composed of an analog switch 5 and a photodiode 6 (or a photoconductive capacitor. The photodiode 6 performs a storage operation. That is, the voltage across the photodiode 6 is initially charged to the sensor bias voltage V _SB. And then exposed to discharge the electric charge.
When one analog switch 5 selected in 101 is turned on (actually, the analog switch 5 selected before the half cycle of the clock is also turned on), the sensor bias voltage V _SB is applied to the corresponding photodiode 6. The recharge current Io flows into the briamplifier 103, whereby the signal is taken out.

The preamplifier 103 is composed of resistors R ₁ and R ₂ and an operational amplifier 7, and serves as an inverting current-voltage conversion amplifier.

The integrator 104 is composed of a resistor R ₃ , a capacitor C ₁ , an operational amplifier 8, and an analog switch 10, and is an inverting integrator. The reset pulse R _ST applies the waveform shown in FIG. 2 to reset the charge of the capacitor C ₁ .

The sample holder 105 is a sample hold pulse S shown in FIG.
Apply H and hold sample.

In Fig. 2, the recharge current Io is the signal charge Q _S and the noise charge Q _N.
Including and The noise charge Q _N is generated by the coupling of the clock CL to the photodiode array 102 through the stray parasitic capacitance, and the positive and negative polarities of the noise charge Q _N in the recharge current Io are symmetrical. The coupling amount can be stabilized by modularizing the scanning circuit 101, the photodiode array 102, and the preamplifier 103 (for example, hybrid IC, monolithic, and hybrid circuit for each block). In FIG. 2, the waveform of the recharge current Io is schematically represented for convenience of explanation. That is, the signal charge Q _S and the noise charge Q _N are shown separated in time, but in reality, the waveforms are not separated in time series because the time constants are close to each other.

The operation when the clock signal is not suppressed is the second operation.
It is shown in the integrated waveform Vc ′ and the output waveform Vo ′ in the figure. Second
As can be seen from the figure, the clock CL is superposed on both outputs when the photodiode 6 is not selected and when the same amount of light is incident on each photodiode. A clock suppressing circuit 106 composed of analog switches 11 and 12, an inverter 13, a variable voltage source V _CL , a capacitor C ₂ and a resistor R ₄ is used. Black C
Analog switch 11 and 12 to which L is input, inverter 13,
The variable voltage source V _CL constitutes a square wave generator that is in phase with the clock CL and whose amplitude can be varied. The amount of suppression of the clock CL is adjusted by adjusting the size of the variable voltage source V _CL and the capacitor C ₂ , and the injection amount is increased by increasing the value in both sides. The resistor R ₄ is added to the integrator so that a steep waveform is not applied, and its time constant is proportional to the product of the capacitor C ₂ and the resistor R ₄ , and also becomes the time constant equivalent to the recharge current Io. To set. Further, since the preamplifier is an inverting amplifier, in order to suppress the clock CL, a compensation signal having the same phase as the clock CL when input from the integrator as shown in FIG. 1 may be used. Similarly, in the case of injecting from the input terminal of the preamplifier 103 for compensation, a signal having a phase opposite to that of the clock CL is required, and since it is suppressed before amplification, it is necessary to inject a minute compensation signal.

The operation when the clock suppression circuit 106 is used is shown by the integral waveform V _C and the output waveform Vo in FIG. Since the integrator 104 is used, it is not necessary to compensate with the same waveform as the noise charge Q _N. Therefore, the response of the integrated waveform Vc is disturbed,
The output waveform Vo that samples and holds it suppresses the clock CL. The problem of this circuit is the stability of the electrostatic coupling between the clock CL and the photodiode array 102.
With mechanically stable construction, the only problem is the temperature characteristic, and if the variable voltage V _CL has the same temperature characteristic, a clock suppression effect with considerable temperature stability can be obtained.

Since the present invention has a scanning means for always selecting two adjacent sensors, its operation will be described. When the selection pulse S ₁ is in the selected state in FIGS. 1 and 2, the photodiode 6 corresponding to S ₁ accumulates and is recharged according to the exposure amount, so that it is taken out as an output. At that time, the photocurrent currently exposed to the photodiode 6 corresponding to S ₁ is also extracted. Next, when the selection pulses S ₁ and S ₂ enter the selected state, the recharge of the photodiode 6 corresponding to S ₁ is completed. Then, recharging is performed in accordance with the exposure amount accumulated in the photodiode 6 corresponding to S ₂ , so that it is taken out as an output. In that case, the photodiode 6 corresponding to S ₁ and S ₂
The photocurrent currently being exposed to is also extracted.
In this way, the non-accumulated output of the sensor selected one sensor before appears as an error, but the read time is shorter than the accumulation time of the sensor because it is an adjacent bit and the information is correlated. If it is 1/1000 or less.), The exposure can be stopped in the read cycle.
It's not a big issue for a number of reasons.

〔effect〕

As described above, according to the present invention, the scanning circuit can be simplified. This is because a 1-bit sensor can be driven by a shift register corresponding to a normal half-bit, and only a shift register and a buffer inverter can be configured. Due to the simplification of the scanning circuit, a one-chip type contact image sensor (see Nikkei Electronics 1984-9
-24 P128 to P129 ”, which means that the chip width and the number of elements can be reduced. Therefore, the cost is reduced. Further, the simplification of the scanning circuit also leads to improvement in operating speed.

As described above, the present invention is particularly effective in reducing the cost and increasing the speed of the one-chip type contact image sensor.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a multiple sensor signal read circuit of the present invention. FIG. 2 is a timing chart of the multiple sensor signal reading circuit of the present invention. CL is a clock, 6 is a sensor (photodiode), 101 is a scanning circuit, 102 is a sensor array (photodiode array), 103 is a preamplifier, 104 is an integrator, and 106 is a clock suppression circuit.

Claims (1)

[Claims] 1. A photoelectric conversion element array in which a plurality of series circuits each including a photoelectric conversion element and switch means are connected in parallel, a scanning circuit for selectively scanning the switch means in synchronization with a clock signal, and an output from the photoelectric conversion element array. The converted signal 1
And a switch for integrating the output of the current-voltage converting means, wherein the scanning circuit has two switches at timings shifted in time series during one cycle of the clock signal. In the photoelectric conversion circuit for selecting, a signal having a phase opposite to the clock noise component included in the signal output from the current-voltage converting means to the integrating means is superimposed on the signal output from the current-voltage converting means. A photoelectric conversion circuit having clock noise suppressing means for