JPH0789434B2 - Dynamic memory device - Google Patents
Dynamic memory deviceInfo
- Publication number
- JPH0789434B2 JPH0789434B2 JP61270124A JP27012486A JPH0789434B2 JP H0789434 B2 JPH0789434 B2 JP H0789434B2 JP 61270124 A JP61270124 A JP 61270124A JP 27012486 A JP27012486 A JP 27012486A JP H0789434 B2 JPH0789434 B2 JP H0789434B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- memory device
- power
- activation signal
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 13
- 230000004913 activation Effects 0.000 claims description 11
- 230000002093 peripheral effect Effects 0.000 claims description 9
- 239000003990 capacitor Substances 0.000 description 5
- 238000007493 shaping process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 102200091804 rs104894738 Human genes 0.000 description 1
Landscapes
- Static Random-Access Memory (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明はダイナミック型記憶装置、例えば半導体基板上
に集積化されたダイナミック型記憶装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic memory device, for example, a dynamic memory device integrated on a semiconductor substrate.
（従来の技術） 従来、この種のダイナミック型記憶装置としては、例え
ば日本電気株式会社製のμPD4164Cが知られており、こ
のダイナミック型記憶装置はＰ型の半導体基板にＮチャ
ンネルMOSトランジスタを多数形成し、これらのMOSトラ
ンジスタでメモリセルアレイと該メモリセルアレイの機
能に必要な周辺回路とを構成している。かかる従来のダ
イナミック型記憶装置にあっては、使用時に半導体基板
を負にバイアスして各MOSトランジスタをエンハンスト
メントモードで動作させている。(Prior Art) Conventionally, as this type of dynamic memory device, for example, μPD4164C manufactured by NEC Corporation is known, and this dynamic memory device has a large number of N-channel MOS transistors formed on a P-type semiconductor substrate. Then, these MOS transistors form a memory cell array and peripheral circuits necessary for the function of the memory cell array. In such a conventional dynamic memory device, each MOS transistor is operated in the enhancement mode by negatively biasing the semiconductor substrate at the time of use.
（発明が解決しようとする問題点） 上述した従来のダイナミック型記憶装置は基板に負のバ
イアス電圧を供給する基板電圧発生回路を有し、電源投
入後には基板を負にバイアスしてMOSトランジスタをエ
ンハンスメントモードで動作させている。ところが、こ
の基板電位は電源投入後すぐには安定化しないことから
この種のダイナミック型記憶装置は電源投入後100μｓ
以上経過しなければ正常に動作しない。（例えば、上記
μPD4364Cの取扱説明書には、「電源投入時には、電源
投入後100μｓ以上たってからRAS（バー）クロックを入
力するダミーサイクルを８サイクル入れて下さい」と記
載されている。）これを無視すると、メモリを構成する
トランジスタがデプレッションモードで動作するのでメ
モリに異常電流が流れ、メモリを含むシステムの消費電
力の増大をもたらすだけでなく、長期的には信頼性の低
下を招くという問題点があった。(Problems to be Solved by the Invention) The conventional dynamic memory device described above has a substrate voltage generation circuit that supplies a negative bias voltage to the substrate, and after the power is turned on, the substrate is negatively biased to turn on the MOS transistor. It operates in enhancement mode. However, since the substrate potential is not stabilized immediately after the power is turned on, this type of dynamic memory device is 100 μs after the power is turned on.
It will not operate normally if the above does not elapse. (For example, the instruction manual for the µPD4364C above states "When turning on the power, insert eight dummy cycles for inputting the RAS (bar) clock after 100 µs or more after turning on the power.") If neglected, the transistors that make up the memory operate in depletion mode, causing an abnormal current to flow in the memory, which not only increases the power consumption of the system including the memory, but also causes a decrease in reliability over the long term. was there.
それで、本発明の目的は電源投入時に不所望の異常電流
を防止し消費電力の少ないダイナミック型記憶装置を提
供するものである。Therefore, an object of the present invention is to provide a dynamic memory device which prevents an undesired abnormal current when the power is turned on and consumes less power.
（問題点を解決するための手段、作用および効果） 第２図（Ａ）、（Ｂ）には64Kbitダイナミックランダム
アクセスメモリ装置の電源投入直後に流れる電源電流が
チップ活性化信号を含むクロック入力（RAS（バー）、C
AS（バー）、WE（バー））の電圧レベルに依存している
ことを示している。図中、Icc（Ａ）は入力電圧をロウ
レベル（活性化状態）にした時の電源電流を、Icc
（Ｂ）は入力電圧をハイレベル（非活性状態、スタンバ
イ状態）にしたときの電源電流値をそれぞれ示してい
る。上記Icc（Ａ）とIcc（Ｂ）とを比較すると、電源投
入時にチップ活性化信号をハイレベル（非活性状態）に
設定すれば電源電流値を減少させることができ、大きな
突入電流も流れないことが理解できる。(Means, Actions and Effects for Solving Problems) FIGS. 2 (A) and 2 (B) show that a power supply current flowing immediately after power-on of a 64 Kbit dynamic random access memory device is a clock input including a chip activation signal ( RAS (bar), C
It shows that it depends on the voltage level of AS (bar) and WE (bar). In the figure, Icc (A) is the power supply current when the input voltage is at low level (active state).
(B) shows power supply current values when the input voltage is set to a high level (inactive state, standby state). Comparing Icc (A) and Icc (B) above, if the chip activation signal is set to a high level (inactive state) when the power is turned on, the power supply current value can be reduced and a large inrush current will not flow. I understand.
本発明は上記知見に基づきなされたものであり、複数の
セルからなるメモリセルアレイと、外部から供給される
チップ活性化信号に基づき活性化され基板に一定のバイ
アス電圧を供給する基板電圧発生回路を含む周辺回路と
を備えたダイナミック型記憶装置において、上記周辺回
路に電源投入後所定時間の間上記チップ活性化信号を非
活性化する回路を含めたことを特徴としている。The present invention has been made based on the above findings, and includes a memory cell array composed of a plurality of cells and a substrate voltage generation circuit which is activated based on a chip activation signal supplied from the outside and supplies a constant bias voltage to the substrate. In the dynamic memory device including a peripheral circuit including the peripheral circuit, a circuit for deactivating the chip activation signal for a predetermined time after power-on is included in the peripheral circuit.
かかる構成のダイナミック型記憶装置は、電源投入時に
所定時間の間上記チップ活性化信号が非活性化されるの
で電源投入時の消費電力の減少させることができるとい
う効果が得られる。In the dynamic memory device having such a configuration, since the chip activation signal is deactivated for a predetermined time when the power is turned on, it is possible to obtain an effect that the power consumption when the power is turned on can be reduced.
（実施例） 第１図は本発明を64Kbitダイナミックランダムアクセス
メモリ装置に適用した例を示す図であり、１はRAS（バ
ー）パワーオンリセット回路を、２はメモリセルアレイ
を示している。このRAS（バー）パワーオンリセット回
路があらたに付加された構成である。第３図は第１図中
のRAS（バー）パワーオンリセット回路１の具体的な構
成を示している。同図中、Ｃはキャパシタ、Ｒは抵抗
体、G1は波形整形回路またはコンパレータ、G2はナンド
ゲート、G3はオアゲート、RAS（バー）はチップ活性化
信号をそれぞれ示している。第４図は第３図に示された
回路の動作タイミングチャート図である。第３図と第４
図とを参照しつつ本実施例の動作を説明する。なお、RA
S（バー）パワーオンリセット回路１は電源投入直後の
み作動する。電源電圧が立ち上がった直後は上記キャパ
シタＣと抵抗体Ｒとで構成されるCR回路のノードＡ、ま
たはノードＡ′はロウレベルであり、ナンドゲートＧ2
とオアゲートＧ3よりなる順序回路の出力Ｑは少なくと
もキャパシタＣが抵抗体Ｒを介して充電され、波形整形
回路Ｇ1のしきい値VTを超えるまでRAS（バー）入力レベ
ルに無関係にハイレベルを保持する。第４図の破線はRA
S（バー）がロウレベルで電源が投入された場合の波形
を示している。本回路中のキャパシタＣ、抵抗体Ｒおよ
び波形整形回路Ｇ1のしきい値VTの値は必要とするリセ
ット期間に応じて決定することができる。(Embodiment) FIG. 1 is a diagram showing an example in which the present invention is applied to a 64 Kbit dynamic random access memory device, where 1 is a RAS (bar) power-on reset circuit and 2 is a memory cell array. This RAS (bar) power-on reset circuit is newly added. FIG. 3 shows a specific configuration of the RAS (bar) power-on reset circuit 1 in FIG. In the figure, C is a capacitor, R is a resistor, G1 is a waveform shaping circuit or comparator, G2 is a NAND gate, G3 is an OR gate, and RAS (bar) is a chip activation signal. FIG. 4 is an operation timing chart of the circuit shown in FIG. Figures 3 and 4
The operation of this embodiment will be described with reference to the drawings. RA
The S (bar) power-on reset circuit 1 operates only immediately after the power is turned on. Immediately after the power supply voltage rises, the node A or node A'of the CR circuit composed of the capacitor C and the resistor R is at the low level, and the NAND gate G 2
The output Q of the sequential circuit composed of the OR gate G 3 and the OR gate G 3 is at a high level regardless of the RAS (bar) input level until at least the capacitor C is charged through the resistor R and exceeds the threshold VT of the waveform shaping circuit G 1. Hold. The broken line in Fig. 4 is RA
The waveform when S (bar) is low level and power is turned on is shown. The value of the threshold value VT of the capacitor C, the resistor R and the waveform shaping circuit G 1 in this circuit can be determined according to the required reset period.
以上、説明したように本実施例はダイナミック型記憶装
置において、チップ活性化信号をチップ内部にて電源投
入直後の一定期間自動的に非活性化することによりメモ
リの動作に制限を加えることなくメモリを安定状態に導
く。これによりメモリの電源投入直後の電源電流を減少
せしめることができる。As described above, according to the present embodiment, in the dynamic memory device, the chip activation signal is automatically deactivated within the chip for a certain period immediately after the power is turned on, so that the operation of the memory is not restricted. Lead to a stable state. As a result, the power supply current immediately after the memory is powered on can be reduced.
第１図は一実施例のブロック図、第２図（Ａ）、（Ｂ）
は電源投入直後の電源電流の変化を示すグラフ、第３図
はRAS（バー）パワーオンリセット回路の回路図、第４
図は一実施例のタイミングチャート図である。 １……RAS（バー）パワーオンリセット回路、２……メ
モリセルアレイ、Ｃ……キャパシタ、Ｒ……抵抗体、Ｇ
1……波形整形回路、Ｇ2……ナンドゲート、Ｇ3……オ
アゲート、RAS（バー）……チップ活性化信号。FIG. 1 is a block diagram of one embodiment, and FIGS. 2 (A) and 2 (B).
Is a graph showing the change in the power supply current immediately after the power is turned on. Fig. 3 is a circuit diagram of the RAS (bar) power-on reset circuit.
The figure is a timing chart of one embodiment. 1 ... RAS (bar) power-on reset circuit, 2 ... memory cell array, C ... capacitor, R ... resistor, G
1 ...... Waveform shaping circuit, G 2 …… NAND gate, G 3 …… OR gate, RAS (bar) …… Chip activation signal.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｇ１１Ｃ 11/34 ３３５ Ｃ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location G11C 11/34 335 C
Claims (2)
投入された電源電圧に基づき基板に一定のバイアス電圧
を発生する基板電圧発生回路を有し、外部から供給され
るチップ活性化信号に基づき活性化され前記電源電圧で
動作する周辺回路とを備えるダイナミック型記憶装置に
おいて、 前記電源電圧の投入後、所定時間の間前記チップ活性化
信号の前記周辺回路への転送を禁止して前記周辺回路を
非活性化させ、その後、前記チップ活性化信号の前記周
辺回路への転送を許可する回路を設けたことを特徴とす
るダイナミック型記憶装置。1. A memory cell array comprising a plurality of cells,
A dynamic circuit having a substrate voltage generation circuit that generates a constant bias voltage on the substrate based on a supplied power supply voltage, and a peripheral circuit that is activated based on a chip activation signal supplied from the outside and operates at the power supply voltage. In the memory device, the transfer of the chip activation signal to the peripheral circuit is prohibited to deactivate the peripheral circuit for a predetermined time after the power supply voltage is turned on, and then the chip activation signal is transferred to the peripheral circuit. A dynamic memory device comprising a circuit for permitting transfer to a peripheral circuit.
ら発生される前記基板電位が安定する期間である特許請
求の範囲第１項記載のダイナミック型記憶装置。2. The dynamic memory device according to claim 1, wherein the predetermined time is a period during which the substrate potential generated from the substrate voltage generating circuit is stable.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61270124A JPH0789434B2 (en) | 1986-11-12 | 1986-11-12 | Dynamic memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61270124A JPH0789434B2 (en) | 1986-11-12 | 1986-11-12 | Dynamic memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63122087A JPS63122087A (en) | 1988-05-26 |
| JPH0789434B2 true JPH0789434B2 (en) | 1995-09-27 |
Family
ID=17481884
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61270124A Expired - Lifetime JPH0789434B2 (en) | 1986-11-12 | 1986-11-12 | Dynamic memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0789434B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2772530B2 (en) * | 1988-12-05 | 1998-07-02 | 三菱電機株式会社 | Semiconductor integrated circuit device |
| JPH0512861A (en) * | 1991-07-04 | 1993-01-22 | Mitsubishi Electric Corp | Semiconductor memory device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5836435B2 (en) * | 1978-10-31 | 1983-08-09 | 松下電器産業株式会社 | semiconductor memory circuit |
| JPS5641328U (en) * | 1979-09-05 | 1981-04-16 | ||
| JPS595488A (en) * | 1982-07-01 | 1984-01-12 | Fujitsu Ltd | Semiconductor device |
| JPS6069895A (en) * | 1983-09-22 | 1985-04-20 | Fujitsu Ltd | Semiconductor integrated circuit |
| JPH0618249B2 (en) * | 1984-10-17 | 1994-03-09 | 富士通株式会社 | Semiconductor integrated circuit |
| JPS6368053U (en) * | 1986-10-20 | 1988-05-07 |
-
1986
- 1986-11-12 JP JP61270124A patent/JPH0789434B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63122087A (en) | 1988-05-26 |
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