JPH0793131A - Bit reverse operation circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] An object of the present invention is to provide a bit reverse operation circuit which can be realized in a small circuit scale, is high-speed, and has a high design efficiency. [Structure] An upper (M−N) bit processing circuit and a lower N bit processing circuit adder circuit, and a (M−N) bit left shift circuit in the lower N bit processing circuit uses a signal obtained by inverting a control signal. One shifter circuit and a second shifter circuit that performs a predetermined number of shifts. And M =
If 3 × 2 ⁿ⁻² (n is the number of control signal bits and M is the number of input signal bits) holds, the first shifter circuit is an n-th power of 2 shifter circuit, and the second shifter circuit is a second shifter circuit. 2 °
It is realized by the shifter circuit of.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit reverse arithmetic circuit.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 2, an n-bit (2 ⁿ ≧ M) -bit control signal 2 is applied to an M-bit input signal 1 according to a numerical value N represented by the control signal.
The bit-reverse operation circuit that outputs a signal in which the lower N bits are bit-reversed while the -N) bit remains unchanged is a 1-bit reverse circuit 11, a 2-bit reverse circuit 12, ... It is composed of a fixed number bit reverse circuit of a kind and a selection circuit 14 which selects the output of only one of these circuits according to the numerical value N represented by the control signal.
However, there is a problem that the circuit scale also increases as the number increases.

Further, in order to reduce the circuit scale, there is provided a bit reverse operation circuit composed of an upper (MN) bit processing circuit, a lower N bit processing circuit and an adding circuit, the lower N bit processing circuit thereof. It is difficult to increase the speed when a circuit for performing (M−N) bit shift is used in the above and an arithmetic circuit for calculating (M−N) is used for the circuit for performing the (M−N) bit shift. There was a problem.

[0004]

As described above, the conventional
For an M-bit input signal, an n (2 ⁿ ≧ M) -bit control signal causes the upper (M−N) bits to remain unchanged and the lower N bits to be bit-reversed according to the numerical value N represented by the control signal. In the bit reverse operation circuit that outputs the signal, there is a problem that the circuit scale becomes large or it is difficult to increase the speed.

The present invention was devised to solve the above problems, and an object of the present invention is to provide a bit reverse operation circuit which can be realized with a small circuit scale, is fast, and has a high design efficiency.

[0006]

In order to achieve the above object, a bit reverse operation circuit of the present invention is a high-order (M-
An N) bit processing circuit, a lower N bit processing circuit, and an addition circuit, and a circuit for performing (MN) bit shift is used in the lower N bit processing circuit. A circuit for performing the (M−N) -bit shift includes a first shifter circuit that uses a signal obtained by inverting all the bits of the control signal as a control input signal, and a second shifter circuit that performs a predetermined number of shifts. Consists of. Then, M = 3 × 2 between M and N
When there are ^n-2 the relationship, the first shifter circuit 2 ⁰ bit shifter circuit, 2 ¹ bit shift circuit, 2 ² bit shift circuit, · · · 2 ^n-2 bit shift circuit and, 2 ^n-2
It is composed of a total of n power of two-bit shift circuit of bids shift circuit, and the second shifter circuit is composed of 2 ⁰ bit shift circuit.

[0007]

In the circuit of the present invention, the high-order (M-N) bit processing circuit outputs a signal in which the high-order (M-N) bits of the M-bit input signal remain unchanged and the low-order N bits are all zero. Further, the lower N-bit processing circuit outputs a signal in which all the upper (MN) bits of the M-bit input signal are 0 and the lower N bits are bit-reversed. Then, the two output signals from the high-order (M−N) bit processing circuit and the low-order N-bit processing circuit are added by an adder circuit (the logical sum is obtained), so that the high-order (M−N) bits remain unchanged and the low-order A signal in which N bits are bit-reversed is obtained. Here, the lower N-bit processing circuit is realized as follows. The input M-bit signal is the internal (M−N)
The bit shift circuit shifts to the left by (M−N) bits. Here, it is assumed that all the lower (MN) bits are 0. Then, the signal shifted left by (M−N) bits is reversed by M bits (all bits). As a result, as described above, a signal in which the upper (M−N) bits of the M-bit input signal are all 0 and the lower N bits are bit-reversed is obtained.

The circuit for (MN) bit shifting according to the present invention is realized as follows. Now, it is assumed that the binary value of the n-bit control signal represents the numerical value N. The first shifter circuit uses a signal obtained by inverting all the bits of the control signal. Since the signal obtained by inverting all the bits is a one's complement, the numerical value (2 ⁿ -1-
N). However, the power of the bit shift circuit each bit of n 2 of the control signal, i.e. 2 ⁰ bit shift circuit, 2 ¹ bit shift circuit, ...
It controls the 2 ^n-2 bit shift circuit and the 2 ^n-2 bit shift circuit. Since the last shift circuit is a 2 ^{n- 2} bit shift circuit instead of 2 ^n-1 , the above numerical value (2 ⁿ -1-N)
Does not match the actual shift amount. As a result, the first shifter circuit performs (2 ⁿ -1-N) -2 ^n-2 bit left shift on the M-bit input signal. Here, when there is a relation of M = 3 × 2 ⁿ⁻² between M and n,
The first shifter circuit has (2 ⁿ −1−N) −2 ⁿ⁻² = M−
This means that N-1 bit left shift has been performed. Then, the left-shifted signal is left-shifted by a predetermined number of bits, that is, 2 ⁰ = 1 bit by the second shifter circuit. In this way, a signal shifted to the left by (M−N) bits is obtained as a whole.

[0009] Usually, the first shifter circuit 2 ⁰ bit shift circuit, 2 ¹ bit shift circuit is constituted by · · · 2 ^n-1 bit shift circuit, thus the input signal of M bits (2 ⁿ - 1-N) shift left by one bit. Then, the second shifter circuit shifts to the right by a predetermined number of bits, that is, (2 ⁿ -1-M) bits. Thereby, as a whole, (2 ⁿ -1-N)-(2 ⁿ -1-M) = (M-
N) A bit left shift is realized. However, in that case, the first shifter circuit requires a shift circuit with a maximum of 2 ^n-1 bits, and the second shifter circuit also has a shift circuit of (2 ⁿ -1).
A shift circuit having a large shift amount of −M) bits is required. On the other hand, in the present invention, the first shifter circuit is a shift circuit having a maximum shift amount of 2 ^n-2 bits,
The second shifter circuit may be realized in 2 ⁰ bit shift circuit is the minimum shift amount, thus together both only (n-1) kinds (n + 1) number of, yet a power of 2 bit shift circuit Therefore, it is possible to provide a bit reverse operation circuit having a small circuit scale and good design efficiency.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a bit reverse operation circuit of the present invention. Upper (MN) bit processing circuit 3, lower N bit processing circuit 4 and addition (logical sum) circuit 5
The lower N-bit processing circuit 4 includes a first shifter circuit 6 composed of n number of bit-shift circuits to the power of 2 using the inverted control signal 2 and a second shifter circuit 2 for performing 2 ⁰ bit shift. It comprises a shifter circuit 7 and an M-bit reverse circuit 8. The upper (MN) bit processing circuit 3 outputs a signal in which the upper (MN) bits remain unchanged and the lower n bits are all 0s. The lower N-bit processing circuit 4
For the M-bit input signal 1, the (MN) bit left shifter circuit 9 by the first and second shifter circuits (MN)
Bit shift left, then bit reverse M bits. As a result, a signal in which the upper (M−N) bits are all 0 and the lower N bits are bit-reversed is output.
These two output signals are added by the adder circuit 5, and the upper (M−N) bits of the M-bit input signal remain unchanged and the lower N
The output signal 10 in which the bits are bit-reversed is output.

[0011]

As described above, according to the present invention,
A first shifter circuit for inputting a signal obtained by inverting a control signal and a second shifter circuit for performing a certain predetermined number of shifts are used for a circuit for (MN) bit shift used in a lower N bit processing circuit. As a result, it is possible to realize a bit reverse operation circuit whose circuit scale is smaller than that of the conventional system. Further, when there is a relationship of M = 3 × 2 ⁿ⁻² between M and n, the first shifter circuit is a shift circuit having a shift amount of at most 2 ⁿ⁻² bits and the second shifter circuit. may be realized in 2 ⁰ bit shift circuit is the minimum shift amount, thus together both only (n-1) kinds of (n + 1), yet can be realized only by a power bit shift circuit 2, (EN) Provided is a bit reverse operation circuit having a small circuit size and good design efficiency.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

[Explanation of symbols]

 1 ... M bit input signal 2 ... n bit control signal 3 ... Higher (MN) bit processing circuit 4 ... Lower N bit processing circuit 5 ... Adding circuit 6 ... First shifter circuit 7 ... Second shifter circuit 8 ... M-bit reverse circuit 9 ... (MN) bit left shifter circuit 10 ... Output signal

Claims (1)

[Claims] 1. For an M-bit input signal, n (2 ⁿ
A bit-reverse operation circuit that outputs a signal in which only the lower N bits are bit-reversed according to a numerical value N represented by the control signal by a control signal of ≧ M) bits and the lower N bits are output. Is higher (M-
N) bit processing circuit, lower N bit processing circuit, and adder circuit. A circuit for performing (M−N) bit shift is used in the lower N bit processing circuit.
-N) A circuit for performing a bit shift includes a first shifter circuit that uses a signal obtained by logically inverting all bits of the control signal as a control input signal, and a second shifter circuit that performs a predetermined number of shifts. In the bit reverse operation circuit, when there is a relation of M = 3 × 2 ^n-2 between M and n, the first shifter circuit is a 2 ⁰ bit shift circuit, a 2 ¹ bit shift circuit, a 2 ² bit shift circuit. circuit, the · · · 2 ^n-2 bit shift circuit and 2 ^n-2 bit shift circuit is composed of a power bit shift circuit having a total of n 2, also the second shifter circuit from 2 ⁰ bit shift circuit Bit reverse operation circuit characterized by