JPH0793310B2 - Semiconductor chip with electrode and mounting method thereof - Google Patents

Semiconductor chip with electrode and mounting method thereof

Info

Publication number
JPH0793310B2
JPH0793310B2 JP63261788A JP26178888A JPH0793310B2 JP H0793310 B2 JPH0793310 B2 JP H0793310B2 JP 63261788 A JP63261788 A JP 63261788A JP 26178888 A JP26178888 A JP 26178888A JP H0793310 B2 JPH0793310 B2 JP H0793310B2
Authority
JP
Japan
Prior art keywords
wire
semiconductor chip
electrode
metal
pillar
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP63261788A
Other languages
Japanese (ja)
Other versions
JPH02109339A (en
Inventor
昌弘 老田
徹 石田
泰彦 堀尾
俊雄 津田
芳宏 別所
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP63261788A priority Critical patent/JPH0793310B2/en
Publication of JPH02109339A publication Critical patent/JPH02109339A/en
Publication of JPH0793310B2 publication Critical patent/JPH0793310B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01221Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition
    • H10W72/01225Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition in solid form, e.g. by using a powder or by stud bumping
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221Structures or relative sizes
    • H10W72/222Multilayered bumps, e.g. a coating on top and side surfaces of a bump core
    • H10W72/223Multilayered bumps, e.g. a coating on top and side surfaces of a bump core characterised by the structure of the outermost layers, e.g. multilayered coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241Dispositions, e.g. layouts
    • H10W72/245Dispositions, e.g. layouts of outermost layers of multilayered bumps, e.g. bump coating being only on a part of a bump core
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251Materials
    • H10W72/252Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251Materials
    • H10W72/255Materials of outermost layers of multilayered bumps, e.g. material of a coating
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/551Materials of bond wires
    • H10W72/552Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]

Landscapes

  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、配線回路基板に、半導体チップを直付けする
ための方式、すなわち、チップオンボード(COB)、な
いしは、チップオングラス(COG)に十分に対応できる
電極付半導体チップに関するものである。
TECHNICAL FIELD The present invention is applicable to a method for directly attaching a semiconductor chip to a printed circuit board, that is, a chip-on-board (COB) or a chip-on-glass (COG). The present invention relates to a semiconductor chip with an electrode that can handle

従来の技術 近年、配線回路のフアイン化が進み、高密度実装の傾向
がしだいに強まり、殊に、半導体チップは裸のまま、な
いしは裸に近い状態で配線回路基板に実装することが必
要になってきている。とくにコンピュータでは、多層セ
ラミック基板上に100個前後の多端子チップを高密度に
搭載することはごく普通である。半導体チップを裸のま
ま、直に基板に実装する方法としては、ワイヤ・ボンデ
イング法とワイヤレスボンデイング法に大別され、後者
ではとくにフィルムキャリア(TAB)法、フリップチッ
プ(CCB)法がもっともよく知られている。
2. Description of the Related Art In recent years, wiring circuits have become finer, and the tendency for high-density mounting has gradually increased. In particular, it is necessary to mount semiconductor chips on a printed circuit board in a bare state or in a state close to a bare state. Is coming. Especially in computers, it is very common to mount a high density of about 100 multi-terminal chips on a multilayer ceramic substrate. The method of directly mounting a semiconductor chip on a substrate directly without a wire is roughly classified into a wire bonding method and a wireless bonding method. Among them, the film carrier (TAB) method and the flip chip (CCB) method are the most well known. Has been.

TAB法は、日本マイクロエレクトロニクス協会編「IC化
実装技術」P.84(工業調査会1980)に記載されているよ
うに、テープキャリア用のベアチップの電極構成法であ
り、その概要を第2図に示す。熱酸化SiO22で被覆され
たシリコン1上にAl3を真空蒸着法で形成し、ホトリソ
グラフィ技術により、Al3を所望の位置にのみ残す。さ
らに、蒸着とホトリソグラフィを繰り返しながら、パッ
シベーション膜としてSiO2ないしはガラスの保護膜4を
所望の位置に形成し、Al3の電極パッド上には、CrやTi
等の密着用の金属5、さらにこの上に、Cu,Ni,W,Pt,Ag
等の拡散バリヤ金属6を順次生成させる。つづいて、め
っきによってAuのバンプ金属7を形成し、これを外部接
続端子としてリードフレームに接続することによって、
いわゆるインナーボンデイングを行なう。
The TAB method is a bare chip electrode construction method for tape carriers, as described in "IC Packaging Technology" P.84 (Industrial Research Association 1980) edited by the Japan Microelectronics Association, and its outline is shown in FIG. Shown in. Al 3 is formed on the silicon 1 covered with the thermally oxidized SiO 2 by a vacuum deposition method, and Al 3 is left only at a desired position by a photolithography technique. Further, by repeating vapor deposition and photolithography, a SiO 2 or glass protective film 4 is formed at a desired position as a passivation film, and Cr or Ti is deposited on the Al 3 electrode pad.
Adhesion metal 5 such as Cu, Ni, W, Pt, Ag
A diffusion barrier metal 6 such as is sequentially generated. Then, by forming Au bump metal 7 by plating and connecting it to the lead frame as an external connection terminal,
So-called inner bonding is performed.

フリップチップ法については、前出の参考文献のP.80な
らびに、特開昭58−51511号公報にその概要についての
記載がある。この方法の特徴は、チップを裏返しにして
その表面に構成された電極を介して、配線回路基板にベ
アチップを直付けで接続するものである。第2図におい
て、Auのバンプ金属7の代りに、Auめっきを下地にして
はんだのバンプをはんだ浸漬法等により被着させたもの
が、一般に、よく知られているコントロールドコラップ
スフリップチップの構造である。フリップチップにはほ
かに、電極に金属ボールをつけるボール方式(IBM社のS
LT)や、Alバンプ、およびペデステル方式もあり、あと
の方式はいずれも超音波圧着による接続で1チップごと
にボンデイングしなければならないので不便であり、バ
ンプの形成のさい、チップ自体に損傷を与えないよう細
心の注意が必要である。
Regarding the flip chip method, the outline thereof is described in P.80 of the above-mentioned reference and JP-A-58-51511. The feature of this method is that the chip is turned upside down and the bare chip is directly connected to the printed circuit board through the electrodes formed on the surface of the chip. In FIG. 2, instead of the Au bump metal 7, a bump of solder is adhered by a solder dipping method or the like using Au plating as a base, and the structure of a well-known controlled collapse flip chip is generally known. Is. In addition to the flip chip, a ball method in which a metal ball is attached to the electrode (IBM S
LT), Al bump, and pedestal method. All the other methods are inconvenient because they have to be bonded by chip by ultrasonic pressure bonding, and the chip itself is damaged when bumps are formed. You need to be very careful not to give it.

発明が解決しようとする課題 しかしながら、これらの方法は、いずれも高価な蒸着装
置を用いての真空蒸着工程を必要とし、しかも厄介なこ
とは、密着用金属のCrやTiは、きわめて酸化されやす
く、その結果、その上にCuなどの拡散バリヤ用金属をす
ばやく連続して蒸着しなければならないこと、フリップ
チップ法において、はんだ浸漬法ではんだバンプをつく
るとき、バンプの高さの均一性の維持がきわめて困難で
あること、また、所望の位置に蒸着金属等を形成するた
めに煩雑なホトリソグラフィ技術を繰り返し用いなけれ
ばならないこと、さらには、電極パッドのアルミ上に
は、酸化アルミの薄い層が空気酸化の結果生じているの
で、アルミとクロムとの接着強度が十分に得られないこ
とがあり、クロムが剥離するという問題が発生するこ
と、また、そのさいに、目視検査がきわめてむつかしい
こと等の欠点があった。
However, all of these methods require a vacuum vapor deposition step using an expensive vapor deposition apparatus, and the problem is that Cr and Ti of the adhesion metal are extremely easily oxidized. As a result, a diffusion barrier metal such as Cu must be vapor-deposited continuously in quick succession, and when the solder bumps are formed by the solder dipping method in the flip chip method, the height uniformity of the bumps is maintained. Is extremely difficult, and complicated photolithography technology must be repeatedly used to form a vapor-deposited metal or the like at a desired position. Furthermore, a thin layer of aluminum oxide is formed on the electrode pad aluminum. Occurs as a result of air oxidation, which may result in insufficient adhesion strength between aluminum and chromium, resulting in the problem of chromium peeling. In addition, there was a defect that the visual inspection was extremely difficult.

課題を解決するための手段 本発明は、上記のような欠点のない電極付半導体チップ
を提供することを意図するものであって、半導体チップ
において、その電極パッドに、ワイヤをボンデングし、
ワイヤ・ピラーを形成し、そのワイヤ・ピラーを配線回
路基板に直接ボンデングするために、ワイヤ・ピラーを
金属で補強することを特徴とするものである。
Means for Solving the Problems The present invention is intended to provide an electrode-equipped semiconductor chip without the above-mentioned drawbacks, in which the electrode pad of the semiconductor chip is bonded with a wire,
In order to form the wire pillar and to bond the wire pillar directly to the printed circuit board, the wire pillar is reinforced with metal.

作用 上記の本発明の半導体ベアチップの外部接続用の電極
は、電極の芯部を構成するワイヤのAl電極パッドへの接
続には接続技法としてすでに確立されたきわめて信頼性
の高いワイヤボンデング技術にもとづいていること、さ
らに、ボンデング後のワイヤにはめっきを施してめっき
金属を被覆することにより、電極ピラーを形成している
ことからアルミ電極パッドとの接触はいっそう確実とな
り、めっきにより補強されたピラー電極はきわめて堅牢
であるので、はんだによる直付にさいして、取扱いが便
利であり、たとえ、外力が加わったとしても半導体チッ
プが損傷することがない。
The electrode for external connection of the above-mentioned semiconductor bare chip of the present invention is an extremely reliable wire bonding technology already established as a connection technique for connecting the wire forming the core of the electrode to the Al electrode pad. Moreover, since the wire after bonding is plated and coated with plating metal to form the electrode pillar, the contact with the aluminum electrode pad becomes more reliable, and it is reinforced by plating. Since the pillar electrode is extremely robust, it is easy to handle when directly attached by soldering, and the semiconductor chip is not damaged even if external force is applied.

実施例 つぎに、本発明の実施例について図面を用いて説明す
る。
Example Next, an example of the present invention will be described with reference to the drawings.

実施例1 ホトリソグラフィ技術を用いて、SiO22の膜を有するシ
リコン1の基体の上に、アルミ3の電極および、所望の
位置にSiO2等の保護膜4を形成した裸の半導体チップを
用意する。アルミ3の電極パッドに直径30ミクロンのAu
線をボンデング装置でボンデングし、170ミクロンの長
さのワイヤ・ピラー8を形成した。しかるのちに、ワイ
ヤ・ピラー8のまわりに、シプレイ社の無電解Niめっき
液ニポジット468を用いて、作業温度68℃で、2時間め
っきを行なって、Au線に18ミクロンの厚さの金属ニッケ
ルを補強材9として被覆した。こうして得られた半導体
チップの外部接続用の電極端子は、Au線だけの場合にく
らべると、かたいニッケルめっきにより十分に補強され
ているために、きわめて堅牢で、取扱いに便利なもので
あった。ピラー電極とAl電極パッドとの接触状態を目視
とテスタで試験したところ、接触不良は皆無であった、
また、配線回路基板にあらかじめ塗布したクリームはん
だ上にこのチップを装着して、この基板を加熱し、クリ
ームはんだを溶融してはんだづけを行なういわゆるリフ
ロー方式でチップを容易に直付けすることができた。上
記のNiめっきの代りに、Agペイントを用いて、Auのワイ
ヤ・ピラーを被覆することも考えられるが、この場合、
ワイヤ・ピラーの補強はめっきに比べるとやや劣るこ
と、さらには、はんだづけにさいして、はんだによるAg
喰われが生じる虞れがあること等の不具合がある。ワイ
ヤ・ピラーへのめっきについては、Niめっきの代りに、
Au,Cu,Sn,はんだ等のめっきに適する金属で、かつのち
のボンデイングに適する金属であればいずれも本発明の
主旨にかなっており、場合によってはこれらのめっきを
いくつか組み合せることも効果的である。
Example 1 Using a photolithography technique, a bare semiconductor chip in which an electrode of aluminum 3 and a protective film 4 of SiO 2 or the like are formed at a desired position on a substrate of silicon 1 having a film of SiO 2 2 is formed. prepare. 30 μm diameter Au on aluminum 3 electrode pad
The wire was bonded with a bonding device to form a 170 micron long wire pillar 8. After that, around the wire pillar 8, plating was performed for 2 hours at an operating temperature of 68 ° C. using an electroless Ni plating solution Nipposit 468 manufactured by Shipley Co., and the Au wire was coated with metallic nickel having a thickness of 18 microns. Was coated as the reinforcing material 9. The electrode terminal for external connection of the semiconductor chip obtained in this way was extremely rugged and easy to handle because it was sufficiently reinforced by hard nickel plating compared to the case of using only Au wire. . When the contact state between the pillar electrode and the Al electrode pad was examined visually and with a tester, no contact failure was found,
In addition, the chip could be mounted directly on the cream solder pre-applied to the printed circuit board, the board was heated, the cream solder was melted, and soldering was performed so that the chip could be directly attached directly. . Instead of the above Ni plating, Ag paint may be used to coat the Au wire pillar, but in this case,
Reinforcement of wire pillars is slightly inferior to that of plating. Furthermore, when soldering, Ag
There are problems such as the possibility of biting. For plating on wire pillars, instead of Ni plating,
Au, Cu, Sn, a metal suitable for plating such as solder, and any metal suitable for later bonding is within the scope of the present invention, and in some cases, it is also effective to combine some of these platings. Target.

実施例2 実施例1と同様に、ベアチップのAlの電極パッドに、直
径32ミクロンのAu線をワイヤボンデングし、370ミクロ
ンの高さのピラーを形成し、実施例1で述べた方法と同
様にしてニッケルめっきを行なってから、さらに、シア
ン金カリウム15g/、ピロリン酸カリウム30g/からな
るAuめっき液を用いて、操作温度30℃、電流密度1A/dm2
で電解Auめっきを行なって、約1.2ミクロンのAuめっき
をピラー電極の先端からほぼ150ミクロンのところつま
りはんだづけ部に析出させた。
Example 2 Similar to Example 1, wire bonding of an Au wire having a diameter of 32 μm was performed on an Al electrode pad of a bare chip to form a pillar having a height of 370 μm, and the same method as described in Example 1 was performed. Nickel plating, and then using an Au plating solution consisting of potassium cyanide potassium 15 g / and potassium pyrophosphate 30 g /, operating temperature 30 ° C., current density 1 A / dm 2
Electrolytic Au plating was performed to deposit about 1.2 μm of Au plating on the soldered part approximately 150 μm from the tip of the pillar electrode.

こうして得られたピラー電極付、接触不良が皆無であ
り、配線回路基板に、接着し、溶融はんだ噴流中に、浸
漬してはんだづけをフロー方式で行なうことで、直付け
が可能であった。さらに、はんだづけ以外の他のボンデ
ング法としては、配線回路基板にSnめっきを施したもの
を用いると、Au−Sn共晶合金の生成による接続も可能と
なる。
With the pillar electrodes thus obtained, there was no contact failure, and direct bonding was possible by bonding to a printed circuit board, immersing in a molten solder jet, and performing soldering in a flow system. Further, as a bonding method other than soldering, if a wiring circuit board plated with Sn is used, connection can be achieved by forming an Au—Sn eutectic alloy.

実施例3 実施例1のAu線の代りに、直径35ミクロンのAl−Si1%
の細線をボンデングした。このワイヤ・ピラーをか性ソ
ーダ50g/、酸化亜鉛7g/、塩化第2鉄2g/、ロッセ
ル塩50g/、硝酸ソーダ1g/からなる処理液に浸漬
し、25℃で20秒間処理して実施例1と同様の方法でニッ
ケルめっきを行なった。得られた結果は、実施例1と比
べて、ピラー電極の強度および接触不良率は、共に遜色
のないものであった。また、ボンデング用のワイヤとし
て、Alの線の代りにCu線を用いることもできるが、この
場合には、ZnCl2の処理は、不要となる。
Example 3 Instead of the Au wire of Example 1, 35% diameter Al-Si 1%
Bonded the thin wire. This wire pillar was dipped in a treatment solution consisting of caustic soda 50 g /, zinc oxide 7 g /, ferric chloride 2 g /, Rochelle salt 50 g /, and sodium nitrate 1 g /, and treated at 25 ° C for 20 seconds. Nickel plating was performed in the same manner as in 1. The obtained results were comparable to the strength of the pillar electrode and the contact failure rate in comparison with Example 1. Further, as a wire for bonding, a Cu wire can be used instead of the Al wire, but in this case, the treatment with ZnCl 2 becomes unnecessary.

発明の効果 本発明の半導体チップの外部接続用電極端子の構成は、
金属ワイヤをAl電極パッドに、ボンデイングし、その上
に金属をめっきすることによって被覆した高信頼性のピ
ラー状の電極であり、ワイヤ・ピラーがめっきによっ
て、十分に補強されていて、非常に丈夫であることから
取扱いが容易であり、COB用のベアチップの電極として
は申し分のないものとなっている。また高価な蒸着装置
を用いての蒸着作業が不要であるばかりでなく、煩雑な
ホトリソグラフィ工程も軽減される利点がある。さら
に、ボンデイングの接触不良の有無は、特別な検査装置
によらなくても目視でもかんたんに検査できるので好都
合である。裸のままのチップを位置合せして、配線回路
基板に並べて、一度炉を通すだけで一括ボンデングする
いわゆるCOB方式での装着が容易であり、高密度実装化
に好適である。また、従来のフリップチップ方式では、
電極のバンプを一定の高さに調節することはかなりむつ
かしかったが、本発明によると、高さの調節はきわめて
容易であり、かつその形状やサイズも従来よりはるかに
自由に、選択できる長所がある。
The structure of the electrode terminal for external connection of the semiconductor chip of the present invention is
It is a highly reliable pillar-shaped electrode in which a metal wire is bonded to an Al electrode pad and plated with a metal, and the wire pillar is sufficiently reinforced by plating and is extremely durable. Therefore, it is easy to handle and it is a perfect electrode for a bare chip for COB. Further, there is an advantage that not only the vapor deposition work using an expensive vapor deposition apparatus is unnecessary but also the complicated photolithography process is reduced. Furthermore, the presence or absence of contact failure in the bonding can be easily inspected visually without using a special inspection device, which is convenient. The so-called COB method, in which the bare chips are aligned, arranged on the printed circuit board, and batch-bonded only by passing through the furnace once, is easy and suitable for high-density mounting. Also, in the conventional flip chip method,
Adjusting the electrode bumps to a certain height was quite difficult, but according to the present invention, the height adjustment is extremely easy, and its shape and size are far more freely selectable than the conventional ones. is there.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明に係る外部接続用のピラー状の電極付半
導体チップの断面図、第2図は従来のCOB用のバンプ状
の電極付半導体チップの断面図である。 1……シリコン、2……SiO2、3……Al、4……保護
膜、5……密着用金属、6……拡散バリヤ金属、7……
バンプ金属、8……ワイヤ・ピラー、9……補強材。
FIG. 1 is a sectional view of a pillar-shaped semiconductor chip with electrodes for external connection according to the present invention, and FIG. 2 is a sectional view of a conventional bump-shaped semiconductor chip with electrodes for COB. 1 ... Silicon, 2 ... SiO 2 , 3 ... Al, 4 ... Protective film, 5 ... Adhesion metal, 6 ... Diffusion barrier metal, 7 ...
Bump metal, 8 …… Wire pillar, 9 …… Reinforcement material.

フロントページの続き (72)発明者 津田 俊雄 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 別所 芳宏 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (56)参考文献 特開 昭58−182248(JP,A)Front page continued (72) Inventor Toshio Tsuda 1006 Kadoma, Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Yoshihiro Bessho, 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. (56) Reference Document JP-A-58-182248 (JP, A)

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】半導体チップの電極パッド上に、ワイヤボ
ンディング可能な金属を用いて、ワイヤピラーを形成し
た電極付半導体チップにおいて、前記ワイヤピラーを金
属で被覆して補強したことを特徴とする電極付半導体チ
ップ。
1. An electrode-equipped semiconductor chip having a wire pillar formed by using a wire-bondable metal on an electrode pad of the semiconductor chip, wherein the wire pillar is covered with metal to be reinforced. Chips.
【請求項2】金属はめっき金属であることを特徴とする
請求項(1)記載の電極付半導体チップ。
2. The electrode-equipped semiconductor chip according to claim 1, wherein the metal is a plated metal.
【請求項3】ワイヤボンディング可能な金属がAu,Alな
いしはCuを主成分とするものであることを特徴とする請
求項(1)記載の電極付半導体チップ。
3. A semiconductor chip with an electrode according to claim 1, wherein the wire-bondable metal contains Au, Al or Cu as a main component.
【請求項4】ワイヤボンディング可能な金属を用いて、
ワイヤピラーを半導体チップの電極パッド上に形成し、
前記ワイヤピラーを金属で被覆することにより前記ワイ
ヤピラーを補強した電極付半導体チップを、配線回路基
板へ半田付けにより直接ボンディングすることを特徴と
する半導体チップの実装方法。
4. A wire-bondable metal is used,
Wire pillars are formed on the electrode pads of the semiconductor chip,
A method of mounting a semiconductor chip, comprising: directly bonding an electrode-equipped semiconductor chip, in which the wire pillar is reinforced by covering the wire pillar with a metal, to a printed circuit board by soldering.
【請求項5】配線回路基板への直接ボンディングが、非
晶接合、熱圧着であることを特徴とする請求項(4)記
載の半導体チップの実装方法。
5. The method of mounting a semiconductor chip according to claim 4, wherein the direct bonding to the printed circuit board is amorphous bonding or thermocompression bonding.
【請求項6】ワイヤピラーの被覆をめっき法で行うこと
を特徴とする請求項(4)または(5)記載の半導体チ
ップの実装方法。
6. The method of mounting a semiconductor chip according to claim 4, wherein the coating of the wire pillar is performed by a plating method.
JP63261788A 1988-10-18 1988-10-18 Semiconductor chip with electrode and mounting method thereof Expired - Lifetime JPH0793310B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63261788A JPH0793310B2 (en) 1988-10-18 1988-10-18 Semiconductor chip with electrode and mounting method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63261788A JPH0793310B2 (en) 1988-10-18 1988-10-18 Semiconductor chip with electrode and mounting method thereof

Publications (2)

Publication Number Publication Date
JPH02109339A JPH02109339A (en) 1990-04-23
JPH0793310B2 true JPH0793310B2 (en) 1995-10-09

Family

ID=17366719

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63261788A Expired - Lifetime JPH0793310B2 (en) 1988-10-18 1988-10-18 Semiconductor chip with electrode and mounting method thereof

Country Status (1)

Country Link
JP (1) JPH0793310B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6835898B2 (en) 1993-11-16 2004-12-28 Formfactor, Inc. Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures
JP4863746B2 (en) * 2006-03-27 2012-01-25 富士通株式会社 Semiconductor device and manufacturing method thereof
JP4597940B2 (en) * 2006-10-26 2010-12-15 富士通セミコンダクター株式会社 External connection terminal

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58182248A (en) * 1982-04-19 1983-10-25 Mitsubishi Electric Corp Semiconductor device

Also Published As

Publication number Publication date
JPH02109339A (en) 1990-04-23

Similar Documents

Publication Publication Date Title
US6346469B1 (en) Semiconductor device and a process for forming the semiconductor device
US7449406B2 (en) Semiconductor element and a producing method for the same, and a semiconductor device and a producing method for the same
JPH09129647A (en) Semiconductor element
JP3297177B2 (en) Method for manufacturing semiconductor device
WO2004056162A1 (en) Flip-chip mounting electronic component and method for producing the same, circuit board and method for producing the same, method for producing package
CN1350420A (en) Method for electroplating solder on organic circuit board
JPH08139097A (en) Connection ball for flip chip and method for joining semiconductor chip
JP3475558B2 (en) Ball for bonding semiconductor chip and method for bonding semiconductor chip
JPH0793310B2 (en) Semiconductor chip with electrode and mounting method thereof
GB2364172A (en) Flip Chip Bonding Arrangement
JPH04263434A (en) Formation of electric connection contact and manufacture of mounting board
JP2000012605A (en) Method of forming electrode portion of semiconductor chip
JPH02276249A (en) Manufacture of semiconductor circuit bump
JPH02312240A (en) Formation of bump
JPS63168028A (en) Fine connection structure
JPH11135533A (en) Electrode structure, silicon semiconductor device provided with the electrode, method of manufacturing the same, circuit board mounted with the device, and method of manufacturing the same
JP3311376B2 (en) Bump forming method
JPS62104143A (en) Formation of solder bump
JPS63289947A (en) Substrate with solder bump and manufacture thereof
JPH0732170B2 (en) Semiconductor device
JPH05175408A (en) Material and method for mounting semiconductor element
TW483057B (en) Semiconductor device with bump electrode
JPH0745664A (en) Semiconductor device mounting method
JPS6366949A (en) Forming method for solder bump
JPS6358945A (en) Formation of solder bump