JPH0793370B2 - Semiconductor device - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor device including a sense circuit using a MOS transistor.

[Technical background of the invention and its problems]

In recent years, high integration of integrated circuits such as MOS semiconductor memory and miniaturization of elements have been rapidly advanced.

In a MOS type semiconductor memory, a sense circuit that uses a pair of MOS transistors to detect a minute potential difference by utilizing the difference in conductance is often used, for example, in an address buffer.

FIG. 4 shows the basic configuration of such a sense circuit. First
MOS transistors Q ₁ and a second MOS transistor Q ₂ are sources commonly connected, a drain, a gate have been cross-connected to each other, the difference in the respective gate That potential entering nodes N _1, N _2, the MOS Detection is performed by using the difference in conductance between the transistors Q ₁ and Q ₂ .

FIG. 5 shows a layout example of such a sense circuit on a semiconductor substrate. 51 and 52 are MOS transistors Q ₁ and Q ₂ , respectively
Gate electrode and is usually formed of a polycrystalline silicon film. Reference numerals 53 and 54 denote n ⁺ type layers that serve as drains of the MOS transistors Q ₁ and Q ₂ , and 55 denotes an n ⁺ type layer that serves as a common source. The n ⁺ type layers 53, 54, 55 are usually formed in a self-aligned manner by using ion implantation with the gate electrodes 51 and 52 as a mask.

By the way, at present, MOS type semiconductor memory has a gate length of 2 μm.
Although miniaturization is progressing to some extent, this is 1 in the near future
It is about to be reduced to about μm. When the gate length is shortened in this way, hot carriers are generated by the high electric field near the drain, and these are injected into the gate insulating film.
It causes the characteristic variation of the MOS transistor. This is called the so-called hot carrier effect, and has been found to be a serious problem in the reliability of MOS integrated circuits. One effective way to solve this problem is to source the MOS transistor,
That is, the LDD structure or the GDD structure in which the low impurity concentration layer is provided on the channel region side of the drain region is adopted.

FIG. 6 shows an LDD structure MOS transistor. 61 is p-type Si
A substrate, 62 is a gate electrode made of a polycrystalline silicon film formed on this substrate, 63 and 64 are n ⁺ type layers serving as a source and a drain, and these are selected on the side wall of the gate electrode 62. Ion implantation is performed while the insulating film is formed (not shown). At the ends of the channel regions of these n ⁺ type layers 63 and 64, ion implantation is performed using the gate electrode 62 as a mask to form n ⁻ type layers 65 and 66 of low impurity concentration.

When a MOS transistor having such an LDD structure or GDD structure is used to previously configure the sense circuit as shown in FIGS. 4 and 5, when the gate length of the MOS transistor becomes shorter than the present, Such problems will become more serious. As described above, the source and drain regions are formed by ion implantation using the gate electrode as a mask. In general, ion implantation is performed by tilting the implantation direction at a predetermined angle with respect to the substrate surface in order to prevent the channeling phenomenon on the substrate. Done. This is shown in FIG. 67 is the ion implantation direction. When the n ⁻ type layers 65 and 66 of the source and the drain are formed by such ion implantation, n is formed on the shadow side of the gate electrode 62.
^- offset distance d as shown between the mold layer 65 and the gate electrode 62 occurs. As a result, the parasitic resistance becomes larger on the side where the offset occurs than in the ideal case shown in FIG. As is well known, a MOS transistor has a small transconductance when the source parasitic resistance is large. That is, in the structure as shown in FIG. 7, the source and drain are not symmetrical, and the characteristics differ when the offset side is used as the source and the drain. Therefore, when the sense circuit shown in FIG. 4 is constructed in the conventional layout as shown in FIG. 5, a pair is formed.
Characteristic imbalance occurs between the MOS transistors Q ₁ and Q ₂ . As a result, the sense sensitivity to the potential difference is greatly deteriorated. The state of this sense sensitivity deterioration is shown by the broken line in FIG. This deterioration in sense sensitivity becomes greater as the element becomes finer.

[Object of the Invention]

An object of the present invention is to provide a semiconductor device having a sensor circuit that solves the above problems.

[Outline of Invention]

The present invention considers the pattern layout on the substrate of the sense circuit, and the first and second MOs forming the sense circuit.
In the ion implantation for forming the source and drain, the S-transistor is equally affected by the inclination of the implantation direction.

That is, according to the present invention, the sources are commonly connected and the drain and the gate are cross-connected to each other, and the first and second MOS transistors are configured to detect the difference in potentials entering the respective gates by using the difference in conductance. In the semiconductor device having a sense circuit for
Each MOS transistor has one transistor region or a plurality of transistor regions connected in parallel, and the transistor regions having the same channel current direction have the same gate width between the first and second MOS transistors. The area of the portion where all the gate electrodes and the source region existing in the transistor region having the same channel current direction between the first and second MOS transistors overlap each other is It is characterized in that all the gate electrodes existing in the transistor regions having the same direction and the drain region are larger or smaller than the area of the overlapping portion.

In other words, the present invention provides first and second MOSs whose sources are commonly connected and whose drains and gates are cross-connected to each other.
A semiconductor device having a sense circuit configured by a transistor, the sense circuit detecting a potential difference between respective gates by using a difference in conductance.
The MOS transistor has a single transistor region or a plurality of transistor regions connected in parallel.
In the MOS transistor of, the conductance changes depending on the direction of the channel current, and the first and second MOS transistors
In the transistor region where the direction of the channel current is the same between the transistors, the conductances are changed in the same manner.

In other words, the present invention provides first and second MOSs whose sources are commonly connected and whose drains and gates are cross-connected to each other.
A semiconductor device having a sense circuit configured by a transistor, the sense circuit detecting a potential difference between respective gates by using a difference in conductance.
The MOS transistor has a single transistor region or a plurality of transistor regions connected in parallel.
In the above MOS transistor, the positional relationship between the source and the drain is asymmetrical with respect to the gate, and
In the transistor region in which the channel current directions are the same between the first and second MOS transistors, the asymmetric relationship is the same.

In other words, the present invention provides first and second MOSs whose sources are commonly connected and whose drains and gates are cross-connected to each other.
A semiconductor device having a sense circuit configured by a transistor, the sense circuit detecting a potential difference between respective gates by using a difference in conductance.
The MOS transistor has a single transistor region or a plurality of transistor regions connected in parallel.
In the second MOS transistor, in the transistor region in which the parasitic resistance of the source and that of the drain are different and the direction of the channel current is the same between the first and second MOS transistors, the parasitic resistance for the source and drain is It is characterized in that the resistances differ in the same way.

〔The invention's effect〕

According to the present invention, the first and second parts forming the sense circuit
Since the MOS transistor is affected by the inclination of the implantation direction in the ion implantation process for forming the source and drain, the source and drain parasitic resistances become equal. As a result, it is possible to obtain a semiconductor device that realizes a sense circuit with high sense sensitivity by using a fine MOS transistor structure.

Example of Invention

 Examples of the present invention will be described below.

FIG. 1 is a pattern layout of the sense circuit portion of one embodiment. The equivalent circuit of the sense circuit is the same as that of FIG. 4 described above. In this embodiment, the first and second MOS transistors Q ₁ and Q ₂ are each constituted by two transistor regions connected in parallel. That is, the portions of the gate electrodes 11 ₁ and 11 ₂ formed by the continuous polycrystalline silicon film become the two transistor regions Q ₁₁ and Q ₁₂ that form the _first MOS transistor Q ₁ . Also, two gate electrodes 11 ₃ and 11 ₄ formed by a continuous polycrystalline silicon film, which are laid out symmetrically with respect to this, form two transistor regions Q ₂₁ and Q ₂₂ which form the _second MOS transistor Q _2.
Has become. In this embodiment, the gate lengths of all the transistor regions are all the same and the gate widths are all the same. Reference numeral 12 ₁ is an n ⁺ type layer which will be the source regions of the transistor regions Q ₁₁ and Q ₂₁ , and 12 ₂ is an n ⁺ type layer which will be the source regions of the transistor regions Q ₁₂ and Q ₂₂ . 13 ₁ is the transistor area Q ₁₁
And an n ⁺ -type layer serving as a drain region of Q _12, 13 ₂ are n ⁺ -type layer serving as a drain region of the transistor region Q ₂₁ and Q _22. These n ⁺ -type layers are the gate electrodes 11 ₁ to ₁ 1 as in the conventional case.
It is formed by ion implantation, leaving the insulating film on the sidewalls of 1 _4. Although not shown in the figure, the gate electrodes 11 ₁ to 1
1 ₄ ion implanting respective source performs as a mask, n the channel region side end portion of the drain region ^- an LDD structure or GDD structure to form a mold layer. The metal wirings forming the sense circuit are shown by thick lines for convenience of illustration.

In the two transistor regions Q ₁₁ and Q ₁₂ forming the first MOS transistor Q ₁ , the directions of the channel currents are opposite on the substrate. Similarly, between the two transistor regions Q ₂₁ and Q ₂₂ forming the _second MOS transistor Q ₂ , the direction of the channel current is opposite on the substrate. But the first MOS transistor Q
Looking between ₁ and the second MOS transistor Q ₂ , the direction of the channel current is the same in the transistor regions Q ₁₁ and Q ₂₁ ,
Similarly, the transistor regions Q ₁₂ and Q ₂₂ have the same channel current direction.

With such a layout, the influence of the inclination of the implantation direction in the ion implantation process for forming the source and drain appears equally between the transistor regions Q ₁₁ and Q ₂₁ , and similarly between the transistor regions Q ₁₂ and Q ₂₂ . Appear equally. After all, according to this embodiment, the characteristics of the first MOS transistor Q ₁ and the second MOS transistor Q ₂ which form the sense circuit are equally affected by the inclination of ion implantation, and the same gate voltage is applied. Conductance becomes equal.

That is, in the first and second MOS transistors Q1 and Q2,
Conductance depends on the direction of the channel current,
Further, the transistor region Q11 and the transistor region Q21, and the transistor region Q12 and the transistor region Q in which the channel current directions are the same between the first and second MOS transistors
At 22, the conductance changes are the same.

In other words, the ion implantation forms a positional relationship between the source and drain in the asymmetrical relationship with respect to the gate in the first and second MOS transistors Q1 and Q2, and
The transistor regions Q11 and Q21 having the same channel current direction between the first and second MOS transistors have the same asymmetrical relationship, and similarly the transistor regions Q12 and Q22 have the same asymmetrical relationship. .

In other words, the first and second MOs are implanted by the ion implantation.
In the S transistors Q1 and Q2, the parasitic resistance of the source is different from that of the drain, and the direction of the channel current is the same between the first and second MOS transistors. The difference is the same, and similarly the transistor area
The difference in the above parasitic resistances in Q12 and transistor region Q22 is the same.

The solid line in FIG. 2 shows the simulation result of the potential difference sense sensitivity of the sense circuit according to this embodiment. It is clear that it exhibits excellent sense sensitivity characteristics as compared with the conventional example.

In the above-mentioned embodiment, the first and the second which constitute the sense circuit
Although each MOS transistor is composed of two transistor regions, the present invention can be applied to the case where each MOS transistor is composed of one transistor region.

FIG. 3 is a layout of the sense circuit portion of such an embodiment. The gate electrodes 31 ₁ and 31 ₂ made of a polycrystalline silicon film form the first and second MOS transistors Q ₁ and Q ₂ , respectively. The gate length and the gate width of each transistor part are the same. Reference numeral 32 is an n ⁺ type layer that serves as a common source region, and 33 ₁ and 33 ₂ are n ⁺ type layers that serve as drain regions of the first and second MOS transistors Q ₁ and Q ₂ , respectively. Although omitted in the figure, in this embodiment as well, the drain region and the source region are provided at the end portions on the channel region side.
An n ^- type layer is formed to have an LDD structure or a GDD structure. The construction process is similar to that of the previous embodiment.

In the case of this embodiment, when a transistor having a large gate width is used, the pattern becomes elongated as compared with the previous embodiment.
If such a pattern layout is allowed in relation to other circuits, there is no problem. Also in the case of this embodiment, each MO
Since the S transistors Q ₁ and Q ₂ are laid out so that the channel current directions are the same, the inclinations of the implantation directions of the source and drain in the ion implantation process are the same for both transistors Q ₁ and Q 2.
Appears equal to _two . As a result, excellent sense sensitivity can be obtained even in this sense circuit.

The present invention is particularly effective when the element is miniaturized and the LDD structure or the GDD structure is introduced as described in the above embodiments, but it is applied to the case of a normal MOS transistor structure not using these structures. But still effective. Others The present invention can be variously modified and implemented without departing from the spirit thereof.

[Brief description of drawings]

FIG. 1 shows a pattern of a sense circuit unit according to an embodiment of the present invention.
A layout diagram, FIG. 2 is a diagram showing sensitivity characteristics of the sense circuit in comparison with a conventional example, FIG. 3 is a pattern layout diagram of a sense circuit portion of another embodiment, and FIG. 4 is a MOS transistor. FIG. 5 is a diagram showing the basic configuration of a sense circuit, FIG. 5 is a pattern layout diagram of a conventional sense circuit, and FIG. 6 is
FIG. 7 is a diagram showing the LDD structure of a MOS transistor, and FIG. 7 is a diagram for explaining the influence of the inclination in the ion implantation direction on the transistor characteristics. Q ₁₁ , Q ₁₂ ...... Transistor area of the _first MOS transistor (Q ₁ ), Q ₂₁ , Q ₂₂ ...... Transistor area of the second MOS transistor (Q ₂ ), 11 _{1 to} 11 ₄ ...... Gate electrode, 12 ₁ , 12, ₂ …
… N ⁺ type layer (source region), 13 ₁ , 13 ₂ …… n ⁺ type layer (drain region), 31 ₁ , 31 ₂ …… Gate electrode, 32 …… n ⁺ type layer (source region), 33 ₁ , 33 ₂ …… n ⁺ type layer (drain region).

Claims (8)

[Claims] 1. A first MOS transistor and a second MOS transistor, the sources of which are commonly connected, and the drain and the gate of which are cross-connected to each other. The difference between the potentials applied to the respective gates is detected by using the difference in conductance. In a semiconductor device having a sense circuit, each of the first and second MOS transistors has one or a plurality of transistor regions connected in parallel, and a channel current between the first and second MOS transistors. All the gate electrodes that are laid out so that the gate widths of the transistor regions having the same direction are the same, and that exist in the transistor regions having the same channel current direction between the first and second MOS transistors. And the area where the source region overlaps,
A semiconductor device, characterized in that the area is larger or smaller than the area of a portion where all the gate electrodes and the drain regions existing in the transistor regions having the same channel current direction overlap each other. 2. The first and second MOS transistors,
The semiconductor device according to claim 1, further comprising a low impurity concentration layer on the channel region side of the source and drain regions. 3. A first MOS transistor and a second MOS transistor, the sources of which are commonly connected, and the drain and the gate of which are cross-connected to each other. The difference between the potentials applied to the respective gates is detected by using the difference in conductance. In a semiconductor device having a sense circuit, each of the first and second MOS transistors has one or a plurality of transistor regions connected in parallel, and the conductance is a channel current. In the transistor region in which the direction of the channel current is the same between the first and second MOS transistors, the semiconductor device has the same change in the conductance. 4. The first and second MOS transistors are
4. The semiconductor device according to claim 3, wherein the semiconductor device has a low impurity concentration layer on the channel region side of the source and drain regions. 5. A first and a second MOS transistor, whose sources are commonly connected and whose drain and gate are cross-connected to each other, detect the potential difference between the respective gates by utilizing the difference in conductance. In a semiconductor device having a sense circuit, each of the first and second MOS transistors has one or a plurality of transistor regions connected in parallel, and the first and second MOS transistors have a source and a drain. Is asymmetrical with respect to the gate, and the asymmetrical relationship is the same in the transistor region in which the direction of the channel current is the same between the first and second MOS transistors. Semiconductor device. 6. The first and second MOS transistors are
The semiconductor device according to claim 5, further comprising a low impurity concentration layer on the channel region side of the source and drain regions. 7. A first and a second MOS transistor whose sources are commonly connected and whose drain and gate are cross-connected to each other, and detect the potential difference between the respective gates by utilizing the difference in conductance. In a semiconductor device having a sense circuit, the first and second MOS transistors each have one or a plurality of transistor regions connected in parallel, and in these first and second MOS transistors,
In the transistor region where the parasitic resistance of the source is different from that of the drain and the direction of the channel current is the same between the first and second MOS transistors, the parasitic resistances of the source and the drain are different. A semiconductor device characterized by: 8. The first and second MOS transistors are
8. The semiconductor device according to claim 7, further comprising a low impurity concentration layer on the channel region side of the source and drain regions.