JPH0793385A - Automatic place and route processing method - Google Patents

Abstract

PURPOSE:To minimize the chip size of a semiconductor integrated circuit by calculating the minimum number of necessary level generators from circuit connection information, and changing connections from the level generators to blocks and generating optimized circuit connection information. CONSTITUTION:A circuit connection information optimizing process part 103 finds the total terminal capacity of all blocks connected to level generators belonging to an object type. Then the necessary irreducible number of level generators is found from maximum connectable capacity of the existent level generators and level generators which are as many as the found number are newly provided in the circuit connection information; and the connections are changed and the original level generators are removed. A similar process is repeated for all the generators, and then the process is ended. Namely, when the semiconductor integrated circuit is arranged and wired, the circuit connection information is optimized and then the arrangement and wiring are performed by the same method as before.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for inputting circuit connection information and processing automatic placement and routing of a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art In a method of processing the layout and wiring of a semiconductor integrated circuit, when the input terminal of a certain block is a positive logic in a semiconductor integrated circuit of 5 volt operation, for example, the logic value "1" or 0 volt corresponding to 5 volt is set. Corresponding logical value "0"
In order to fix it to a fixed level, a block called the level generator whose output value after power supply is always fixed to "1" or "0" is created as a library, and the connection described in the circuit connection information is written in this library block. It is realized by connecting the input terminals of the blocks to be executed.

As the structure of the level generator in the library, its output terminal is connected to the GND bus (corresponding to "0" in the case of positive logic) or the VDD bus (corresponding to "1" in case of positive logic). In advance, by wiring the input terminal of the block to be connected and this terminal in the automatic placement and routing process, the GND bus and VD can be electrically connected.
It should be the same as connecting to the D bus.

With such a structure, in the automatic placement / routing process, the signal line connecting the output terminal of the level generator and another block is not distinguished from other normal signal lines, and the level generator is not distinguished. Also, it becomes possible to collectively perform the placement and routing processing without distinguishing it from a normal block.

[0005]

Normally, the output terminal of this level generator is always fixed at "1" or "0" from the time when a voltage is applied to the power supply of the semiconductor integrated circuit device, and the output signal is maintained even during the circuit operation. Does not change,
You can connect the input terminals of a large number of other blocks whose logic you want to fix compared to the output terminals of a normal block, and because there are no timing restrictions, redundant wiring patterns will be loosened. .

However, in the conventional placement and routing processing method, the processing is simply executed based on the input circuit connection information, and the circuit connection information is greatly increased depending on the number of level generators inserted into the circuit by the circuit designer. change.

That is, if the circuit designer connects only a few blocks to each level generator and inserts a large number of level generators into the circuit to create redundant circuit connection information, the semiconductor integrated circuit More level generators will be placed on the chip,
As a result, there is a problem that the chip size becomes large.

An object of the present invention is to calculate the required minimum number of level generators from input circuit connection information, and change the connection from each level generator to a block to generate optimized circuit connection information. An object of the present invention is to provide an automatic placement and routing processing method that minimizes the chip size of a semiconductor integrated circuit device.

[0009]

The first means of the present invention is as follows:
Of the level generators for always supplying a constant potential and fixing the potentials of the input terminals of the blocks that are the partial circuits of the LSI, first, the total capacitance of the input terminals of all blocks connected to the level generator of the target type. Obtained, the maximum connectable capacity of the level generator is compared and the minimum required number of level generators is calculated, and the number of level generators is newly provided in the circuit connection information to determine the maximum connectable capacity of the level generator. Change the connection of each block so that it does not exceed, remove the original level generator in the circuit connection information, repeat the above steps until the above process is completed for all model of the level generator, and the placement result after the optimization. Block-to-block and block-based Click - to collectively connect the wiring between the level generator.

The second means of the present invention deletes the level generator and the wiring connected to the level generator from the circuit connection information to generate the circuit connection information after the level generator deletion, and the circuit connection information after the level generator deletion. The placement result, the circuit connection information after level generator deletion and the saved deletion data are input to the level generator connection optimization restoration process, and the total input terminals of all blocks other than the level generator are input. Calculate the minimum required number of level generators by calculating the capacity, add the level generator to provide circuit connection information after level generator optimization, and change the circuit connection information after optimization and the placement result after optimization. Block-to-block and block-to-level generator To collectively connect the line.

[0011]

The minimum required number of level generator blocks is calculated from the circuit connection information of the semiconductor integrated circuit device and the library, and the minimum number of level generators is used.
Optimized circuit connection information is generated, and automatic placement and routing is performed based on the optimized circuit connection information.

Further, as another processing means of the present invention, there is also a method of processing the optimization of the number of level generators in two stages. That is, in the first stage, the level generators are deleted and blocks are arranged, then in the second stage, the circuit connection information after the level generator optimization including the minimum required number of level generators is obtained, and wiring is performed together with the placement result after the optimization. Perform processing.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The processing according to the first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a flow chart showing a processing procedure of a layout and wiring processing method using an embodiment of the present invention. In the figure, the circuit connection information 101 and the library 102 are data to be input to the processing device according to the present invention.

The circuit connection information 101 stores the logical connection information of the circuit to be realized on the semiconductor integrated circuit chip by the layout and wiring processing method of the present invention.

Further, the library 102 is data describing the shape of the block, the terminal position, the wiring rule, etc. used in the circuit connection information, and is necessary for realizing the semiconductor integrated circuit device from the circuit connection information. Stores the design rules for Further, in the present embodiment, the capacitance value connectable to the level generator and the capacitance value of the terminal of each block, which is information necessary for realizing the processing of the present invention, are also described in this library information. In the processing procedure, this information is referred to as needed.

The circuit connection information optimization processing section 103 is a section for counting the capacitance value of each block terminal connected to each level generator and the capacity connectable to the level generator to change the connection relation, The converted circuit connection information 104 is obtained.

The wiring processing section 105 is a section for performing the layout in the same manner as the conventional method according to the optimized circuit connection information 104 corrected by the circuit connection information optimization processing section 103, and the wiring processing section 107 is for optimization. Rear circuit connection information 104
Based on the layout result 106 and the layout result 106, the wiring route between each block is determined and connected by a method similar to the conventional one.

Next, the processing procedure of the circuit connection information optimization processing unit 103 of FIG. 1 which is the main part of the present invention will be described in detail with reference to FIG. This process is executed in the following steps.

Step 1: Obtain the sum of the terminal capacities of all the blocks connected to the level generator belonging to the target type.

Step 2: The required minimum number of level generators is obtained from the maximum connectable capacity of the existing level generator type.

Step 3: The number of level generators obtained in the above step 2 is newly provided in the circuit connection information, the connection is changed so as not to exceed the maximum connectable capacity of each, and the original circuit connection information is obtained. Remove the level generator inside.

Step 4: If the processing is not completed for all level generator types, the above steps 1 to 3 are repeated for the next level generator. If it is finished, the result is output and the process is finished.

As described above, in the placement and routing process of the semiconductor integrated circuit according to the present invention, the placement and routing is performed by a method similar to the conventional method after optimizing the circuit connection information.

Next, the processing according to the second embodiment of the present invention will be described with reference to the drawings.

FIG. 3 is a flow chart showing the processing procedure of the second embodiment of the present invention.

In this example, the process of optimizing the number of level generators is processed in two stages. That is, the level generator and the wiring information connected to them are deleted by the level generator connection information deletion processing unit 303,
After the level generator is deleted, the circuit connection information 304 is generated, the block placement processing is performed thereby, and the deletion data storage unit 305 that separately stores information about what kind of change is made is generated. Next, the circuit connection information after level generator deletion 304, the placement result 307, and the deletion data 305 are input to the level generator connection optimization restoration processing unit 308, and the circuit connection information after level generator optimization including the required minimum number of level generators. 31
0 and a placement result 309 after level generator optimization are generated. Based on the circuit connection information and placement result after this level generator optimization, the wiring process of the conventional method is used to convert the signal line from the level generator to a normal signal. Wiring is performed together with the line.

In the case of this embodiment, the placement processing unit 306
In, the placement process is performed using the circuit connection information without the level generator. However, considering that there is no timing constraint on the wiring connected to the level generator, the optimization process of the result can be speeded up. It will be.

The placement and wiring of the level generators are performed after the placement process 306. This takes into consideration the placement positions of the blocks connected to the level generators of the same type, and those placed close to each other are considered. This is for connecting to one level generator. By this,
The wiring length can be minimized.

[0030]

As described above, the present invention introduces a processing procedure for optimizing the number of level generators and the connection relationship, thereby minimizing the redundant circuit in the circuit connection,
This has an effect that the chip size of the semiconductor integrated circuit device can be minimized.

[Brief description of drawings]

FIG. 1 is a flowchart showing a processing procedure of a first embodiment of the present invention.

FIG. 2 is a detailed diagram of a circuit connection information optimizing process shown in FIG.

FIG. 3 is a flowchart showing a processing procedure of a second embodiment of the present invention.

FIG. 4 is a flowchart showing a conventional processing procedure.

[Explanation of symbols]

 101, 301, 401 Circuit connection information 102, 302, 402 Library 103 Circuit connection information optimization processing 104 Optimized circuit connection information 201 Start input 202 Level generator required minimum number determination processing 203 Circuit diagram optimization processing 204 All types completed 205 End output 303 Level generator connection information deletion processing 304 Level generator deleted circuit connection information 305 Deleted data storage 308 Level generator connection optimization restoration processing 309 Level generator optimized placement result 310 Level generator optimized circuit connection information 105, 306, 403 Placement process 106, 307, 404 Placement result 107, 311, 405 Wiring process 108, 312, 406 Placement and wiring result

Claims (2)

[Claims] 1. A method for inputting circuit connection information and processing an automatic placement and routing of a semiconductor integrated circuit device, for always supplying a constant potential and fixing a potential of an input terminal of a block which is a partial circuit of an LSI. Among the above level generators, first find the total capacity of the input terminals of all blocks connected to the level generator of the target model, and consider the maximum connectable capacity of the level generators to find the minimum required number of level generators. The number of level generators is newly provided in the circuit connection information, the connection of each block is changed so as not to exceed the maximum connectable capacity of the level generator, and the original level in the circuit connection information is changed. Remove the generator and follow the steps above until the process is complete for all level generator models. Ri returns, block based on the placement result and the circuit connection information after optimization after the optimized -
A method for automatically arranging and wiring a semiconductor integrated circuit device, wherein wiring between blocks and between a block and a level generator are collectively connected. 2. A method for inputting circuit connection information and processing an automatic placement and routing of a semiconductor integrated circuit device, wherein a level generator and a line connected to the level generator are deleted from the circuit connection information and a level generator is deleted. Generates post-circuit connection information, performs placement processing based on the post-level generator deletion circuit connection information, and restores the wiring result, level generator post-deletion circuit connection information, and saved deletion data for level generator connection optimization. Input to the process, calculate the total capacity of the input terminals of all blocks other than the level generator, calculate the required minimum number of level generators, add the level generator to provide circuit connection information after level generator optimization,
An automatic semiconductor integrated circuit device characterized in that wiring between blocks and between blocks and level generators is collectively connected in accordance with the rearranged optimized circuit connection information and the optimized placement result. Place and route processing method.