JPH0795065A - Intermittent frequency synthesizer device - Google Patents

Abstract

(57) [Summary] [Purpose] To provide an intermittent operation synthesizer that can be started up at high speed even when the phase comparator is of a type that synchronizes with a certain phase difference Δφ. [Configuration] A reference frequency divider 2 that consists of a counter that divides the reference frequency signal and outputs it as a reference signal, and a counter that counts and divides the output from the voltage-controlled oscillator (VCO) 5. And a comparison frequency divider 6 that obtains a comparison signal and a synthesizer of the type in which the reference signal and the comparison signal are synchronized with a certain phase difference Δφ.
Corresponding to the phase comparator 3 which generates the control voltage of VCO,
After holding the VCO control voltage during power saving mode transition,
The loop is released, the count numbers of the reference frequency divider and comparison frequency divider at that time are held, these counts are restarted from the count number held when the power saving mode was released, and then the VCO control held The control unit 8 controls the application of a voltage to form a closed loop.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL frequency synthesizer device which operates intermittently to reduce current consumption.

[0002]

2. Description of the Related Art A frequency synthesizer is a signal generator that can easily obtain a stable and accurate frequency signal by digitally supplying an external control signal, and is widely used in the field of mobile communication and the like. .

Here, a general synthesizer will be described. FIG. 8 shows the basic configuration of a conventional PLL frequency synthesizer. The circuit shown in FIG. 8 is a highly stable reference oscillator 101 such as a temperature compensated crystal oscillator (TCXO).
, The oscillation output signal generated by the reference oscillator 101 is divided into 1 / R by passing through the reference divider 103 which is a 1 / R divider. Then, the signal of the frequency divided into 1 / R is obtained as the reference signal Fr. The reference signal Fr is input to the reference signal input terminal of the phase comparator 105.

On the other hand, the output of the voltage controlled oscillator (VCO) 109 that generates a signal at a frequency corresponding to the input voltage is 1
The output signal from the voltage controlled oscillator (VCO) 109, which is given to the comparison frequency divider 111 which is a / N frequency divider and is divided into 1 / N by the comparison frequency divider 111, is compared with the comparison signal Fv.
Get as. This comparison signal Fv is the phase comparator 105.
Is input to the comparison signal input terminal which is the other input of the.

The phase comparator 105 is a circuit for outputting a voltage ε according to the phase difference between two input signals. The phase of the two input signals Fr and Fv input to the phase comparator 105 is the phase here. The phase comparator 105 outputs a voltage ε corresponding to the phase difference between these two input signals Fr and Fv, and the loop filter (low-pass filter) 1
It is given to 07.

The loop filter 107 smoothes the output voltage ε of the phase comparator 105 and outputs it.
By smoothing the output voltage ε of the phase comparator 105 and outputting it to the voltage controlled oscillator (VCO) 109, a control voltage V to be given to the voltage controlled oscillator (VCO) 109 is obtained.
c is generated, and the oscillation frequency of the voltage controlled oscillator (VCO) 109 is changed.

The oscillation signal of the voltage controlled oscillator (VCO) 109 is fed back to the phase comparator 105 via the comparison frequency divider 111. In this way, the phase locked loop (P
By configuring LL), an output signal having a stable frequency can be obtained from the VCO.

The operation of this PLL is such that when the phase difference between the two signals Fr and Fv input to the phase comparator 105 becomes zero, the PLL enters the synchronization state, and V in that synchronization state is reached.
The oscillation signal of the frequency Fout of CO becomes the output of the synthesizer.

By the way, in the mobile communication system, in addition to the call state, there is a standby state. In this standby state, the output of the synthesizer is unnecessary. Therefore, it is convenient that the synthesizer used for the mobile communication terminal or the like can be operated by an intermittent operation method that suspends the operation in a standby state or the like. Therefore, the intermittent operation will be described next.

A synthesizer used in a mobile communication terminal or the like is provided with a normal operation mode and a power saving mode in order to reduce power consumption during standby and save energy. Then, the operation is performed while selecting the normal operation mode and the power saving mode. This is the intermittent operation.

Then, in the power saving mode, the power of the entire synthesizer is turned off. When the power saving mode is released, the PLL starts operating (this is called a pull-in mode), and after a certain period of time, the PLL enters a synchronous state and generates a signal with a stable frequency (this is called an operating mode). FIG. 9 shows changes in the oscillation frequency of the synthesizer with time.

When the power saving mode is released as shown in the figure, the oscillation frequency of the synthesizer gradually approaches the target frequency F1 while moving back and forth around the target frequency F1, and finally synchronizes with the target frequency F1. To do.

In this case, since the operation is not synchronized at all at first and the loop is brought into the synchronized state from the state where the synchronization is not completely achieved, it takes a long time to reach the synchronized state. Become.

As described above, in the conventional synthesizer, since it takes a long time to rise from the power saving mode (that is, the pull-in mode time), the TDMA is performed.
Cannot be used to save power by intermittently operating the synthesizer during communication, etc., and the power saving mode described above is limited to use when the idle time is relatively long, such as during standby. It was being done.

By the way, a method for solving the problem that the pull-in mode takes a long time has already been proposed, for example, in Japanese Patent Laid-Open No. 61-269421.

In the method disclosed in this publication, the following control is performed. That is, the control voltage of the VCO is held by means such as opening the loop before entering the power saving mode. At the same time when the power saving mode is released, the initial phase (clock rising edge) of the reference signal and the comparison signal input to the phase comparator is set to zero. This can be realized by means of, for example, resetting the comparison frequency divider in accordance with the phase of the reference signal.

The method disclosed in the above publication intends to shorten the pull-in mode time by such an operation. Further, in the power saving mode, it is possible to turn off the power for all but the control block.

By the way, some synthesizers cannot use this method. It is a synthesizer that synchronizes with phase offset. That is, a general PLL is controlled so that the phase difference between the two signals input to the phase comparator is zero, as described above. However, such a phase comparison method has a phase difference near zero. Due to the dead zone, there is a drawback in that there is much jitter and noise during synchronization.

On the other hand, as a method capable of suppressing such a phenomenon, two signals input to the phase comparator are controlled so as to be offset by a certain phase difference Δφ. There is a PLL. This is a synthesizer that offsets and synchronizes. Such P
In the case of LL, the intermittent operation method cannot be expected to be effective.

That is, the pull-in time can be shortened by using the above control method only when the loop operates so that the two input signals of the phase comparator are in phase with each other. This is because when the two input signals are a loop that synchronizes with a certain phase offset, the loop has a phase difference of "0" between the two input signals even if the above control method is used. This is because it takes time from the state to synchronize with the phase “Δφ” corresponding to the offset, so that the pull-in time cannot be shortened.

[0021]

As described above, in the conventional intermittent operating frequency synthesizer, the phase comparator has two components.
The method of synchronizing in a state where the phase difference between two input signals is offset by Δφ has a drawback that it cannot be started up at high speed.

However, the type in which the phase comparator synchronizes in the state where the phase difference between the two input signals is offset by Δφ is very convenient for mobile communication because it has very little noise. Therefore, in such a system, there is a strong demand for the development of an intermittent operation synthesizer capable of starting up at high speed.

The present invention has been made in view of the above drawbacks, and an object of the present invention is to start up at high speed even when the phase comparator is of a type that synchronizes with a certain phase difference Δφ. An object of the present invention is to provide an intermittent operation frequency synthesizer device that enables the operation.

[0024]

In order to solve the above-mentioned problems, the present invention has the following constitution. That is, the reference oscillating means for generating a reference signal of a predetermined frequency and the reference signal output by this reference oscillating means are counted and divided by a required frequency division number, and the counting operation is stopped / restarted by the function and command to be output A first frequency dividing means (reference frequency divider) which is controllable and has a function of holding the count number when the count operation is stopped and a function of restarting the count from the held count number when restarting the count; , A voltage controlled oscillator (voltage controlled oscillator) that oscillates and outputs at a frequency corresponding to the level of the input control signal, and an output signal of this voltage controlled oscillator is divided by a required frequency division number and output. , A function that can stop / restart the count operation by a command and that holds the count number when the count operation is stopped Programmable second frequency dividing means (comparison frequency divider) having a function of restarting counting and a control signal corresponding to the phase difference between the first and second frequency dividing means are received. The phase comparison means (phase comparator) that is generated, a loop filter that filters the output of this phase comparison means and applies it as a control signal to the voltage controlled oscillation means, and the connection between the phase comparison means and the loop filter are opened.・ Short-circuiting loop open / close switch, oscillator power supply open / close switch for opening / closing the power supply of the voltage control oscillator, and loop open / close switch and oscillator power supply open / close switch for open control in power saving operation mode and short-circuit control for normal operation mode At the same time, a command is issued to the first and second frequency dividing means to stop the count in the power saving operation mode and restart the count in the normal operation mode. And configure and a obtaining control means.

[0025]

The frequency synthesizer having such a configuration has a normal operation mode and a power saving operation mode. In the normal operation mode, the output corresponding to the difference between the outputs of the first and second frequency dividing means is compared with the phase comparing means. Obtained by, filtered by a filter, given as a control voltage to the voltage controlled oscillator, oscillate the voltage controlled oscillator at an oscillation frequency corresponding to the control voltage, to obtain a required oscillation output to function as a frequency synthesizer, At the start of the power saving operation mode, the switches are opened, the input of the filter is cut off, the power supply of the voltage controlled oscillator is cut off, and the counting operation of the first and second frequency dividing means is stopped to reduce power consumption. The voltage controlled oscillator, which occupies most of the power consumption, is stopped to save power.

When shifting from the power saving operation mode to the normal operation mode, the above switches are turned on to start the operation of the voltage controlled oscillator, and the counting of each frequency dividing means is restarted. It controls and restarts the counting operation of each frequency dividing means. Each frequency dividing means is a frequency divider using a counter, and has a function of holding the count number when the count is stopped and a function of starting the count from the held count number when the counting is restarted. The phase difference of these frequency dividing means maintains the state at the time of the count stop control. The voltage controlled oscillator has a high input impedance, and the loop filter holds the output level of the phase comparator at the time of count stop control by the capacitor forming the filter. As a control voltage, the level at the time of the count stop control can be immediately given to the oscillator and the operation can be started from that level. Therefore, when the phase comparator is of a type that synchronizes with a certain phase difference Δφ, it becomes possible to shift from the power saving mode to the synchronization state at high speed.

[0027]

EXAMPLE A first example according to the present invention will be described below.
A description will be given with reference to the drawings. (First Embodiment) [Structure] FIG. 1 is a block diagram showing the structure of a frequency synthesizer according to the present invention.

The configuration of the first embodiment will be described. As shown in FIG. 1, this synthesizer comprises a reference oscillator 1, a reference frequency divider 2, a phase comparator 3, a loop filter 4, and a voltage controlled oscillator (VCO) 5. , Comparison frequency divider 6, loop switch 7,
It is composed of a controller 8 and a switch 9.

Of these, the reference oscillator 1 is a circuit that oscillates and outputs a reference high-frequency signal using a highly stable oscillator such as a temperature-compensated crystal oscillator (TCXO). The reference frequency divider 2 is a frequency divider that divides the oscillation output signal generated by the reference oscillator 1 by 1 / R and outputs it. The frequency-divided output of the reference frequency divider 2 is used as the reference signal Fr. The phase comparator 3 is a circuit which receives the reference signal Fr and a comparison signal Fv described later and outputs a voltage ε according to the phase difference between the two input signals. The phase comparator 3 compares the phases of the two input signals Fr and Fv that have been input, outputs a voltage ε corresponding to the phase difference between the two input signals Fr and Fv, and outputs the voltage ε via the loop switch 7. Is applied to the loop filter (low-pass filter) 4.

The voltage controlled oscillator (VCO) 5 generates a signal at a frequency corresponding to the input voltage, and the comparison frequency divider 6 divides the output of the voltage controlled oscillator (VCO) 5 by 1 / N. It is a vessel. The frequency division output of the comparison frequency divider 6 is used as the comparison signal Fv.

The switch 9 is a voltage controlled oscillator (VCO) 5
Is a switch for controlling ON / OFF of the driving power source of, and is controlled by the control unit 8. The loop switch 7 is a switch for turning on / off the input of the loop filter 4, and is controlled by the control unit 8.

The control unit 8 controls the loop switch 7 and the switch 9 to be turned off in the standby state and to turn them on in the communication state. Further, the control unit 8 inputs a count stop command (disenable signal) to the reference frequency divider 2 and the phase comparator 3 in the standby state, and issues a count execution command (enable signal) to these in the communication state.
Control to give.

The loop filter 4 smoothes the output voltage ε of the phase comparator 3 to generate a voltage controlled oscillator (VC).
O) to generate a control voltage Vc for giving to
The oscillation frequency of the voltage controlled oscillator (VCO) 5 can be changed by applying the control voltage Vc.

A concrete circuit example of the loop filter 4 is shown in FIG. 2, which is generally called a perfect integral second-order filter. This filter includes resistors R1 and R
2 and the capacitor C determine the loop constant (natural angular frequency and damping coefficient).

The reference frequency divider 2 divides the signal input from the reference oscillator 1 into 1 / R. This operation is performed by changing the rising edge (or the falling edge) of the signal of the reference oscillator 1. A digital operation is performed in which counting is performed and one clock is output from the output terminal each time the number of counts reaches R. The reference frequency divider 2 has a function of stopping the count and holding the count number at that time at the same time according to a command from the control unit 8.
This function is similar to the enable terminal of a general-purpose logic IC element, for example, an IC element of model number 74F1611 / 163.

The operation of the comparison frequency divider 6 is similar, that is, it divides the signal input from the voltage controlled oscillator (VCO) 5 to 1 / N, and its operation is exactly the same as that of the reference frequency divider 2. It is a thing.

The phase comparator 3 receives the signal Fr input from the reference frequency divider 2 and the signal Fv input from the comparison frequency divider 6.
Is compared and the voltage Vp proportional to the phase difference is output. Here, the phase comparison characteristic of the phase comparator 3 becomes the characteristic shown in FIG.

The phase comparison characteristic of the phase comparator 3 will be described with reference to FIG. 3. As shown in the figure, the phase comparator 3 has a certain voltage V when the phase difference between the two input signals Fr and Fv is zero.
Output d. Further, it has a characteristic that the output voltage becomes zero when the phase difference between the two input signals Fr and Fv is 2Δφ. In the synchronized state, the phase difference between the two input signals is Δφ, and at that time, the output voltage Vp of the phase comparator 3 becomes Vd / 2. The ratio of the output voltage to the unit input phase difference at this time is called the phase comparison sensitivity. The unit is usually V / rad.

[Operation] Next, the operation of this embodiment will be described with reference to FIG. [Normal Operation Mode] First, the operation in the synchronous state will be described.

When the synthesizer is synchronized at a certain frequency, the two signals of the reference signal Fr and the comparison signal Fv input to the phase comparator 3 have the same frequency and have a certain phase difference Δφ. At this time, the voltage Vp corresponding to the phase difference Δφ is output to the output terminal of the phase comparator 3. This voltage is a predetermined voltage as described above. For example, when the output voltage when the phase difference is zero is Vd,
It is d / 2. This voltage Vp is integrated by the loop filter 4 to generate the control voltage Vc of the voltage controlled oscillator (VCO) 5, and in the synchronized state the voltage controlled oscillator (VCO) 5
The oscillation frequency of is always stable.

[Transition from Synchronized State to BS Mode] Next, the transition from the synchronized state to the power saving mode (BS mode) will be described. When a command to shift to the power saving mode is externally given to the control unit 8, the control unit 8 first performs the OFF control of the loop switch 7 and opens the loop switch 7. By opening the loop switch 7, the connection between the loop filter 4 and the phase comparator 3 is cut off. Here, since the input impedance of the control voltage input terminal of the voltage controlled oscillator (VCO) 5 connected to the output side of the loop filter 4 is very high, the output side of the loop filter 4 can be regarded as an open state.

Therefore, the control voltage Vc of the voltage controlled oscillator (VCO) 5 is held by the capacitor C of the loop filter 4. Then, the control unit 8 sends an instruction to the reference frequency divider 2 and the comparison frequency divider 6 to stop counting. Specifically, this command is given by sending a count disable signal from the control unit 8 to the counters that control the frequency dividing operation of each of the frequency dividers 2 and 6. By this operation, the reference frequency divider 2 and the comparison frequency divider 6 stop their operations while holding the count numbers at that time. further,
The power of the voltage controlled oscillator (VCO) 5 is cut off by controlling the opening of the switch 9 according to a command from the control unit 8. As a result, the reference frequency divider 2 and the comparison frequency divider 6 are in an operation stop state while holding the count number at that time, and the voltage control oscillator (V
The CO) 5 is turned off and this is also deactivated, and these deactivations reduce power consumption significantly. Therefore, in the power saving mode (BS mode), the power consumption can be significantly suppressed and the power saving effect can be obtained.

[Transition from BS Mode to Synchronous State] Next, the operation for canceling the power saving mode (BS mode) will be described. When a command for canceling the power saving mode is given to the control unit 8, the control unit 8 first controls the switch 9 to turn on and short-circuits the switch 9. As a result, the power source of the voltage controlled oscillator (VCO) 5 is first turned on.

Next, the control section 8 sends a command (count enable signal) to restart counting to the reference frequency divider 2 and the comparison frequency divider 6 which have stopped counting.
As a result, the reference frequency divider 2 and the comparison frequency divider 6 restart counting from the count numbers respectively held therein. Finally, the loop switch 7 is controlled to turn on, which shorts the loop switch 7 and recreates a closed loop.

The reference frequency divider 2 and the comparison frequency divider 6 are respectively B
Since the counting is restarted from the count number held at the time of entering the S mode, the phase difference between the output signals Fr and Fv is the same as that before entering the BS mode.

As a result, in the above operation, both the reference frequency divider 2 and the comparison frequency divider 6 hold the count number immediately before the counting is stopped until it is restarted.
The state of the loop at the moment when the power saving mode is released is recreated to be exactly the same as the state immediately before the power saving mode was entered. As a result, even when the power saving mode is changed to the operation mode, it is possible to quickly perform synchronization.

[Summary] The operation of the synthesizer described above will be described once again in a summary sense. First, the operation when changing from the normal synchronization state to the power saving mode is as follows.

1) The loop switch 7 is opened, and the condenser C in the loop filter 4 holds the VCO control voltage. 2) A count temporary stop command is sent to the reference frequency divider 2 and the comparison frequency divider 6 to stop the count and at the same time hold the count number at that time.

3) Turn off the power supply of the voltage controlled oscillator (VCO) 5. Next, the operation from the power saving mode to the synchronous mode via the pull-in mode is as follows.

11) Power on the voltage controlled oscillator (VCO). 12) By short-circuiting the loop switch 7, the control voltage of the VCO held in the capacitance C of the loop filter is applied again.

13) At the same time, the counting of the reference frequency divider 2 and the comparison frequency divider 6 which have stopped counting is restarted. [Power Saving Capability of Frequency Dividers 2 and 6 in BS Mode] Further, the synthesizer of the present embodiment described above has a power saving mode (B
Although only the VCO is powered off in the S mode), the effect is great in view of the fact that most of the power consumption of the synthesizer is occupied by the VCO. The comparison frequency divider 6 is usually a C-MO.
Since it is composed of an integrated circuit element of a logic circuit using the S process, the power supply of the voltage controlled oscillator (VCO), which is its clock input, is cut off and the input disappears.
The power consumption can be almost zero in the power saving mode.

As a supplementary explanation, leakage of the holding voltage Vcon of the capacitor C in the loop filter 4 will be described next. In the above description, it is assumed that the control voltage of the voltage controlled oscillator (VCO) 5 is accurately held in the capacitor C, which is the capacitive element of the loop filter 4, but actually the control of the voltage controlled oscillator (VCO) 5 is performed. It fluctuates due to a very small amount of current flowing out to the terminal.
However, even if the voltage held in the capacitor C fluctuates, compared with the time required until the conventional voltage starts from 0V and reaches the synchronous state,
The time required to start from the voltage value of the capacitor C that has undergone voltage fluctuation and reach the synchronized state is much shorter, and therefore the effectiveness of the present invention is not impaired in terms of the time saving effect.

Next, consider the power saving effect of the reference frequency divider 2. In the case of the first embodiment of the present invention described above, the reference frequency divider 2
The counting is stopped by sending a count disenable signal from the control unit 8 to the frequency divider 2, but instead, as shown in FIG. 4, immediately before the reference frequency divider 2. It can also be realized by providing the switch 21 on the. In this case, the signal from the reference oscillator 1 is directly input to the reference frequency divider 2 by the signal from the control unit 8, and the input to the reference frequency divider 2 is cut off. As a result, the counting is stopped. .

By thus configuring the reference frequency divider 2 and cutting off the clock input (reference signal input in this case) in the power saving mode, the reference frequency divider 2 is a C-MOS type integrated circuit device. If so, the power consumption of the reference frequency divider can be set to almost 0, similarly to the comparison frequency divider 6, and the power saving effect is great. The switch 21 can be easily realized by using a general-purpose logic element such as an AND gate.

(Second Embodiment) The above-mentioned comparison frequency divider 6 can adopt a pulse swallow method. In this case, the comparison frequency divider 6 comprises a programmable counter 61, a swallow counter 62, and a two-modulus prescaler 63, as shown in FIG. A description will be added to the case of adopting such a pulse swallow method.

Here, the programmable counter 61, the swallow counter 62, and the prescaler 63 together have the same function as that of the comparison frequency divider 6 of the synthesizer of the first embodiment of the present invention shown in FIG. , Is generally called the pulse swallow method.

The pulse swallow method is a very general method for a synthesizer that oscillates a frequency above the UHF band, and therefore a detailed description thereof will be omitted here. Control unit 8
When the power supply of the voltage controlled oscillator (VCO) 5 is cut off by the control signal from, as a result, the input of the prescaler 63 is lost, so the counts of the programmable counter 61, the swallow counter 62, and the prescaler 63 are stopped, and the count number Since the operation is shifted to the power saving mode by holding, the operation exactly the same as that of the first embodiment can be realized.

Even when the comparison frequency divider 6 is constructed by the pulse swallow method as described above, since the input of the prescaler 63 (the signal from the VCO 5) is lost in the power saving mode (the programmable counter 61 and the swallow counter are C- The power consumption of the programmable counter 61 and the swallow counter 62 can be made almost zero if they are made of MOS type semiconductor integrated circuit elements.

If the prescaler 63 is required to operate at a high speed, it is generally not made as a semiconductor integrated circuit of a C-MOS process, but an integrated circuit is constructed by a bipolar transistor process. In the case of a bipolar transistor, power consumption is relatively large. When the prescaler 63 including such a relatively high power consumption element is used, the power consumption of the prescaler 63 is not reduced even if the VCO is powered off and the input to the prescaler 63 is lost.

A method for solving this point will be described below as a third embodiment. (Third Embodiment) In the third embodiment, when the power saving mode is entered, not only the voltage controlled oscillator (VCO) 5 but also the power of the prescaler 63, which is a relatively high power consumption element, is cut off. It is configured to do. The overall structure at this time is shown in FIG. In this case, as shown in FIG. 6, a switch 10 for cutting off the power source of the prescaler 63 is newly provided. Then, the control unit 8 is configured to perform on / off control of the switch 10. When the switch 10 is turned on, it is in the operation mode, and when it is turned off, it is in the power saving mode.

The synthesizer is constructed as shown in FIG. 6, and when shifting to the power saving mode, the voltage controlled oscillator (VCO) is used.
By turning off the power of 5 and the prescaler 63 at the same time,
Since the power consumption is reduced and the inputs to the programmable counter 61 and the swallow counter 62 are stopped, the frequency dividers 61 and 62 hold the count numbers at that time.

In this case, the prescaler 63 no longer holds the previous count number at the time of canceling the power saving mode (for temporarily turning off the power), and that amount becomes an error. However, this error does not impair the effectiveness of the present invention. This point will be described below with reference to a specific example.

[Specific Embodiment] The third embodiment described above will be described with specific practical numbers.
For example, the oscillation frequency of the reference oscillator 1 is 19.2 MHz. Then, the reference signal Fr input to the phase comparator 6
Is 50 kHz, the frequency division number R of the comparison frequency divider 6 is 19.2 MHz ÷ 50 kHz = 384. When the output center frequency of the voltage controlled oscillator (VCO) 5 is 1897.5 MHz, the frequency division number N of the comparison frequency divider 6 is 1897.5 MHz ÷ 50 kHz = 37950. When the configuration of the comparison frequency divider 6 is the pulse swallow method, if the frequency division number of the programmable counter 61 is M, the frequency division number of the swallow counter 62 is A, and the frequency division number of the 2 modulus prescaler 63 is P / P + 1, There is a relation of N = M · P + A between them, and assuming that the frequency division number of the prescaler 63 is P = 128 for P, that is, 128/129 frequency division, M is “29”.
6 "and A become" 62 ".

Further, the phase comparator 6 has two input signals Fr.
When the phase difference Δφ between Fv and Fv is 0, a predetermined voltage Vd is output, and when the phase difference between the two input signals Fr and Fv occurs, the output voltage Vp (Vp <Vp corresponding to the phase difference Δφ is generated.
Change to d). The change characteristic is linear.

Now, the phase comparison sensitivity of the phase comparator 6 is 5 V /
rad, assuming that the output voltage Vd of the phase comparator 6 when the phase difference between the two input signals Fr and Fv is 0 is 5V, the output voltage Vp of the phase comparator 3 is Vp / 2.
Phase difference Δ between the two input signals Fr and Fv when 5 V is indicated
φ is 2.5 / 5 = 0.5 rad = 28.6 °.

This is the phase difference Δφ between the reference signal Fr and the comparison signal in the synchronous state when the phase comparator 6 is used. Now, the phase comparison is performed at 50 kHz, so if the phase difference Δφ at this time is converted to time τ, it is 50 kHz.
Since the period of the signal having the frequency of is the inverse of 20 μsec, τ = 20 μsec × 28.6 ° ÷ 360 ° = 1.6 μsec. That is, in the synchronized state, the input of the phase comparator 6 has a phase difference of τ = 1.6 μsec, and the comparison signal Fv is input 1.6 μsec after the input of the reference signal Fr.

Next, the case of shifting to the power saving mode will be described. The instruction to shift to the power saving mode and the instruction to cancel the power saving mode are randomly input regardless of the operation of the loop. Therefore, the phase of the reference oscillator 1 at the moment when the reference frequency divider 2 stops counting and the phase of the reference oscillator 1 at the moment when the reference frequency divider 2 restarts counting have a maximum error of one cycle. This is the reciprocal of 19.2MHz in time,
That is, it is 52 nsec.

On the side of the comparison frequency divider 6, the prescaler 6
When the power supply of No. 3 is cut off, the error due to the same reason as above is 67 nsec which is the reciprocal of 1897.5 MHz ÷ 128 = 14.8 MHz. Therefore, the sum of the error on the reference frequency divider 2 side and the error on the comparison frequency divider 6 side is 52 + 67 = 1.
It will be 19 nsec.

Therefore, after the power saving mode is released, the phase error is corrected, and the synchronization state is reached in a time only for pulling in, so that it is possible to start up at a very high speed. The present invention is not limited to the embodiments described above and shown in the drawings, but may be modified and implemented as appropriate without departing from the scope of the invention.

For example, in the present invention, a voltage controlled oscillator (VC
O) 5 for holding the control voltage of the loop filter 4
Although the capacity holding capacity of the capacitor C of is used as it is, the control voltage holding circuit 11 that holds the output voltage of the loop filter 4 during the normal operation is used as shown in FIG. The control voltage holding circuit 11 is configured to hold the voltage, and when the power saving mode is released.
It is also possible to apply the voltage held by the above to the voltage controlled oscillator (VCO) 5 so as to quickly bring it to the synchronized state.
The control voltage holding circuit 11 is, for example, Japanese Patent Laid-Open No. 58-664.
No. 22 (Phase-locked loop circuit), JP-A-61-810
The technology disclosed in Japanese Patent No. 27 (PLL circuit) can be used.

As described above in detail, the synthesizer of the present invention counts the reference oscillator for generating the reference signal of the predetermined frequency and the required frequency division number (divisor R).
Frequency division) and output, a function that can stop and control the count operation arbitrarily, a function that holds the count number at that time, and a function that restarts counting from the held count number when restarting the count. The first frequency dividing means (reference frequency dividing means), the voltage controlled oscillator that oscillates and outputs at the frequency corresponding to the level of the input control signal, and the output signal of the voltage controlled oscillator is divided by the required frequency division number ( It has a function of dividing and outputting by dividing by a divisor N), and a function of arbitrarily stopping the count, a function of holding the count number at the time of stopping, and a function of holding at the time of stopping when restarting the counting. Programmable second frequency dividing means (comparative frequency dividing means) having a function of restarting from the count number, and receiving the outputs of the first frequency dividing means and the second frequency dividing means to obtain a phase difference between them. Corresponding control Signal generating means, a loop filter for filtering the output of the phase comparing means and giving it as a control signal to the voltage controlled oscillator, and a loop for opening / shorting the connection between the phase comparing means and the loop filter. The open / close switch, the oscillator power supply open / close switch for opening / closing the power supply of the voltage controlled oscillator, the loop open / close switch and the oscillator power supply open / close switch are opened in the power saving operation mode, and short-circuit control is performed in the normal operation mode. The frequency dividing means is provided with a control means for stopping and controlling the count in the power saving operation mode and for restarting the counting in the normal operation mode.

The frequency synthesizer having such a configuration is
It has a normal operation mode and a power saving operation mode. In the normal operation mode, an output corresponding to the difference between the outputs of the first and second frequency dividing means is obtained by the phase comparing means, and this is filtered by a filter, It is given as a control voltage to the voltage-controlled oscillator, and this voltage-controlled oscillator is oscillated at an oscillation frequency corresponding to the control voltage to obtain the required oscillation output and function as a frequency synthesizer.At the start of the power saving operation mode, each switch is opened. Then, the input of the filter is cut off, the power supply of the voltage controlled oscillator is cut off, and the first and second
In order to save power, the counting operation of the frequency dividing means is stopped and the voltage controlled oscillator, which accounts for a large amount of power consumption, is stopped. Then, when shifting from the power saving operation mode to the normal operation mode, the switches are turned on to start the operation of the voltage controlled oscillator, and the counting operation of each frequency dividing means is controlled to restart. The counting operation of each frequency dividing means is restarted. Each frequency dividing means is a frequency divider using a counter, and has a function of holding the count number when the count is stopped and a function of starting the count from the held count number when the counting is restarted. The phase difference of these frequency dividing means maintains the state at the time of the count stop control. The voltage controlled oscillator has a high input impedance, and the loop filter holds the output level of the phase comparator at the time of count stop control by the capacitor forming the filter. As a control voltage, the level at the time of the count stop control can be immediately given to the oscillator and the operation can be started from that level. Therefore, when the phase comparator is of a type that synchronizes with a certain phase difference Δφ, it becomes possible to shift from the power saving mode to the synchronization state at high speed.

[0073]

As described above in detail, according to the present invention, in the synthesizer of the type in which the reference signal and the comparison signal are synchronized with a certain phase difference Δφ, the loop is opened after holding the VCO control voltage at the time of shifting to the power saving mode, The count numbers of the reference frequency divider and the comparison frequency divider at that time are held, the counts of the reference frequency divider and the comparison frequency divider are restarted from the count numbers that were held when the power saving mode was released, and then they are held. After applying the VCO control voltage, the closed loop is formed. By the above operation, the phase difference Δφ at the time of synchronization is reformed when the power saving mode is released, so that there is an effect that it is possible to reach the synchronization at a high speed.

By using this synthesizer, the synthesizer can be operated intermittently and the power supply to the VCO or the like, which consumes a large amount of power, can be stopped, so that the power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram for explaining an embodiment of the present invention,
The block diagram which shows the structure of the frequency synthesizer which concerns on 1st Example of this invention.

FIG. 2 is a diagram for explaining an embodiment of the present invention,
The figure which shows the specific circuit example of the loop filter 4 used for the frequency synthesizer which concerns on 1st Example of this invention.

FIG. 3 is a diagram for explaining an embodiment of the present invention,
The figure which shows the phase comparison characteristic of the phase comparator 3 used for the frequency synthesizer which concerns on 1st Example of this invention.

FIG. 4 is a diagram for explaining an embodiment of the present invention,
FIG. 4 is a block diagram showing an embodiment in which a switch 21 is provided in front of the reference frequency divider 2 in the frequency synthesizer of the present invention so as to obtain a power saving effect.

FIG. 5 is a diagram for explaining an embodiment of the present invention,
The block diagram which shows the structure of the comparison frequency divider 6 used for the frequency synthesizer which concerns on the 2nd Example of this invention.

FIG. 6 is a diagram for explaining an embodiment of the present invention,
The block diagram which shows the structural example which aims at energy saving of the comparison frequency divider 6 which employ | adopted the pulse swallow system used for the frequency synthesizer which concerns on the 3rd Example of this invention.

FIG. 7 is a diagram for explaining an embodiment of the present invention,
FIG. 9 is a diagram showing another embodiment of the present invention, and is a block diagram showing an example in which a control voltage holding circuit 11 holding the output voltage of the loop filter 4 during normal operation is used to hold the control voltage.

FIG. 8 is a diagram for explaining a conventional example, which is a conventional P
The block diagram which shows the basic composition of a LL frequency synthesizer.

FIG. 9 is a diagram for explaining a conventional example, showing a conventional P
The figure which shows the mode of change of the oscillation frequency at the time of starting in an LL frequency synthesizer with respect to time.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Reference oscillator 2 ... Reference frequency divider 3 ... Phase comparator 4 ... Loop filter 5 ... Voltage controlled oscillator (VCO) 6 ... Comparison frequency divider 7 ... Loop switch 8 ... Control unit 9, 10, 21 ... Switch 11 ... Control voltage holding circuit 61 ... Programmable counter 62 ... Swallow counter 63 ... Prescaler C ... Capacitors R1, R2 ... Resistors

Claims (1)

[Claims] 1. A reference oscillating means for generating a reference signal of a predetermined frequency, and a reference signal output from this reference oscillating means is counted and divided by a required frequency division number, and a counting operation is performed by a function and a command to be outputted. A first frequency dividing means capable of stop / restart control and having a function of holding a count number at the time of count operation stop control and a function of restarting the count from the held count number when restarting the count; Voltage control oscillating means for oscillating and outputting at a frequency corresponding to the control signal, and outputting the output signal of the voltage controlling oscillating means by dividing the output signal by a required frequency division number and stopping / counting operation by a command.
Programmable second frequency dividing means having restartable controllable function of holding the count number at the time of count operation stop control and function of restarting the count from the held count number when restarting the count; Phase comparing means for receiving the outputs of the first and second frequency dividing means and generating a control signal corresponding to the phase difference between them, and the output of this phase comparing means is filtered and given to the voltage controlled oscillator means as a control signal. A loop filter, a loop open / close switch for opening / shorting the connection between the phase comparison means and the loop filter, an oscillator power open / close switch for opening / closing the power supply of the voltage controlled oscillation means, these loop open / close switch and oscillator power open / close The switch is open-controlled in the power-saving operation mode, short-circuited in the normal operation mode, and the first and second frequency divisions are performed. And count stop control in power saving operation mode with respect to stage, the intermittent operating frequency synthesizer apparatus characterized by being configured by comprising a control means for providing a command to control resume the normal operation mode.