JPH0797621B2 - Dynamic random access memory - Google Patents

Description

DETAILED DESCRIPTION [Table of Contents] Outline Industrial field of use Conventional technology Problems to be solved by the invention Means for solving problems Problems Working Example First Embodiment Schematic diagram (first embodiment) Fig.) Schematic diagram of the second embodiment (Fig. 2) Process diagram of manufacturing method (Fig. 3) Schematic diagram of conventional structure example (Fig. 4) Effect of the invention [Overview] Dynamic random access having a trench capacitor In a memory (hereinafter abbreviated as DRAM) cell, a first conductive layer deposited on the inner wall surface of a trench formed in a semiconductor substrate is used as a counter electrode, and a second conductive layer is embedded in the trench via a dielectric layer. In a structure having a storage capacitor having a conductive layer as a storage electrode, the upper end of the counter electrode is located lower than the bottom surface of the source / drain region of the cell transistor,
An insulating layer is interposed between the separated portions to prevent the breakdown voltage of the source / drain junction of the cell transistor from decreasing.

[Industrial application field]

 The present invention relates to a highly integrated and high performance DRAM cell structure.

The trench capacitor has a MOS structure in which the capacitor part is three-dimensionally (groove-shaped) and can take a larger effective capacitor area than the planar type cell that has been generally used up to 256 Kbit DRAM. It is characterized by its small size and large storage capacity.

However, the trench capacitor has the problems described below, and there is a demand for a structure that is smaller, has a large storage capacitance, and does not cause punch-through between adjacent capacitors even with high integration.

[Conventional technology]

FIG. 4 is a schematic sectional view showing a conventional example of a trench capacitor cell.

In the figure, 51 is a semiconductor substrate which is a p-type silicon (p-Si) substrate, 52 is a field insulating layer which defines a cell region, a silicon dioxide (SiO ₂ ) layer, 53 is an electron which forms an inversion layer by a storage electrode, 54 Is a dielectric layer, 55 is a cell plate (opposite electrode) made of a polycrystalline silicon (poly-Si) layer, the inversion layer 53, the dielectric layer 5
4. The cell plate 55 constitutes a storage capacitor.

56 is a gate insulating layer, 57 is a word line made of poly-Si, 58
A and 58B are high-concentration impurity introduction regions, which are n ⁺ type source / drain regions. A MIS transistor (FET) is formed by using the source / drain regions 58A and 58B and the word line 57 as a gate.

Then, a bit line 59 made of, for example, aluminum (Al) is formed on the substrate in contact with the source / drain region 58A and in a direction perpendicular to the word line 57.

In this case, the connection between the storage capacitor and the MIS transistor is made between the source / drain region 58B and the inversion layer 53, so that the inversion layer 53 on the substrate side becomes the storage electrode for storing the information charges.

As shown on the right side of the figure, the DRAM cell has a storage capacitor of an adjacent cell formed in the vicinity thereof with a field insulating film 52 therebetween. The dotted line represents the tip of the depletion layer spreading in the substrate, and the figure shows the state where adjacent capacitors are punching through.

Such a conventional trench capacitor cell is advantageous for higher integration than a planar type cell, but has the following drawbacks.

Write voltage loss The storage capacitor uses the capacitance between the MOS structure inversion layer 53 and the cell plate 55 formed in the trench.
Only the voltage lower than the cell plate voltage by the threshold voltage for forming 53 can be written, and the power supply voltage cannot be effectively used.

Punch through between capacitors To reduce the above voltage loss, the impurity concentration of the substrate must be lowered, but if it is too low, punch through occurs between the adjacent cell and trench capacitor due to the expansion of the depletion layer as shown in the figure. And the capacitors are electrically coupled, and the reliability of the stored information is impaired.

Also, if a so-called Hi-C capacitor structure is formed in which a region of the opposite conductivity type to the substrate is formed along the surface in the trench, the problem of voltage loss is eliminated, but it is adjacent by the diffusion depth of this opposite conductivity type region. The distance between the trench capacitors is reduced, increasing the risk of punch through.

Further, at this time, the process of introducing impurities into the sidewall of the trench cannot be performed by ion implantation, so that the structure is extremely difficult.

Soft error The depletion layer spreads widely from the storage electrode (inversion layer) 53 in the substrate, and it is easy to capture the minority carriers generated in the substrate.
It is easy to cause a soft error due to line incidence.

The drawbacks described above have been a major obstacle to the practical use of trench capacitors.

[Problems to be solved by the invention]

The problems to be solved by the present invention include the problems of punch through between adjacent storage capacitors, soft error, and the degree of integration due to the cell plate arrangement, which have occurred in the DRAM cell having the conventional trench capacitor as described above. And the problem of lowering the withstand voltage of the source / drain junction of the cell transistor that occurs when the above is solved.

As a solution to such a problem, the conductive region surrounding the trench may be positively separated from the source / drain region. However, in the manufacturing process, the source / drain region and the inner trench surface are made of a dielectric material. There is no choice but to separate them in layers. In order to connect both regions to each other with this dielectric layer sandwiched, it is not only complicated in the process that contact holes are individually provided, but also unevenness can be eliminated on the surface of the wiring after the wiring is formed. This also lowers the reliability of the upper wiring layer, which in turn lowers the yield and reliability of the entire device. In addition, due to the wiring, the gate electrode on the surface and the word line formed in the vicinity cannot be brought close to each other, which is against the miniaturization.

[Means for solving problems]

The above problem is that the first conductive layer having one conductivity type deposited on the inner wall surface of the groove or hole formed from the surface of the one conductivity type semiconductor substrate toward the inside is used as the counter electrode of the capacitor, and A storage capacitor having a second conductive layer having an opposite conductivity type, which fills the inside of the groove or hole having one conductive layer through a dielectric layer, as a storage electrode, and the semiconductor substrate adjacent to the storage capacitor. Is arranged,
One of the source / drain regions is formed of a MIS transistor electrically connected to the storage electrode, and the upper end of the first conductive layer of the storage capacitor is lower than the bottom surface of the source / drain region of the MIS transistor. The first conductive layer and a gap between the upper end of the first conductive layer and the bottom of the source / drain region, the gate electrode of the MIS transistor, and the upper portion of the groove or hole. A word line having a thickness substantially the same as that of the gate electrode, covering both the surface of the one source / drain region and the surface of the groove or hole, and between the gate electrode and the word line. And a buried electrode having a thickness substantially the same as that of the word line and the word line.

[Work]

That is, in the DRAM cell of the present invention, the first conductive layer having a high impurity concentration deposited on the base side of the trench is used as the counter electrode of the storage capacitor, and the second conductive layer is buried in the trench via the dielectric layer.
By using the conductive layer of as the storage electrode, the storage electrode is separated from the substrate to eliminate the coupling between the adjacent trench capacitors, thereby improving the performance and integration of the DRAM cell and increasing the impurity concentration of the trench capacitor. The upper end of the counter electrode having a high concentration and the bottom of the source / drain region on the side of the trench capacitor of the cell transistor are separated from each other, and an insulating layer is interposed between the separated parts as necessary to prevent the breakdown voltage of the source / drain junction from being lowered. To do.

〔Example〕

 Hereinafter, the present invention will be specifically described with reference to illustrated embodiments.

FIG. 1 is a plan view (a) schematically showing a trench capacitor cell according to a first embodiment of the present invention and a sectional view taken along the line AA (b), and FIG. 2 is a second embodiment of the present invention. FIG. 3 is a plan view schematically showing a trench capacitor cell according to the present invention and a sectional view taken along the line AA, and FIGS. 3 (a) to 3 (f) show an example of a manufacturing method of a second embodiment of the trench capacitor cell according to the present invention. It is a process plan view and process cross-sectional views that are shown.

In FIGS. 1A and 1B, 1 is a semiconductor substrate and is a p-Si substrate, 3 is a field insulating layer that defines a cell region, and is an SiO ₂ layer, and 4 is a groove (trench) including the field region. ), 5 is a first conductive layer formed on the entire inner surface of the trench except the region at the depth of d ₁ from the trench opening, and is a cell plate (counter electrode) made of p ⁺ -type poly-Si, 6 is mainly silicon nitride A dielectric layer made of (Si ₃ N ₄ ) 7 is a second conductive layer buried in the trench via the dielectric layer and is a storage electrode made of n ⁺ type poly-Si.

The cell plate 5, the dielectric layer 6, and the storage electrode 7 form a storage capacitor.

8 is a gate insulating layer, a SiO ₂ layer, and 9A and 9B are n ⁺ type source / drain (S / D) having a depth of d _2.
Region, 9C is an n ⁺ type region formed simultaneously with the source / drain region.

10A is the word line (gate electrode) of the self-cell made of a titanium silicide (TiSi ₂ ) layer, and 10B is the word line of the adjacent cell.

The p-Si substrate 1, the gate insulating layer 8, the n ⁺ type S / D regions 9A and 9B, and the word line 10A form a transistor (cell transistor) of the memory cell.

11 is a SiO ₂ insulating layer, 12A is a third conductive layer made of an n ⁺ -type poly-Si layer, 12B is a third conductive layer, which is the S / D region of a transistor, for example, 9B.
And an n ⁺ -type poly-Si layer for electrically connecting the storage electrode 7 of the storage capacitor to each other, whereby the storage capacitor and the cell transistor are connected to form a DRAM cell.

Reference numeral 13 is an interlayer insulating layer, 14 is a wiring contact window, 15 is a contact with the S / D region 9A via the third conductive layer 9A, and aluminum (aluminum (aluminum) extending on the interlayer insulating layer in a direction orthogonal to the word line ( Al) is a bit line.

As shown in the figure, in the trench capacitor cell according to the present invention, the S / D region 9B of the transistor and the storage electrode 7 of the storage capacitor are electrically connected to each other by the third conductive layer 12 (12
B).

Therefore, the second conductive layer 7 in the trench 4 serves as a storage electrode for storing information charges, and the first conductive layer 5 on the substrate side serves as a cell plate (counter electrode).

Then, a third conductive layer for connecting the S / D region 9B of the transistor and the storage electrode 7 of the storage capacitor, that is, n ⁺ -type poly
The Si layer 12 (12B) is the Si exposed between the word lines 10A and 10B.
By selective vapor deposition on the surface, it is formed in self-alignment with the word line without using a mask process.

As a result, miniaturization and high integration of cells can be achieved.

Further, in the structure of the present invention, the upper end portion of the cell plate 5 made of the p ⁺ -type poly-Si layer deposited on the wall surface of the trench 4 has the depth d of the bottom surface of the n ⁺ -type S / D region 9B of the cell transistor. ₂
It is suppressed to a position at a distance of d ₁ from the opening end of the deeper trench, and a space is provided between the cell plate 5 and the bottom surface of the S / D region 9B.

This prevents the n ⁺ type S / D region 9B having a high impurity concentration and the p ⁺ type cell plate 5 having a high impurity concentration from being in direct contact with each other, thereby preventing a decrease in the junction breakdown voltage of the S / D region.

2 (a) and 2 (b) show a second embodiment.

This embodiment is different from the first embodiment in that an n ⁺ type S / D region 9B is used.
That is, the SiO ₂ insulating layer 16 which is thicker than the dielectric layer 6 and which is formed by thermal oxidation, for example, about 1000 to 2000 Å is disposed in the space between the p ⁺ type cell plate 5 and the p ⁺ type cell plate 5.

The other parts are the same as those in the first embodiment, and the respective parts are indicated by the same reference numerals as in FIG.

This structure thermally oxidized SiO ₂ higher thicker withstand voltage as described above
Since the insulating layer 16 is interposed in the space between the n ⁺ type S / D region 9B and the p ⁺ type cell plate 5, the junction breakdown voltage of the S / D region is further increased.

Next, an outline of the method for manufacturing the trench capacitor cell according to the present invention will be described with reference to FIG.
The description will be given with reference to the process plan view and process cross-sectional view shown in FIG.

See FIG. 3 (a). First, as an oxidation resistant film for selective oxidation, for example, a Si ₃ N ₄ layer (or a composite layer of Si ₃ N ₄ and SiO ₂ ) 2 is formed on the element formation region of the p-Si substrate 1 surface. Is formed, and the Si substrate 1 is oxidized using this as a mask to form a SiO ₂ layer 3 having a thickness of 4000 Å as a field insulating layer.

See FIG. 3B. Then, using normal lithography and reactive ion etching (RIE), the trench 4 having a depth of, for example, 3 to 4 μm is formed in the oxidation resistant region including a part of the field insulating layer 3.
Formed, and thermal oxidation is performed again to form a thickness on the inner wall of the trench 4.
A buffer SiO ₂ layer 17 of about 300 Å is formed. Then, a Si ₃ N ₄ layer 18 having a thickness of about 1000Å is deposited on the entire surface by the CVD method, and isotropically etched by the plasma etching method.
The Si ₃ N ₄ layer 18 near the substrate surface and the opening of the trench 4 is removed, and the Si ₃ N ₄ layer 18 functioning as an oxidation resistant film remains on the wall surface of the region near the bottom of the trench 4.

See FIG. 3 (c). Then, selective oxidation is performed using the Si ₃ N ₄ layer 18 as a mask.
A thickness of about 1000Å is applied to the inner wall surface of the trench 4 except near the bottom.
The SiO ₂ insulating layer 16 is formed.

See FIG. 3 (d). The Si ₃ N ₄ layers 2 and 18 are removed, the SiO ₂ layer below these Si ₃ N ₄ layers is removed, and the upper surface of the p-Si substrate 1 and the region near the bottom of the trench 4 are removed. After exposing the wall surface, a p ⁺ -type poly-Si layer with a thickness of about 1000Å doped with boron at a high concentration is formed on the entire surface of the substrate including the inner wall surface of the trench 4 by the CVD method, and isotropic etching (plasma Etching) is performed to leave the p ⁺ -type poly-Si layer 5 only in the trench 4.

At this time, it is a central element of the present invention that the upper end of the p ⁺ type poly-Si layer 5 is located at a distance d ₁ from the opening end of the trench 4 which is larger than the depth of the S / D region of the cell transistor.
The value of d ₁ is about 0.2 to ₁ μm.

The formation of the p ⁺ -type poly-Si layer 5 on the inner surface of the trench is intended to form a region of the same conductivity type as the substrate and a high impurity concentration on the wall surface of the trench. It comes to act as a plate.

Then, as shown in FIG. 3 (e), Si ₃ N _{4 having} a thickness of, for example, about 100Å is formed as a dielectric layer on the entire surface including the inner surface of the trench 4 having the p ⁺ type poly-Si layer 5.
Oxidize the layer (or the SiO ₂ layer, or a composite layer thereof) 6,
Alternatively, it is formed by growth.

It is known that the withstand voltage is improved by annealing this film in an oxygen atmosphere.

Then, on the substrate 1 including the inside of the trench 4, an n ⁺ -type poly-Si layer highly doped with phosphorus is grown to a thickness enough to fill the trench, and then isotropically etched on the substrate. The poly-Si layer is selectively removed to form an n ⁺ -type poly-Si layer 7 which fills the trench 4 with the dielectric layer 6 interposed therebetween. The n ⁺ type poly-Si layer 7, that is, the second conductive layer functions as a storage electrode.

Then, the dielectric layer 6 exposed outside the trench 4 is removed to expose the surface of the Si substrate 1 and then the surface of the substrate 1 is oxidized according to a usual MOS transistor forming method to form a gate insulating film. As a layer, a SiO ₂ layer 8 having a thickness of, for example, about 280 Å is formed. At this time 900
When the oxidation is performed at a low temperature of about ° C, the SiO ₂ layer 8 on the surface of the n ⁺ type poly-Si layer (storage electrode) 7 has a thickness of about 600 Å.

Then, a material to be a gate material such as titanium silicide (TiSi ₂ ) is deposited on the main surface to a thickness of, for example, 400 Å,
Then deposit a SiO ₂ layer 11A having a thickness of about 1500Å on it,
Patterned TiSi ₂ with SiO ₂ layer 11A on top
A word line pattern is formed and then 1500 again on the major surface.
A SiO ₂ layer 11B of about Å is formed, and the SiO ₂ layer 11A or the SiO ₂ layer 11B is left on the upper surface and the side surface of the word line pattern by anisotropic etching means (the above-mentioned known technique), and the surface becomes an insulating layer. TiSi ₂ covered with SiO ₂ layer 11 (11A, 11B)
To form the word lines 10A, 10B and the like. At this time, the surface of the Si substrate 1 not covered by the word lines and the surface of the poly Si layer 7 buried in the trench 4 are exposed.

Then, using a word line (gate electrode) 10A as a mask, phosphorus or arsenic is selectively ion-implanted by an ordinary method to n ⁺
Form source / drain regions 9A and 9B. At this time, the n ⁺ type impurity introduction region 9C is also formed in the n ⁺ type poly-Si layer 7 buried in the trench 4.

See FIGS. 1 (a) and 1 (b). Then, the thickness is formed on the substrate by the usual selective vapor deposition method.
Selective growth of n ⁺ -type poly-Si layer highly doped with phosphorus of about 4000 Å is performed.

At this time, the poly-Si layer does not grow on the SiO ₂ layers 11 and 3, and the source / drain regions 9A and 9B and the n ⁺ -type poly-Si that expose the Si surface are formed.
Third conductive layers 12A and 12B made of n ⁺ -type poly-Si are formed on the layer 7 or the n ⁺ region 9C on the upper surface of the storage electrode. In addition, the n ⁺ -type poly is formed on the edges of the exposed dielectric layer 6 and SiO ₂ insulating layer 16.
Although the Si layer does not grow, the thickness of the Si layer does not reach 2000 Å, so that the poly-Si layer on the source / drain region 6B and the poly-Si layer on the storage electrode 7 become a continuous third conductive layer 12B, and the source / drain is formed. The region 6B and the storage electrode 7 are electrically connected.

After that, the interlayer insulating layer 13 is formed on the entire surface of the substrate by a usual method.
Then, a contact window 14 is opened on the source / drain region 9A where the bit line contacts the cell, and a bit line 15 made of Al or the like is formed.

The memory cell according to the present invention completed as described above is
It has the following features.

The cell plate (counter electrode) of the storage capacitor is the substrate itself (specifically, a conductive layer directly attached to the substrate and having the same conductivity type as the substrate). Therefore, if the substrate is grounded, the potential of the counter electrode is extremely stable, and the so-called voltage bump does not reduce the operation margin or malfunction.

The substrate is one large equipotential electrode plate with no interference between the capacitors, no matter how close they are.

This interference means that leakage of electric charge due to punch-through between capacitors and contact of depletion layers between capacitors cause potential change due to charging / discharging which occurs in one capacitor to another capacitor due to electrostatic coupling. That is, the accumulated charge amount is modulated.

Since the storage electrode is surrounded by the insulating layer and does not greatly expand the depletion layer in the substrate, the soft error is unlikely to occur.

The storage capacitor is made of n ⁺ -type poly Si layer-dielectric layer ~p ⁺ -type poly-Si layer, there is no loss of the write voltage is not used the inversion layer.

The capacitor of the n ⁺ -type semiconductor-dielectric layer ~p ⁺ -type semiconductor structure, the semiconductor side of the depletion layer is generated when a voltage is applied to the storage electrode.

n ^+, depletion and concentration of the p ⁺ low overlaps the dielectric layer, but the storage capacity has one side disadvantageous that would decrease the effective capacitance with a voltage-dependent, n ^+, p ⁺ Higher concentrations do not cause major drawbacks.

Rather, this structure has an advantage that the depletion layer expands and relaxes the electric field in the insulating layer when a high voltage higher than the specified is applied, so that the capacitor is less likely to break down and the breakdown voltage is high.

Since this structure is formed by embedding a capacitor under the source / drain regions of the transistor, the memory cell is substantially the size of one transistor, and the cell itself is significantly reduced as compared with the conventional cell. Since there is no cell plate formed on the substrate in (1), it is not necessary to provide a dimensional margin for alignment between the cell plate and the capacitor and transistor, so that the memory cell becomes smaller.

Further, in the trench capacitor cell having the structure of the present invention, for example, the upper end portion of the p ⁺ type counter electrode having a high impurity concentration formed on the inner wall surface of the trench is connected to the n ⁺ type of the opposite conductivity type.
By controlling to a position deeper than the bottom of the S / D region, n ⁺ type S
Since the / D region and the p ⁺ -type counter electrode are not in direct contact with each other and the insulating layer is interposed in the space between them, the S / D that tends to occur in the trench capacitor cell with the substrate side as the counter electrode. The junction breakdown voltage in the region is prevented from lowering.

The structure of the present invention is not limited to the above-described embodiments, but is applicable to a DRAM cell having a trench capacitor structure formed in an epitaxial layer or a well.

Further, it is of course applied to the DRAM cell of the conductivity type opposite to that of the above embodiment.

〔The invention's effect〕

As described above, according to the present invention, it is possible to obtain a DRAM cell having a trench capacitor structure, which is highly stable, has no interference between capacitors, has a high withstand voltage of capacitors, and can be miniaturized and highly integrated, and a cell transistor. The decrease in junction breakdown voltage of the source / drain regions is prevented.

[Brief description of drawings]

FIG. 1 is a plan view (a) schematically showing a trench capacitor cell according to a first embodiment of the present invention and a sectional view taken along the line AA (b), and FIG. 2 is a second embodiment of the present invention. 2A is a plan view showing a trench capacitor cell according to FIG. 3A and FIG. 3B is a sectional view taken along the line AA of FIG. 3, and FIGS. 3A to 3F are the second embodiment of the trench capacitor cell according to the present invention. FIG. 4 is a schematic side sectional view showing a conventional example of a trench capacitor cell, and FIG. In the figure, 1 is a semiconductor substrate, a p-Si substrate, 3 is a field insulating film layer which is a SiO ₂ layer, 4 is a groove (trench), 5 is a first conductive layer which is a cell plate made of p ⁺ -type poly-Si ( (Counter electrode), 6 is a dielectric layer made of silicon nitride (Si ₃ N ₄ ), 7 is a second conductive layer, a storage electrode made of n ⁺ type poly-Si, 8 is a gate insulating layer, a SiO ₂ layer, 9A , 9B is an n ⁺ type source / drain (S / D) region, and 9C is an n ⁺ type region. 10A is the word line (gate electrode) of the self cell, 10B is the word line of the adjacent cell, 11 is the SiO ₂ insulating layer, 12A and 12B are the third conductive layers made of n ⁺ -type poly-Si layer, and 13 is the interlayer insulation. Layer, 14 is a wiring contact window, 15 is a bit line, and 16 is a SiO ₂ insulating layer.

Claims (1)

[Claims] 1. A first conductive layer having one conductivity type, which is deposited on an inner wall surface of a groove or a hole formed inward from the surface of a one conductivity type semiconductor substrate, is used as a counter electrode of a capacitor.
A storage capacitor having a second conductive layer having an opposite conductivity type, which fills the inside of the groove or hole having the first conductive layer through a dielectric layer, as a storage electrode, and the semiconductor substrate is adjacent to the storage capacitor Is arranged as
One of the source / drain regions is formed of a MIS transistor electrically connected to the storage electrode, and the upper end of the first conductive layer of the storage capacitor is lower than the bottom surface of the source / drain region of the MIS transistor. The first conductive layer is located at a position between the upper end of the first conductive layer and the bottom of the source / drain region, and the gate electrode of the MIS transistor and the upper portion of the groove or hole. A word line having a thickness substantially the same as that of the gate electrode, covering both the surface of the one source / drain region and the surface of the groove or hole, and between the gate electrode and the word line. A dynamic random access memory having a gate electrode and a buried electrode having substantially the same thickness as the word line.