JPH0797637B2 - Heterostructure field effect transistor - Google Patents

Description

The present invention relates to a heterojunction field effect transistor having germanium as an active layer.

[Conventional technology]

Since gallium arsenide has an electron mobility 4 to 5 times higher than that of silicon, various field effect transistors using gallium arsenide as an active layer are used as high speed and high frequency transistors. Among these are, for example, Schottky gate structure field effect transistors (MESFET), selectively doped structure field effect transistors (HEMT), insulated gate structure field effect transistors (SISFET) and the like.

In order to realize a large-scale integrated circuit using such a field effect transistor, it is most desirable to use a complementary circuit in terms of power consumption, operational margin, and the like. In an integrated circuit made of silicon, such a circuit is called a CMOS circuit.

On the other hand, gallium arsenide has electron mobility μe (= 8500 cm ² / V
・ Sec) is large, but hole mobility is μh (= 400cm ² / V ・ s)
ec) is small, and when a complementary circuit is realized, the drain saturation current or transconductance gm of the p-channel field effect transistor becomes small.
Therefore, the characteristics such as the switching time or the degree of integration of the entire complementary circuit including the n-channel and p-channel field effect transistors are limited by the characteristics of the p-channel transistor, which is a major obstacle in terms of speeding up and integration. come.

To avoid this, it is necessary to design the p-channel transistor to have a wide gate width and a large transconductance gm, but this requires a large circuit chip area, making large-scale integration difficult. is there. Alternatively, accompanying this, the wiring length also becomes longer, so that the load due to the wiring increases, the switching time becomes longer, and there is a drawback that it becomes an obstacle in achieving higher speed of the circuit. In fact, the literature IEDM 85, Digest of Technical Papers
According to the data on page 317, in the complementary insulated gate structure field effect transistor circuit realized on the same gallium arsenide wafer, the transconductance gm of the n-channel transistor is 218 mS / mm and the transconductance gm of the p-channel transistor is 28 mS. / mm
It can be seen that the difference in transconductance gm reaches about 8 times.

FIG. 4 is a schematic sectional view of a conventional p-channel field effect transistor. A p-type heavily doped gallium arsenide layer (p-type GaAs layer) 26 is formed on a semi-insulating gallium arsenide substrate 21.
A Schottky junction gate electrode 22 is formed on the gate electrode 26, a p-type high concentration layer (p ⁺ contact layer) 25 formed by an ion implantation method is formed on the left and right sides of the gate electrode 22, and a source electrode 23, A drain electrode 24 is provided, and a p-channel field effect transistor having the gallium arsenide layer 26 as an active layer is realized.

The characteristics of such a p-channel transistor limit the characteristics of the entire circuit, and the superiority of electron mobility in gallium arsenide over silicon is hardly exhibited.

[Problems to be solved by the invention]

As described above, when a complementary field effect transistor circuit is used to realize a large-scale integrated circuit on a gallium arsenide wafer, both the n-channel transistor and the p-channel transistor have active layers made of gallium arsenide. There are drawbacks that the mobility of the holes is small and the characteristics of the entire circuit are limited by the characteristics of the p-channel transistor, which is a serious obstacle to high speed and high integration.

An object of the present invention is to eliminate the drawbacks of these conventional p-channel field effect transistors using gallium arsenide as a substrate and provide a new p-channel field effect transistor.

[Means for solving problems]

In order to achieve the above object, the present invention provides a germanium layer as a channel layer through which holes flow and an electron supply layer or an insulating layer on a gallium arsenide substrate whose crystal axis direction is <1,0,0>. And a gate electrode for applying an electric field in the vertical direction of the laminated structure, and a hole in the in-plane direction of the germanium layer. A source electrode and a drain electrode for injecting and ejecting the gas, and the direction from the source electrode to the drain electrode is made to coincide with the crystal axis direction <1,0,0> of the gallium arsenide substrate.

[Action]

A.G. Milnes and D. El.
Article "Heterojunctions and Metal Semiconductor" by the author Feudt (DLFeucht)
onductor-junctions) (Japanese translation, Sakai, Takahashi, Morizumi, “Semiconductor Heterojunction”, page 9), germanium (hereinafter abbreviated as Ge) gallium arsenide (hereinafter abbreviated as GaAs) is , The lattice constants are almost equal, and the respective thermal expansion coefficients are very close in a wide temperature range centered at room temperature. Therefore, Ge and GaAs can form a heterojunction with extremely good crystallinity.
In addition, GaAs and gallium arsenide aluminum (hereinafter referred to as AlGaA
It is well known that s) also has a lattice constant and a thermal expansion coefficient very close to each other and that a good quality heterostructure can be produced. Therefore,
AlGaAs and Ge make a good heterojunction. However, in a forming method that requires a high temperature, such as liquid phase growth, As in GaAs or AlGaAs diffuses into Ge, and Ge has the property of becoming n-type. However, JM Balingal (J.
M. Ballingall et al., “Journal of Applied Physic”.
s), Vol. 52, No. 6, pp. 4098, and by the same author in the article Journal of Vacuum Science and Technology (Journal of Vacuum Science and Technology).
Vacuum Science and Technology), Vol. B1, No. 3, page 675, using the molecular beam epitaxial growth (MBE) method, Ge is deposited on a GaAs substrate at 250 ° C to 300 ° C.
Epitaxial growth is performed at a low temperature of ℃. At this time Ge
The heterojunction interface of GaAs can be epitaxially grown in a very steep state. This can be verified also by the fact that the Ge-to-GaAs transition region is estimated to be about 10 angstroms even after a thermal history of 400 ° C. for 1 hour according to the two documents by JM Balingal. In addition, the article “Journal of Vacuum Science and Technolog by CAChang et al.
y) ”, Vol. 19, No. 3, pp. 567, the interdiffusion at the heterojunction interface between Ge and GaAs is 400 ° C,
It is reported to be less than 10 angstroms even after 4 hours of thermal history. Therefore, the heterojunction interface between Ge and GaAs is extremely steep on the order of several atomic layers even if there is a temperature history of about 400 ° C., it does not interdiffuse, and the lattice constant and temperature expansion coefficient of both are extremely high. Because of the closeness, it is considered that an ideal heterojunction can be performed without any defects or distortions and maintaining good crystallinity. As described above, the diffusion of As into Ge has been reported only at the interface between GaAs and Ge, but it is considered that the same applies to the interface between AlGaAs and Ge. Therefore, by utilizing the low-temperature growth by the MBE method, it is possible to suppress the diffusion of As into Ge and use a good-quality Ge layer as a channel layer in which holes flow. Also, the forbidden band width of Ge is 0.66 eV and the forbidden band width of GaAs is 1.42 eV. According to the above two documents by J.M. Balingal, the energy on the conduction band side at the heterojunction surface of Ge and GaAs is The discontinuity value is as small as 80 meV,
It can be seen that the discontinuity in the forbidden band width of the two semiconductors is almost in the valence band. The energy discontinuity in the valence band is
Ge and GaAs are about 0.7 eV, which is much larger than the typical conduction band discontinuity of GaAs and Al _0.3 Ga _0.7 As forming a heterojunction of about 0.1 eV. Therefore Ge
When the layer is a channel layer through which holes flow, the GaAs layer can serve as a barrier layer against holes in the Ge layer. AlGaAs has a wider forbidden band width than GaAs, and with Al _0.3 Ga _0.7 As and Ge, the valence band discontinuity is 0.8 eV, which is a better barrier layer. The above situation is shown in FIGS. 3 (a) and 3 (b). In this way, a metal / insulator / semiconductor charge effect transistor (MISFET) having a Ge layer as a channel layer in which holes flow and an AlGaAs as an insulating layer can be realized. The mobility μh of holes in Ge is 1900 cm ² /
Since it is very large (V · sec), when the holes in Ge are used as a carrier of a field effect transistor (FET), the transconductance gm is p-type using conventional GaAs.
It is possible to make a high-performance p-type FET that has a very large value of 5 times or more compared to FET.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic sectional view of a first example of a heterostructure field effect transistor according to the present invention. In the figure,
On the semi-insulating GaAs (1,0,0) substrate 1, a p-type Ge layer 2 and then an intrinsic Al _0.3 Ga _0.7 As layer 3 were sequentially grown by the MBE method. Al _0.3 Ga _0.7 using aluminum as a gate electrode 4 on the As layer 3, deprived of Al _0.3 Ga _0.7 As layer 3 in the portion other than the lower gate electrode by self-alignment method, a source electrode 5, a drain electrode 6, a gold / By depositing an indium alloy and diffusing indium at a low temperature of 350 ° C, p
^{A +} contact layer 7 was formed and contacted with the p-type Ge layer 2 which is a channel layer through which holes flow. Intrinsic Al _0.3 Ga _0.7
The As layer 3 can be epitaxially grown with good crystallinity, and the Al _0.3 Ga _0.7 As layer 3 has aluminum and barrier height.
In order to form a good Schottky junction of 1.2 eV, the leakage current from the gate electrode was suppressed to a negligible small value.
Here, the direction from the source electrode to the drain electrode is the <1,0,0,> direction of the substrate. This is because the holes in Ge are in the <1,0,0> direction, as described by L. Reggiani et al. In the article Physical Review, Volume B16, No. 6, page 2781. On the other hand, the mobility is maximum. Therefore, by making the direction from the source electrode to the drain electrode the <1,0,0> direction, the field effect transistor with the largest gm can be realized. Other metals may be used for the gate electrode described above.

FIG. 2 is also a schematic sectional view of a second embodiment of the heterostructure field effect transistor according to the present invention. Semi-insulating
Intrinsic GaAs layer 12 and intrinsic Ge layer 1 on GaAs (1,0,0) substrate 11
3. Then, the p-type Al _0.3 Ga _0.7 As layer 14 was sequentially grown by the MBE method. This structure is known as a selective doping structure, and G having a small first ionization energy at the AlGaAs / Ge interface.
A two-dimensional hole gas 15 is formed on the e side (see FIG. 3 (b)). The Ge / AlGaAs interface where the two-dimensional hole gas 15 is formed is steep as described in the section of the above action.
The layer and the AlGaAs layer can be grown with good crystallinity.
Al _0.3 Ga _0.7 using aluminum as the gate electrode 16 on the As layer 14, deprived of Al _0.3 Ga _0.7 As layer 14 in the portion other than the lower gate electrode by self-alignment method, a source, a drain electrode 17, a gold / Evaporate indium alloy, 350 ℃
A p ⁺ contact layer 19 was formed by diffusing indium at a low temperature, and contacted with a two-dimensional hole gas. Here, the direction from the source electrode to the drain electrode is the <1,0,0> direction of the substrate. Other metals may be used for the gate electrode described above. Further, the portions below the source and drain electrodes that make contact with the two-dimensional hole gas can also be manufactured by ion implantation using boron or the like.

When aluminum arsenide (AlAs) having the maximum aluminum composition is used for the barrier layer, the barrier height is the highest, but the barrier layer is easily exposed to the atmosphere and oxidized. Here AlGa
The composition ratio of As to aluminum and gallium was 3: 7, but any value can be used depending on the application.

〔The invention's effect〕

The p-channel field-effect transistor according to the first example of the present embodiment makes gallium arsenide active by using germanium having a large hole mobility as an active layer and using a Ge / AlGaAs heterojunction having a large valence band discontinuity. P as a layer
Compared with the channel field effect transistor, gm increases by about 5 times. As a result, the gm of the p-channel field effect transistor formed on the gallium arsenide substrate is about 140 mS /
It is expected to increase to about mm, which is close to gm = 218 mS / mm for the n-channel field effect transistor that is also formed on the gallium arsenide substrate, realizing a complementary field effect transistor circuit capable of high speed and high integration. it can.

The p-channel field effect transistor according to the second example of the present embodiment uses a germanium having a large hole mobility as an active layer and further uses a Ge / AlGaAs heterojunction having a large valence band discontinuity to form a two-dimensional hole gas. Since it is a selectively-doped FET that can have a large areal density Ns, gm is increased by about 10 times as compared with a p-channel field effect transistor using gallium arsenide as an active layer. As a result, the p-channel field effect transistor formed on the gallium arsenide substrate is
It is expected that gm will increase to about 250 mS / mm, which is about the same as gm = 218 mS / mm for n-channel field-effect transistors also formed on a gallium arsenide substrate, which is a complementary electric field capable of high speed and high integration. An effect transistor circuit can be realized.

[Brief description of drawings]

FIG. 1 is a sectional configuration diagram of a first example of a field effect transistor according to the present invention, FIG. 2 is a sectional configuration diagram of a second example of a field effect transistor according to the present invention, and FIG. Energy band diagram to explain
(A) shows the case where both Ge and AlGaAs are intrinsic, and (b) shows the case where the acceptor is doped on the AlGaAs side.
It is a sectional view of a hole channel FET using GaAs. 1,11 ... Semi-insulating GaAs substrate, 2 ... p-type Ge layer 3 ... intrinsic Al _0.3 Ga _0.7 As layer, 4,16 …… gate electrode 5,17 …… source electrode, 6,18 …… drain Electrodes 7, 19 …… p ⁺ contact layer, 12 …… intrinsic GaAs layer 13 …… intrinsic Ge layer, 14 …… p-type Al _0.3 Ga _0.7 As layer GaAs layer 15 …… two-dimensional hole gas

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 29/80 29/812 9171-4M H01L 29/80 A

Claims (1)

[Claims] 1. A germanium layer as a channel layer in which holes flow, and gallium arsenide and aluminum arsenide as an electron supply layer or an insulating layer on a gallium arsenide substrate having a crystal axis direction of <1,0,0>. A gate electrode for applying an electric field in the vertical direction of the laminated structure, and a source electrode for injecting and ejecting holes in the in-plane direction of the germanium layer. A hetero-structure field effect transistor comprising: a drain electrode, wherein a direction from the source electrode to the drain electrode is aligned with a direction <1,0,0> of a crystal axis of the gallium arsenide substrate.