JPH0798618A - Counter readout circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a counter reading circuit that can read time data from a counter circuit only once, thereby reducing the load on a program. [Configuration] Buffer registers 31a to 31g capable of individually storing the data of each counter are connected to the counters 30a to 30g for seconds, minutes, hours, days of the week, days, months, years, etc.
Then, the determination of the timing for transferring data from the counter 30a~30g to the buffer register 31a to 31g, using an event occurrence signal S _2, such as updates and carry the second counter. In addition, the CPU 2 performs an operation of reading the data stored in the buffer registers 31a to 31g by using the event occurrence signal as a trigger. [Effect] There is no need to confirm the validity of the data, such as reading the counter data twice to confirm the coincidence or checking the carry flag to confirm that no carry has occurred. , It is possible to reduce the burden on the program.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a counter reading circuit, and more particularly to a technique which is particularly effective when applied to reading a plurality of counters at the same time. For example, time data from a counter circuit for calendar / clock function. The present invention relates to a circuit technology useful for reading out data.

[0002]

2. Description of the Related Art In recent years, various kinds of electric equipment, the operation of which is controlled by a microcomputer, to which a calendar / clock function is added are known. Such an additional function is realized by providing an IC chip for the calendar / clock function in addition to the LSI chip for the CPU, or by forming the CPU and the circuit for the calendar / clock function on the same LSI chip.

In any of the above cases, the calendar / clock function circuit includes, for example, a plurality of counters having a hierarchical structure,
That is, a counter circuit including a second counter, a minute counter, an hour counter, a day of the week counter, a day counter, a month counter, and a year counter is provided. The second counter counts up every 1 second, the minute counter carries up every 60 seconds and counts up. For example, each counter counts up every predetermined time.

When a time read command provided in the program is executed, for example, the CPU reads time data from the calendar / clock function circuit.
The read operation is, for example, first reading the data of the second counter, then reading the data of the minute counter, and then reading the data of the hour counter, such as the second counter, minute counter, hour counter, day counter, and day counter. The month counter and year counter are read out sequentially.

[0005]

However, the present inventors have clarified that the above-mentioned technique has the following problems. That is, since the above counters are sequentially read one by one, it takes time until the reading of all counters is completed. for that reason,
A carry may occur during the reading of each counter, and in that case, a large difference occurs between the time data read from the counter circuit and the actual time.

A case where such a deviation occurs will be specifically described on the assumption that the time read command is executed at the time "23:59:59 on December 31, 1999", for example. At the start of execution of the read command, “59” is stored in the second counter and the minute counter,
The hour counter stores “23”, the day counter stores “31”, the month counter stores “12”, and the year counter stores “1999”.

Then, "59" is read from the second counter, "59" is read from the minute counter, "23" is read from the hour counter, and "31" is read from the day counter. If the second counter counts up when “12” is read from the month counter, the second counter, minute counter, and hour counter are updated to “0”, and the day counter and month counter are each set to “1”. ", And the year counter is updated to" 2000 ". Therefore, if you read from the year counter subsequently to the month counter, "2000" will be read.
The time obtained by this series of reading is "200
It was 23:59:59 on December 31, 2000 ”.

In order to prevent the occurrence of such a shift, the above-mentioned read command is repeated twice and it is determined whether the time data read at the first time and the time data read at the second time match. However, if they match, it is determined that the correct time has been obtained, and if they do not match, a program may be created so that the time data is read again assuming that the above-mentioned deviation has occurred. Alternatively, a carry flag is set when a carry occurs in the minute, hour, day, month, or year counter, and it is correct if the flag is not set when the time data is read. A program may be created so that it is determined that the time has been obtained, and if the flag is set, the above-mentioned deviation is considered to have occurred and the time data is read again. However, in any case, there is a drawback that the program becomes extremely complicated.

The present invention has been made in view of the above circumstances, and provides a counter reading circuit configured so that the time data can be read from the counter circuit only once, thereby reducing the load of the program. Is the main purpose. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, in the counter reading circuit of the present invention, a buffer register capable of individually storing the data of each counter is connected to each counter such as seconds, minutes, hours, days of the week, days, months, and years. Then, in order to determine the timing of data transfer from each counter to the buffer register, an event occurrence signal such as update of the second counter or carry is used. Further, the CPU uses the event occurrence signal as a trigger to read the data stored in the buffer register. A RAM may be used instead of a new buffer register.

[0011]

According to the above-mentioned means, the buffer register is connected to each counter, and after the occurrence of an event such as the update of the second counter or the carry, until the occurrence of the next event, the buffer register is released from each counter. Since data transfer to and from the buffer register is performed, updated data immediately after an event occurs is stored in the buffer register and is read immediately after that, so the time obtained from the read data is Match the actual time.

[0012]

1 shows an example of a counter reading circuit according to the present invention. In the figure, reference numeral 1 is an LSI
It is a chip, reference numeral 2 is a CPU (central processing unit), and reference numeral 3 is a calendar / clock function circuit. The circuit 3 includes a counter circuit (counter means) 30, a buffer circuit (buffer means) 31, and a carry confirmation circuit (so-called,
Carry look ahead circuit) 32 and carry flag latch circuit 33.

The counter circuit 30 is, for example, a second counter 3
0a, minute counter 30b, hour counter 30c, day counter 30d, day counter 30e, month counter 30f, and year counter 30g. The buffer circuit 31 includes the counters 30a, 30b, 30c, 30d, 30.
Buffer register 3 corresponding to e, 30f, and 30g, respectively
1a, 31b, 31c, 31d, 31e, 31f, 31
g, each of the counters 30a, 30b, 30
The data of c, 30d, 30e, 30f and 30g can be stored individually.

The carry confirmation circuit 32 includes a second counter 30a.
Other counters 30b, 30 such as minutes and hours
When carry occurs in c, 30d, 30e, 30f, 30g, temporarily wait until the carry ends,
Then it goes to the next step. The carry flag latch circuit 33 temporarily holds a carry end signal S ₃ generated by updating the second counter 30a or occurrence of a carry, and also sends an interrupt request signal S ₅ to the CPU 2. .

Reference numeral 4 is a peripheral function section, for example, a timer 40 and a serial communication interface 4
1, DMA (Direct Memory Acces)
s) Consists of a controller 42 and an input / output port 43. Reference numeral 5 denotes a first oscillator, which generates a system clock signal for the CPU 2 and the peripheral function unit 4 based on a signal oscillated by a crystal oscillator 6 (its oscillation frequency is, for example, 10 MHz). Reference numeral 7 is a second oscillator, and a crystal oscillator 8
(The oscillation frequency is, for example, 32.768 kHz.)
The basic clock signal S ₀ of the calendar / clock function circuit 3 is generated on the basis of the signal oscillated in ( ₁ ). Reference numeral 9 is a frequency divider for applying a 1-second pulse to the clock signal S ₀ , that is, 1 Hz.
Signal S ₁ of.

Next, the data read processing of the counter circuit 30 will be described. First, the basic clock signal S ₀ generated from the second oscillator 7 is converted into a 1-second pulse signal S ₁ by the frequency divider 9 and input to the second counter 30a.
The data of the second counter 30a is incremented and updated by the count-up means having such a configuration. Then, the count-up signal (event occurrence signal) S ₂ is output from the second counter 30a and input to the carry confirmation circuit 32. Based on the count-up signal S ₂ , the minute counter 30b, the hour counter 30c,
Day counter 30d, day counter 30e, month counter 3
The carry of 0f and the year counter 30g is carried out appropriately.

When the carry is completed, the carry confirmation circuit 32
Then, a carry end signal S ₃ is issued and latched in the carry flag latch circuit 33. Carry confirmation circuit 32 at the same time
From which a data transfer signal S ₄ is issued. By this signal S ₄ , the counters 30a, 3 of the gate group 34 provided between the counter circuit 30 and the buffer circuit 31 are
The individual gates corresponding to 0b, 30c, 30d, 30e, 30f and 30g are opened. Each of the counters 30a, 30 is constructed by the data transfer means having such a configuration.
Data of b, 30c, 30d, 30e, 30f, and 30g are buffer registers 31a, 31b, 31c, 31d,
31e, 31f, 31g are transferred respectively.

As described above, the carry flag latch circuit 3
In step 3, when the carry end signal S ₃ is latched, C
An interrupt request signal S ₅ is issued to PU2. CP
U2 accepts the interrupt request signal S _5, the buffer register 31a, 31b, 31c, 31d, 31e,
The read programs 31f and 31g are read from the ROM 45. Then, the CPU 2 executes the program and issues a read signal S ₆ to the buffer circuit 31. By the data reading means having such a configuration, the CP
U2 is a buffer register 31a, 31b, 31c,
Data D ₀ , D ₁ , D of 31d, 31e, 31f, 31g
₂ , D ₃ , D ₄ , D ₅ , and D ₆ are loaded on the data bus 10 and fetched. The carry flag latch circuit 33 is cleared by the read signal S ₆ . The above-mentioned data D ₀ , D ₁ , D
The reading process of ₂ , D ₃ , D ₄ , D ₅ , and D ₆ is performed by the second counter 3
The data of 0a is completed by the next update.

According to the above embodiment, the buffer registers 31a, 31b, 31c, 31d, 31e, 31f,
Since the updated data immediately after the occurrence of an event such as counting up or carry is stored in 31g and the data is read immediately after that, the read data D ₀ , D ₁ , D ₂ , D ₃ , Since the time obtained from D ₄ , D ₅ , and D ₆ always matches the actual time, it is not necessary to confirm the validity of the data, and the load on the program can be reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the calendar / clock function circuit 3 includes a counter circuit 30 and a buffer circuit 31, and each counter 30a,
Buffer registers 31a, 31b, 31 corresponding to the data of 30b, 30c, 30d, 30e, 30f, 30g
Needless to say, the present invention is not limited to the above configuration as long as the data can be read at the same time via c, 31d, 31e, 31f and 31g.

Further, a DMA controller 42 is used instead of the CPU 2, and a signal from the carry flag latch circuit 33 (corresponding to the interrupt request signal S ₅ in the above embodiment) is input to the DMA controller 42, and the DMA is based on the signal. The controller 42 directly transfers the buffer register 31
a, 31b, 31c, 31d, 31e, 31f, 31g
It is also possible to read each of the above data and transfer the data to a RAM or the like. With this configuration, the CPU 2 can perform another process while the counter reading process is being performed.

Furthermore, the CPU and the calendar / clock function circuit are not limited to the case of being formed on the same LSI chip.
In addition to U LSI chips, ICs for calendar and clock functions
It is also applicable when a chip is provided.

In the above description, the invention made by the present inventor was mainly applied to a counter circuit for a calendar / clock function, which is the field of application which was the background of the invention, but the invention is not limited thereto. Instead, it can be used for general counter circuits other than those for calendar / clock functions.

[0024]

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, since the updated data input to the buffer register is read immediately after the occurrence of an event such as counting up or carry,
The time obtained from the read data always matches the actual time. Therefore, it is not necessary to confirm the correctness of the data by reading the data twice to confirm the coincidence or by referring to the carry flag to confirm that the carry has not occurred. It is possible to reduce the burden of.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a counter reading circuit according to the present invention.

[Explanation of symbols]

 2 CPU 3 Calendar / Clock Function Circuit 7 Second Oscillator (Count Up Means) 8 Crystal Oscillator (Count Up Means) 9 Frequency Divider (Count Up Means) 30 Counter Circuit (Counter Means) 30a Second Counter 30b Minute Counter 30c Hour counter 30d Day counter 30e Day counter 30f Month counter 30g Year counter 31 Buffer circuit (buffer means) 32 Carry confirmation circuit (data transfer means) 33 Carry flag latch circuit (data read means) 34 Gate group (data transfer means) 45 ROM (data reading means)

Claims (3)

[Claims] 1. A counter means composed of a plurality of counters having a counting function, a buffer means connected to each counter and capable of individually storing data of each counter, and data of the counter at every unit time. And a data transfer means capable of transferring the data of each counter to the buffer means at the same time or substantially the same time after the end of the data update and before the next data update. Counter readout circuit. 2. The data read means for reading the data transferred by the data transfer means from the buffer means after the end of the data update and before the next data update. Counter reading circuit. 3. The counter reading circuit according to claim 1, wherein the counter is a second counter, a minute counter, an hour counter, a day of the week counter, a day counter, a month counter, and a year counter.