JPH0799276A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0799276A JPH0799276A JP5242269A JP24226993A JPH0799276A JP H0799276 A JPH0799276 A JP H0799276A JP 5242269 A JP5242269 A JP 5242269A JP 24226993 A JP24226993 A JP 24226993A JP H0799276 A JPH0799276 A JP H0799276A
- Authority
- JP
- Japan
- Prior art keywords
- external lead
- lead connection
- terminal
- semiconductor device
- connection terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10742—Details of leads
- H05K2201/1075—Shape details
- H05K2201/10757—Bent leads
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
(57)【要約】
【目的】外部リード接続端子の平坦度が良好な半導体装
置を得る。
【構成】金属ベース１ａ外周部に樹脂からなるケース側
面１ｂとこのケース側面上部に複数個の端子台１ｃを形
成し、この端子台１ｃに外部リード接続端子２がそれぞ
れ一体モールドされたケース１を用いる半導体装置にお
いて、前記端子台１ｃの外部リード接続端子引出し部２
ａに端子台上面より低い段差部３を設け、段差部側面に
対向する外部リード接続端子との間にすき間４を設け
る。
(57) [Abstract] [Purpose] To obtain a semiconductor device in which the flatness of external lead connection terminals is good. [Structure] A case side 1b made of resin is formed on the outer periphery of a metal base 1a, and a plurality of terminal blocks 1c are formed on the upper side of the case, and a case 1 in which external lead connection terminals 2 are integrally molded is formed on the terminal block 1c. In the semiconductor device used, the external lead connection terminal lead-out portion 2 of the terminal block 1c
A stepped portion 3 lower than the upper surface of the terminal block is provided in a, and a gap 4 is provided between the external lead connection terminal and the side surface of the stepped portion facing each other.
Description
【０００１】[0001]
【産業上の利用分野】この発明はインテリジェントパワ
ーモジュールなどの半導体装置に係わり、特に入力端子
および出力端子の整形に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as an intelligent power module, and more particularly to shaping of input terminals and output terminals.
【０００２】[0002]
【従来の技術】図３に基づいて説明する。図３は従来例
を示す構成図であり、（ａ）は平面図、（ｂ）はｂ−ｂ
線断面拡大図である。この種の半導体装置は一般的に金
属ベース１ａ外周部に樹脂よりなるケース側面１ｂを形
成したケース１を固着し、金属ベース上面に複数個の半
導体チップ６を絶縁板を介してはんだ等で固着し、その
上層部に図示しない制御回路基板を配置し、この制御回
路基板と半導体チップ６との間の配線および外部リード
接続端子２との間の配線をし、その後図示しないシリコ
ーン系ゲル状樹脂あるいはそれに類するゲル状樹脂を注
入し、その後１２０℃で２時間加熱し樹脂を硬化してい
る。2. Description of the Related Art A description will be given with reference to FIG. 3A and 3B are configuration diagrams showing a conventional example, where FIG. 3A is a plan view and FIG. 3B is bb.
FIG. In this type of semiconductor device, generally, a case 1 in which a case side surface 1b made of resin is formed on the outer peripheral portion of a metal base 1a is fixed, and a plurality of semiconductor chips 6 are fixed on the upper surface of the metal base with solder or the like via an insulating plate. Then, a control circuit board (not shown) is arranged on the upper layer thereof, wiring between the control circuit board and the semiconductor chip 6 and wiring between the external lead connecting terminals 2 are performed, and then a silicone gel resin (not shown) is formed. Alternatively, a gel-like resin similar to that is injected and then heated at 120 ° C. for 2 hours to cure the resin.
【０００３】この半導体装置のケース側面１ｂ上面には
端子台１ｃが７個所に形成されており、外部リード接続
端子２ｂが図３（ｂ）に点線で示すようにそれぞれ端子
台１ｃに垂直に一体モールドされている。この各外部リ
ード接続端子２ｂを図３（ｂ）に実線で示すように９０
°折り曲げて出荷している。Terminal blocks 1c are formed at seven places on the upper surface of the side surface 1b of the semiconductor device, and external lead connection terminals 2b are vertically integrated with the terminal blocks 1c as shown by dotted lines in FIG. 3 (b). It is molded. These external lead connection terminals 2b are connected to each other as shown by a solid line in FIG.
° Bending and shipping.
【０００４】[0004]
【発明が解決しようとする課題】前述の方法によれば、
各端子を９０°折り曲げる時に図３（ｂ）に示すように
各外部リード接続端子引出し部に膨らみが生じ端子の平
坦度が悪くなり、顧客側で外部リードを接続するとき密
着性が悪化するという問題が発生している。この発明は
前記の問題点に鑑みてなされたものであり、その目的は
各外部リード接続端子の平坦度が良好な半導体装置を提
供することにある。According to the method described above,
When each terminal is bent 90 °, as shown in FIG. 3B, the external lead connection terminal lead-out portion bulges to deteriorate the flatness of the terminal, resulting in poor adhesion when connecting the external lead on the customer side. There is a problem. The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor device in which each external lead connection terminal has good flatness.
【０００５】[0005]
【課題を解決するための手段】この発明によれば前述の
目的は、端子台の外部リード接続端子引出し部に端子台
上面より低い段差部を設け、段差部側面に対向する外部
リード接続端子との間にすき間を設けることにより達成
される。さらに外部リード接続端子の前記段差部の上面
に位置する個所にＶみぞを形成すること、さらには外部
リード接続端子が当接する前記段差部の先端部に曲面部
を形成することが有効である。According to the present invention, the above object is to provide an external lead connection terminal lead-out portion of a terminal block with a step portion lower than the upper surface of the terminal block, and to connect the external lead connection terminal to the side surface of the step portion. This is achieved by providing a gap between the two. Further, it is effective to form a V groove in a portion of the external lead connecting terminal located on the upper surface of the step portion, and further to form a curved surface portion in the tip portion of the step portion with which the external lead connecting terminal abuts.
【０００６】[0006]
【作用】この発明の構成によれば、端子台の外部リード
接続端子引出し部に端子台上面より低い段差部を設け、
段差部側面に対向する外部リード接続端子との間にすき
間を設けることとしたため、外部リード接続端子を折り
曲げるときに端子台上面より低い位置にある外部リード
接続端子引出し部に最大応力がかかり、前記すき間分だ
け曲がりこの曲がった分だけ膨らみが吸収される。さら
に外部リード接続端子の前記段差部の上面に位置する個
所にＶみぞを形成することとしたため、Ｖみぞ部の断面
積が減少した分だけ曲がりやすくなる。さらには外部リ
ード接続端子が当接する前記段差部の先端部に曲面部を
形成することにより、曲面部に沿って無理なく曲がるた
めこの部分で膨らみが吸収されることになる。According to the structure of the present invention, the external lead connection terminal lead-out portion of the terminal block is provided with a step portion lower than the upper surface of the terminal block,
Since a gap is provided between the external lead connecting terminal facing the step side surface and the external lead connecting terminal is bent, maximum stress is applied to the external lead connecting terminal lead-out portion located at a position lower than the upper surface of the terminal block. It bends only for the gap, and the bulge is absorbed only for this bending. Further, since the V-shaped groove is formed at a position located on the upper surface of the step portion of the external lead connection terminal, the V-shaped groove is bent more easily because the cross-sectional area of the V-shaped groove portion is reduced. Further, by forming a curved surface portion at the tip of the step portion with which the external lead connection terminal abuts, the curved portion is naturally bent, so that the bulge is absorbed at this portion.
【０００７】[0007]
【実施例】図１および図２に基づいて説明する。図１は
この実施例を示す構成図であり、（ａ）は平面図、
（ｂ）はａ−ａ線断面拡大図である。図２はこの実施例
を示す別の構成図であり、（ａ）はＶみぞを形成した図
１におけるａ−ａ線断面拡大図、（ｂ）は曲面部を形成
した図１におけるａ−ａ線断面拡大図である。従来例と
同一の機能要素をもつものは同一符号を付してある。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An explanation will be given with reference to FIGS. FIG. 1 is a configuration diagram showing this embodiment, (a) is a plan view,
(B) is an aa line sectional enlarged view. 2A and 2B are another structural views showing this embodiment, in which FIG. 2A is an enlarged sectional view taken along line aa in FIG. 1 in which a V groove is formed, and FIG. 2B is aa in FIG. 1 in which a curved surface portion is formed. FIG. Those having the same functional elements as those in the conventional example are designated by the same reference numerals.
【０００８】この実施例では図１（ｂ）に示す段差部４
の深さを１ｍｍ、段差部側面に対向する外部リード接続
端子２ａとの間のすき間５を１ｍｍとした。この半導体
装置を端子整形ジグを用いて外部リード接続端子２を９
０°に曲げた結果、膨らみの発生は認められなかった。
さらに図２（ａ）に示す外部リード接続端子引出し部２
ａより１ｍｍ上方にＶみぞ８を形成したものについても
同様の結果が得られた。さらには図２（ｂ）に示す段差
部４の先端部に曲面部９を形成したものについても同様
の結果が得られた。この場合は段差部側面に対向する外
部リード接続端子との間にすき間５を無くしても同様の
効果を得られることも確認した。In this embodiment, the step portion 4 shown in FIG.
Is 1 mm, and the gap 5 between the external lead connection terminal 2a facing the side surface of the step portion is 1 mm. This semiconductor device is connected to the external lead connection terminal 2 by using a terminal shaping jig.
As a result of bending at 0 °, no bulge was observed.
Further, the external lead connection terminal lead-out portion 2 shown in FIG.
Similar results were obtained with the V groove 8 formed 1 mm above a. Further, similar results were obtained with the curved portion 9 formed at the tip of the step portion 4 shown in FIG. 2 (b). In this case, it was also confirmed that the same effect can be obtained even if the gap 5 is not provided between the external lead connection terminal facing the step side surface.
【０００９】[0009]
【発明の効果】この発明によれば、実施例で行った３通
りの方法のいずれにおいても膨らみの発生は認められな
く、外部リード接続端子曲げ加工後の平坦度が良好な半
導体装置が得られた。また従来極わずか発生していた端
子台の割れも無くなるという付随効果も得られた。According to the present invention, no bulge is observed in any of the three methods carried out in the embodiments, and a semiconductor device having good flatness after bending of external lead connection terminals can be obtained. It was In addition, the attendant effect of eliminating cracks in the terminal block, which had been generated only slightly in the past, was also obtained.
【図１】この実施例を示す構成図であり、（ａ）は平面
図、（ｂ）はａ−ａ線断面拡大図1A and 1B are configuration diagrams showing this embodiment, in which FIG. 1A is a plan view and FIG. 1B is an enlarged sectional view taken along line aa.
【図２】この実施例を示す別の構成図であり、（ａ）は
Ｖみぞを形成した図１におけるａ−ａ線断面拡大図、
（ｂ）は曲面部を形成した図１におけるａ−ａ線断面拡
大図FIG. 2 is another configuration diagram showing this embodiment, in which (a) is an enlarged cross-sectional view taken along the line aa in FIG. 1 in which a V groove is formed,
(B) is an enlarged sectional view taken along the line aa in FIG. 1 in which a curved surface portion is formed.
【図３】従来例を示す構成図であり、（ａ）は平面図、
（ｂ）はｂ−ｂ線断面拡大図FIG. 3 is a configuration diagram showing a conventional example, (a) is a plan view,
(B) is an enlarged view of a bb line cross section.
１ ケース １ａ 金属ベース １ｂ ケース側面 １ｃ 端子台 ２ 外部リード接続端子 ２ａ 外部リード接続端子引出し部 ２ｂ 外部リード接続端子整形前 ３ 膨らみ ４ 段差部 ５ すき間 ６ 半導体チップ ７ 蓋 ８ Ｖみぞ ９ 曲面部 1 case 1a metal base 1b case side surface 1c terminal block 2 external lead connection terminal 2a external lead connection terminal lead-out part 2b external lead connection terminal before shaping 3 bulge 4 step part 5 gap 6 semiconductor chip 7 lid 8 V groove 9 curved surface part
Claims (3)
面とこのケース側面上部に複数個の端子台を形成し、こ
の端子台に外部リード接続端子がそれぞれ一体モールド
されたケースを用いる半導体装置において、前記端子台
の外部リード接続端子引出し部に端子台上面より低い段
差部を設け、段差部側面に対向する外部リード接続端子
との間にすき間を設けたことを特徴とする半導体装置。1. A semiconductor device using a case in which a case side made of resin is formed on the outer peripheral portion of a metal base, and a plurality of terminal blocks are formed on the upper side of the case side, and external lead connection terminals are integrally molded on the terminal block. A semiconductor device characterized in that a step portion lower than the upper surface of the terminal block is provided in the external lead connection terminal lead-out portion of the terminal block, and a gap is provided between the external lead connection terminal facing the side surface of the step portion.
接続端子の前記段差部の上面に位置する個所にＶみぞを
形成したことを特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein a V groove is formed at a position located on the upper surface of the step portion of the external lead connection terminal.
接続端子が当接する前記段差部の先端部に曲面部を形成
したことを特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein a curved surface portion is formed at a tip portion of the step portion with which the external lead connection terminal abuts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5242269A JPH0799276A (en) | 1993-09-29 | 1993-09-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5242269A JPH0799276A (en) | 1993-09-29 | 1993-09-29 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0799276A true JPH0799276A (en) | 1995-04-11 |
Family
ID=17086755
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5242269A Pending JPH0799276A (en) | 1993-09-29 | 1993-09-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0799276A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10120402A1 (en) * | 2001-04-25 | 2002-11-14 | Danfoss Silicon Power Gmbh | Housing for power semiconductor module with plastics body |
| JP2011018933A (en) * | 2010-09-16 | 2011-01-27 | Mitsubishi Electric Corp | Semiconductor device, and method of manufacturing the same |
-
1993
- 1993-09-29 JP JP5242269A patent/JPH0799276A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10120402A1 (en) * | 2001-04-25 | 2002-11-14 | Danfoss Silicon Power Gmbh | Housing for power semiconductor module with plastics body |
| DE10120402B4 (en) * | 2001-04-25 | 2005-04-14 | Danfoss Silicon Power Gmbh | The power semiconductor module housing |
| JP2011018933A (en) * | 2010-09-16 | 2011-01-27 | Mitsubishi Electric Corp | Semiconductor device, and method of manufacturing the same |
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