JPH0799310A - Field-effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent contamination to device itself and a production unit from a high-permittivity material with a thermal process by increasing gate capacitance without augmenting parasitic capacitance between a gate electrode and a diffusion layer, inhibiting a short channel effect and forming a gate oxide film consisting of the high-permittivity material and the gate electrode after the formation of the diffusion layer in a recessed type transistor. CONSTITUTION:In a transistor with diffusion layers 2 projected to sections upper than a silicon substrate 1, insulating films 4 composed of SiO2 are formed on the side faces of a gate insulating film made up of a high-permittivity material 3 and a gate electrode in the lower section of the gate electrode formed by a tungsten layer 5. The structure is manufactured by burying the insulating film and the gate electrode after the shape of a recessed type is formed. The structure is manufactured by using a self-alignment process employing a dummy pattern, the formation of the diffusion layer by a thermal diffusion from BSG or PSG, etc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor which constitutes a semiconductor integrated circuit which requires high speed and high integration such as a logic circuit and a memory, and a manufacturing method thereof.

[0002]

Bruce et al. Have reported that the short channel effect that occurs in a fine field-effect transistor can be suppressed by making the junction of a diffusion layer shallow.
EE Electron Device Letter, Volume 1, Page 1 (Brews, IEEEEEDL Vol. 1 P.
It is shown in 1). In addition, Omura et al.
In the I-transistor, the SOI layer can be made thin to form a shallow diffusion layer junction and the short channel effect can be suppressed. 1992 IMD Technical Digest, p. 615 (Omura, 199).
2 IEDM Tech. Dig. P. 615). In FIG. 19, 91 is a gate electrode, 92 is a gate oxide film, 93 is an SOI layer, 94 is a buried oxide film, 95 is a silicon substrate, 96 is a channel region, and 97 is a diffusion layer.

A method of using a high dielectric constant material for a gate insulating film of a field effect transistor is disclosed by Kuwata et al. In Japanese Patent Laid-Open No. 61-67964 (FIG. 20) and by Kato et al. In Japanese Patent Laid-Open No. 2-273934. (FIG. 21) and Japanese Patent Application Laid-Open No. 3-46267 (FIG. 22) by Iida et al.

In FIG. 20, 101 is a semiconductor layer,
102 is a source electrode, 103 is a drain electrode, 104 is a barium tin titanate layer, 105 is a dielectric layer, 106 is a barium tantalate layer, 107 is a gate electrode, and 108 is an insulating substrate.

Further, in FIG. 21, 111 is a silicon substrate, 112 is a field oxide film, 113 is a diffusion layer, and 11
4 is a tantalum silicide film, 115 is a SiO ₂ film, 11
6 is a Ta ₂ O ₅ film, 117 is a gate electrode, 118 is a second
SiO ₂ films 119 are wiring electrodes.

In FIG. 22, 121 is a silicon substrate, 122 is a diffusion layer, 123 is a SiO ₂ film, and 124 is T.
The a ₂ O ₅ film and 125 are aluminum layers.

A field effect transistor having a concave shape is shown by Takeda in Hot Carrier Effect (Nikkei McGraw-Hill Company, 1987), page 137.
The manufacturing method is shown in FIGS. In this method, a diffusion layer is provided on a semiconductor substrate, a diffusion layer in a region where a channel is formed is removed to form a concave shape, and then a gate insulating film and a gate electrode are embedded in a groove-shaped region.

23 to 25, 131 is a silicon substrate, 132 is a diffusion layer, 133 is a SiO ₂ film, 1
Reference numeral 34 is a channel region, 135 is a gate electrode, and 136 is a gate insulating film.

[0009]

The short channel effect that occurs with the miniaturization of field effect transistors can be suppressed by making the junction of the diffusion layer shallow, but it can also be suppressed by thinning the gate insulating film. It must be made. For simplicity, SOIMOSF using point charge
The model of ET is shown in FIG. In this model, SOIMOSFE at the limit where the junction depth of the diffusion layer is zero
When the surface potential φ of T is calculated,

[0010]

[Equation 1]

[0011] Where Vd is the drain voltage, T
_OX is the gate oxide film thickness, and x is the distance from the drain.
From this equation, the surface potential takes a positive value depending on the drain electric field even if the junction is made as thin as possible. That is,
Even if the junction depth of the diffusion layer is zero, the surface potential is affected by the drain electric field. That is, even if the junction is made extremely thin, the short channel effect due to the drain electric field cannot be completely removed. Therefore, it is necessary to reduce the gate oxide film thickness which is another method for suppressing the short channel effect.

However, if the gate oxide film thickness is reduced, the withstand voltage is reduced. In order to prevent this, a high dielectric constant material is used for the gate insulating film to increase the ratio of the dielectric constant of the gate insulating film to the dielectric constant of the semiconductor layer forming the semiconductor substrate or the SOI substrate and the buried insulating film layer, and equivalently, A method of reducing the gate oxide film thickness is effective.

Many of the high dielectric constant materials are metal oxides,
Considering the contamination of the device itself and the process equipment by the metal element, it is desirable to avoid ion implantation through the gate insulating film when forming the diffusion layer or heat treatment after forming the gate insulating film. Therefore, it is desirable to form the gate insulating film and the gate electrode after forming the diffusion layer. In this case, since the diffusion layer cannot be self-aligned by implanting ions using the gate electrode as a mask, a self-alignment process to replace this is necessary.

In the concave type transistor shown in FIGS. 23 to 25, in the manufacturing method thereof, the diffusion layer 132 is used.
After being prepared in advance, the insulating film 136 and the gate electrode 135 are embedded in the channel region 134 sandwiched by the diffusion layers 132. Therefore, after forming the diffusion layer, self-aligningly,
A gate insulating film and a gate electrode can be formed. However, when a high dielectric constant material is used for the gate insulating film, as shown in FIG.
The parasitic capacitance between the gate electrode and the diffusion layer indicated by Cox1 in FIG. 7 increases, and the high speed of the circuit is lost. In particular, in the case of the SOI structure shown in FIG. 27, since the capacitance between the diffusion layer and the substrate is small, the parasitic capacitance such as Cox1 cannot be ignored compared to other parasitic capacitances.

In FIG. 27, 171 is a buried oxide film, 172 is a diffusion layer, 173 is a SiO ₂ film, 174 is an offset region, 175 is a gate electrode, and 176 is a channel region.

In FIG. 27, the insulating film thickness Tox on the side wall portion
When 2 is larger than the gate insulating film thickness Tox1, the parasitic capacitance Cox1 can be reduced. However, at the same time, the capacitance Cox2 between the gate and the offset region decreases, and the parasitic resistance in the offset region 174 increases.

Further, if the diffusion layer is extended below the insulating film on the side wall, the parasitic resistance of the offset region 174 is reduced, but both diffusion layers come close to each other, which is disadvantageous to the short channel effect.

An object of the present invention is to increase the gate capacitance and suppress the short channel effect in a recessed transistor without increasing the parasitic capacitance between the gate electrode and the diffusion layer.

Another object of the present invention is to form a gate oxide film and a gate electrode made of a high-dielectric constant material after forming a diffusion layer so that the high-dielectric-constant material can be transferred to the device itself and a manufacturing apparatus accompanying a thermal process. It is to prevent pollution.

[0020]

According to a first aspect of the present invention, in a field effect transistor in which a diffusion layer projects above a substrate, a substrate below a gate electrode is provided with a first insulating film made of a high dielectric constant material. And the first insulating film extends toward the diffusion layer side from the end of the gate electrode, the side surface of the gate electrode and the diffusion layer face each other through the second insulating film, and the second insulating film is Is it made of a material having a lower dielectric constant than the first insulating film?
Alternatively, it is characterized by being formed of a composite film including a film made of a material having a dielectric constant lower than that of the first insulating film.

According to a second aspect of the present invention, in a field effect transistor in which a diffusion layer projects above a substrate, a lower portion of a gate electrode is provided with a first insulating film made of a composite film of a high dielectric constant material and a low dielectric constant material. The first insulating film extends toward the diffusion layer side from the end of the gate electrode, the side surface of the gate electrode and the diffusion layer face each other through the second insulating film, and
Is characterized in that it is made of a low dielectric constant material or a composite film in which the film thickness of the low dielectric constant material is larger than that of the first insulating film.

According to a third invention, in the first or second invention, the first insulating film does not extend to the diffusion layer side from the end of the gate electrode, but the first insulating film does not extend to the diffusion layer or the LDD region. Characterized by being in contact.

In the method for manufacturing a field effect transistor according to the fourth aspect of the present invention, after forming a first insulating film made of a material having a low dielectric constant on a sidewall portion of a semiconductor substrate having a concave shape,
The semiconductor substrate is isotropically etched using the first insulating film as a mask, and a gate insulating film made of a high dielectric constant material or a composite film of a high dielectric constant material and a low dielectric constant material is formed on the surface of the resulting depression. Then, subsequently, a gate electrode is formed by embedding a conductive material in the upper part of the gate insulating film.

In the method of manufacturing a field effect transistor according to the fifth aspect of the present invention, an insulating film made of a low dielectric constant material is isotropically deposited on the surface of a concave semiconductor substrate having side walls with an inclination and then anisotropically deposited. Etch back to expose the bottom semiconductor substrate, then form a gate insulating film consisting of a high-dielectric constant material or a composite film of high-dielectric constant material and low-dielectric constant material on the surface. It is characterized in that a gate electrode is formed by embedding a conductive material in the upper part.

In the method for manufacturing a field effect transistor according to the sixth aspect of the present invention, a dummy pattern is provided on a semiconductor substrate, and ion implantation or impurity diffusion is performed using the dummy pattern as a mask, so that both the LDD region and the diffusion layer or After providing only the diffusion layer, and then covering the diffusion layer, the LDD region, and the dummy pattern by depositing the spacer material, an opening is provided in the spacer material above the dummy pattern, and an etchant is introduced from the opening to form the dummy pattern. The gate electrode is formed by selectively removing the substrate to expose the substrate, forming a gate insulating film on the surface of the substrate, and filling the opening obtained by removing the dummy pattern with a conductive material. To do.

According to a seventh aspect of the present invention, there is provided a method of manufacturing a field effect transistor, wherein a BSG, BPSG or PS is formed on a semiconductor substrate.
After G is deposited, these are removed in the region forming the channel to provide a slit-shaped region, and then BS
Impurities are diffused from G, BPSG or PSG to a semiconductor substrate to form a diffusion layer, a gate insulating film is formed on the substrate surface in the slit-shaped region, and a conductive material is embedded in the slit-shaped region to form a gate electrode. It is characterized by forming.

[0027]

When the dielectric constant of the gate insulating film is increased, the capacitance C2 between the diffusion layer and the substrate surface shown in FIG.
The ratio of the capacitance C1 between the gate electrodes becomes large. for that reason,
As a result of the capacitance division, the potential difference between the diffusion layer and the substrate surface is reduced. This means that the influence of the drain electric field on the surface of the channel region is reduced, and the short channel effect is suppressed.

In FIG. 29, 191 is a silicon substrate, 192 is a channel region, 193 is a diffusion layer, 194 is an insulating film, 195 is a gate electrode, and 196 is capacitors C1 and 19.
Reference numeral 7 is the capacity C2.

In the SOI transistor shown in FIG. 30, the capacitance C2 is expressed by the capacitance C21 of the buried oxide film and the capacitance C20 of the semiconductor layer in series. The effect of increasing the dielectric constant of the gate insulating film is shown. Can be considered similarly.

In FIG. 30, 198 is a buried oxide film, 199 is a semiconductor layer, 200 is capacitors C20, 201.
Is the capacity C21.

In the first, second, and third inventions, an insulating film made of a material having a large dielectric constant is provided below and sideways of the gate electrode, and an insulating film made of a material having a low dielectric constant is provided on the side surface of the gate electrode. Accordingly, it is possible to simultaneously satisfy the suppression of the short channel effect due to the increase of the capacitance Cox3 in FIG. 28, the suppression of the parasitic resistance of the offset portion due to the increase of the capacitance Cox2, and the suppression of the parasitic capacitance due to the reduction of the capacitance Cox1. In FIG. 28, reference numeral 177 indicates a high dielectric constant material.

In the manufacturing method according to the fourth, fifth, sixth and seventh inventions, since the gate electrode and the gate insulating film are formed after the diffusion layer is formed, the device itself is formed by the metal element contained in the high dielectric constant material. In addition, it is possible to prevent contamination of the process equipment and form the diffusion layer, the gate insulating film, and the gate electrode in a self-aligned manner.

In the manufacturing method according to the fourth aspect of the present invention, the high dielectric constant material is embedded in the surface of the depression obtained by isotropically etching the semiconductor substrate below the low dielectric constant material on the side wall of the diffusion layer. Then, a gate electrode is formed. Thus, two types of insulating materials having different dielectric constants can be arranged in a self-aligning manner so as to satisfy the structures of the first, second, and third inventions.

In the manufacturing method of the fifth invention, a gate insulating film and a gate electrode are formed after an insulating film made of a wedge-shaped low dielectric constant material is formed on the sidewall of a concave semiconductor device having an inclined sidewall. To do. Thereby, two kinds of insulating materials having different dielectric constants can be arranged in a self-aligning manner so as to satisfy the structure of the third invention.

When the substrate is etched to form a concave structure after removing the dummy pattern using the manufacturing method of the sixth aspect of the invention, a diffusion layer is formed over the entire surface of the substrate as in the conventional example shown in FIGS. There is an advantage that the step difference can be reduced as compared with the case where the diffusion layer of the channel portion is removed after the formation and the concave structure is formed. This is because in the conventional example, the step is always thicker than the diffusion layer, whereas in the present invention, the step can be made smaller than the thickness of the diffusion layer.
In the conventional example, the recessed structure is formed by removing the diffusion layer once formed in the region where the channel is formed, whereas in the present invention, the diffusion layer is formed not only in the channel portion. This is because the formation of the concave structure is not affected by the step of removing the diffusion layer.

In the manufacturing method of the sixth aspect of the invention, when the substrate is not etched after the dummy pattern is removed, the protrusion of the concave structure becomes an insulating film as shown in FIG. 12, so it corresponds to Cox1 in FIG. At the same time that the parasitic capacitance can be significantly reduced, the gate oxide film and the gate electrode can be formed in a self-aligned manner after the diffusion layer is formed, as in the conventional example shown in FIGS.

In the manufacturing method of the seventh invention, BS
Since the diffusion layer is formed by diffusing impurities from G, BPSG, or PSG, the protrusion of the concave structure serves as an insulating film as shown in FIG. 15, so that the parasitic capacitance corresponding to Cox1 in FIG. 27 can be significantly reduced. At the same time, FIGS.
Similar to the conventional example, after forming the diffusion layer, the gate oxide film and the gate electrode can be formed in a self-aligned manner.

[0038]

【Example】

(Embodiment 1) An embodiment according to the first invention is shown in FIG.
An n ⁺ diffusion layer 2 having a height of 0.1 μm is provided above the surface of the p-type silicon substrate 1 with a channel region 6 having a width of 0.2 μm interposed therebetween. A gate insulating film made of the high dielectric constant material 3 is provided on the surface of the channel region 6 and in the region sandwiched between both diffusion layers 2. Here, the high dielectric constant material is, for example, Ta ₂ O ₅ , and the thickness thereof is 300 Å. Above the high dielectric constant material 3, SiO ₂ having a thickness of 300 angstrom is formed so as to contact the side wall of the diffusion layer _2.
A membrane 4 is provided. Further, a SiO ₂ film 4 having a thickness of 300 Å is provided on the diffusion layer 2. A tungsten layer 5 is embedded in a slit-shaped region surrounded by the high dielectric constant material 3 and the SiO ₂ film 4 to serve as a gate electrode. However, Si
The thickness of the O ₂ film 4 may be different on the side wall and the upper part of the diffusion layer 2.

(Embodiment 2) An embodiment according to the second invention is shown in FIG. In this example, the high dielectric constant material in FIG. 1 is replaced with a 20 Å thick second SiO 2 layer.
₂ Film 7 and high dielectric constant material with a thickness of 280 Å 3
And replace it with a composite membrane.

In this structure, a composite film of a high dielectric constant material and a low dielectric constant material is used under the gate electrode, and the quality of the gate insulating film and the channel interface can be kept the same as before.

(Embodiment 3) An embodiment in which the structure of the first invention is manufactured by the manufacturing method of the fourth invention or the manufacturing method of the sixth invention will be described with reference to FIGS.

As shown in FIG. 3, p-type silicon substrate 11
First SiO ₂ film 1 with a thickness of 100 angstrom
After forming 3 by thermal oxidation, the Si ₃ N ₄ film 14 having a thickness of 2000 angstrom is patterned by RIE to have a width of 0.2 μm to form a dummy pattern. Subsequently, a second SiO ₂ film 15 having a thickness of 1000 Å is deposited on the entire surface by CVD, and then anisotropic etching is performed to form a second SiO ₂ film 1 on the dummy pattern.
5 to form side walls. Dummy pattern and SiO ₂
Sidewall was 5 × 10 ¹⁵ cm ^-2 ions implanted arsenic mask 70 keV, performed 10 minutes heat treatment at 800 ° C., the diffusion layer 1
Form 2.

Next, as shown in FIG. 4, a third SiO ₂ film 16 having a thickness of 1000 Å is deposited on the entire surface by CVD as a spacer, and the third SiO ₂ film 16 on the dummy pattern is formed.
The SiO ₂ film 16 is removed by photolithography and RIE.

Next, as shown in FIG. 5, S was added using phosphoric acid.
After etching and removing the i ₃ N ₄ film 14, the first S
The iO ₂ film 13 is removed by etching with 1:30 diluted hydrofluoric acid. Second SiO ₂ film 15, third SiO ₂
The silicon substrate 11 is anisotropically etched by RIE by 500 Å using the film 16 as a mask. Then, a fourth SiO ₂ film 17 having a thickness of 200 Å is formed on the C
Deposited by VD, heat treated at 800 ° C for 10 minutes,
The SiO ₂ film 17 is anisotropically etched by RIE,
A side wall of the SiO ₂ film 17 is formed.

Next, as shown in FIG. 6, the silicon substrate 11 is isotropically etched with hydrochloric acid gas or chlorine gas using the third SiO ₂ film 16 and the fourth SiO ₂ film 17 as a mask, The diffusion layer 12 is exposed below the SiO ₂ film 17. Next, a Ta ₂ O ₅ film 18 is formed by MOCVD to 3
00 Å is deposited.

Finally, as shown in FIG. 7, Ta ₂ O ₅ film 1
A tungsten layer 19 is embedded in the slit surrounded by 8 and patterned to form a gate electrode.

(Embodiment 4) An embodiment in which the structure of the first invention is manufactured by the manufacturing method of the fifth invention will be described with reference to FIGS.

First, as shown in FIG. 8, a silicon substrate 21 is used.
After arsenic is ion-implanted on the surface of the substrate at 70 keV at 5 × 10 ¹⁵ cm ^{−2 and} heat treatment is performed at 850 ° C. for 10 minutes to form a diffusion layer, a first SiO ₂ film 23 is deposited to 1000 angstrom by CVD. Next, the SiO ₂ film 23 has a width of 0.3.
A slit of μm is provided by photolithography and RIE.

Next, as shown in FIG. 9, CF ₄ and CH ₃
The RIE is used to taper-diffuse the diffusion layer 22 with the first SiO ₂ film 23 as a mask. Then, a second SiO ₂ film 24 is deposited on the entire surface by CVD to 1000 angstroms, and anisotropic etching of 1000 angstroms is performed by RIE. Here, the second SiO ₂
The sidewalls of membrane 24 have a thickness of 1000 Angstroms at the top and a wedge-like thinness at the bottom.

Next, as shown in FIG. 10, sputtering, MO
A Ta ₂ O ₅ film 25 is deposited to 300 angstroms by CVD or the like, and a tungsten layer 26 is subsequently sputtered into the slit surrounded by the Ta ₂ O ₅ film 25 as a gate insulating film and patterned to form a gate electrode. Form.

(Embodiment 5) An embodiment according to the sixth invention is shown in FIGS.

First, as shown in FIG. 11, the first SiO 2 having a thickness of 100 angstrom is formed on the p-type silicon substrate 31.
_{After the second} film 33 is formed by thermal oxidation, a Si ₃ N ₄ film 35 having a thickness of 2000 Å is formed by RIE to a width of 0.2 μm.
Patterning is performed to form a dummy pattern. Subsequently, a second SiO ₂ film 34 having a thickness of 1000 Å is deposited on the entire surface by CVD, and anisotropic etching is performed subsequently to form a second SiO ₂ film on the dummy pattern.
₂ A side wall of the film 34 is formed. Dummy pattern and S
5 × 10 ¹⁵ c of arsenic at 70 keV using the iO ₂ sidewall as a mask
M ⁻² ions are implanted and heat treatment is performed at 800 ° C. for 10 minutes to form the diffusion layer 32.

[0053] Then, as shown in FIG. 12, a third SiO ₂ film 36 having a thickness of 1000 Å is deposited on the entire surface by CVD as a spacer, a photo of the third SiO ₂ film 36 of the dummy pattern upper lithography and RIE Then, the Si ₃ O ₄ film 35 is etched with phosphoric acid to remove the first SiO ₂ film 33 at a ratio of 1: 3.
It is removed by etching with 0 diluted hydrofluoric acid.

Finally, as shown in FIG. 13, a Ta ₂ O ₅ film 37 of 300 Å is deposited by MOCVD, a tungsten layer 38 is embedded in the slit surrounded by the Ta ₂ O ₅ film, and patterning is performed to form a gate electrode. Form.

(Embodiment 6) An embodiment according to the seventh invention is shown in FIGS.

As shown in FIG. 14, a silicon substrate 41,
SOI consisting of embedded SiO ₂ film 42 and SOI layer 43
1000 angstrom thick PSG film 44 on the substrate
Are deposited by CVD. Subsequently, the PSG film 44 has a width of 0.
A 2 μm slit is formed using photolithography and RIE.

Next, as shown in FIG.
A heat treatment is performed for a minute to diffuse phosphorus from the PSG film 44 to the SOI layer 43 to form a diffusion layer 47. The Ta ₂ O ₅ film 45 is sputtered with 300 Å or CV.
Then, the tungsten layer 46 is deposited by sputtering and then patterned.

(Embodiment 7) In the invention according to the second invention,
A case having an LDD structure and an SOI structure will be described with reference to FIG.

In the SOI substrate including the silicon substrate 51, the embedded SiO ₂ film (oxide film) 52, and the SOI layer 53, the diffusion layer 55 and the LDD region 54 are SOI.
The thickness of the layer 53 is as thick as 1000 angstrom, and the thickness of the SOI layer 53 in the channel region 56 is 100 Å.
Angstrom and thin. LDD region 54, diffusion layer 55
On top of the first 300 Å thick first SiO
_{2 The} film 59 is provided.

A Ta ₂ O ₅ film 57 having a thickness of 300 Å is provided on the channel region 56. A second SiO ₂ film 58 having a thickness of 300 Å is provided on the sidewalls of the LDD region 54 and the first SiO ₂ film 59. Second C
A tungsten layer 60 is embedded in a region on the slit surrounded by the VDSiO ₂ film 58 and the Ta ₂ O ₅ film 57 to form a gate electrode.

(Embodiment 8) An embodiment corresponding to the third invention and not corresponding to the first invention is shown in FIG. In the structure of FIG. 1, the Ta ₂ O ₅ film 75 extends from the end of the gate electrode (tungsten layer) 74 to the diffusion layer 72 side, but does not contact the diffusion layer 72. In the figure, 71 is a silicon substrate, 7
Reference numeral 3 is a SiO ₂ film.

(Embodiment 9) An embodiment corresponding to the first invention and not corresponding to the third invention is shown in FIG. The diffusion layer 82 has an inclination and is projected by 0.1 μm from the surface of the p-type silicon substrate 81 to the upper part. The SiO ₂ film 83 has a wedge shape that is thick at the upper portion and thin at the lower portion and overlaps the inclined side surface of the diffusion layer. A Ta ₂ O ₅ film 85 having a thickness of 200 Å is provided on the silicon substrate 81 sandwiched by the diffusion layers 82. The tungsten layer 84 is embedded as a gate electrode in the slit sandwiched by the SiO ₂ film 83. In this structure, a gate insulating film 85 made of a high dielectric constant material is in contact with the diffusion layer 82, and Si is provided between the upper portion of the diffusion layer 82 and the gate electrode 84.
Although the O ₂ film 83 exists, the Ta ₂ O ₅ film 85 is formed from the end of the gate electrode formed by the tungsten layer 84.
It does not extend to the diffusion layer side.

Although the respective embodiments have been described above, these embodiments are merely examples, and the shapes, materials, use processes, dimensions,
The combination of each invention or the combination of other structures and manufacturing methods is not limited to those in these examples.

Although the n-channel transistor is described in the above embodiments, a p-channel transistor may be used. The transistor may be formed on either a bulk substrate or an SOI substrate. Further, various channel ion implantations for realizing enhancement type or depletion type transistors may be performed. In the embodiments, the region used as the diffusion layer may include a structure such as an LDD region.

The gate electrode may be made of metal silicide, polysilicon or the like, instead of metal. The gate electrode is not limited to the T-shape that spreads horizontally at the upper portion, but may be, for example, a shape that is completely buried in the slit of the above-described embodiment.

As the high dielectric constant material, a material other than Ta ₂ O ₅ may be used. Further, the high dielectric constant material and the low dielectric constant material in the claims may be in a relationship that this condition is relatively satisfied. The high dielectric constant material is not limited to the metal oxide, and when SiO ₂ is selected as the low dielectric constant material, Si ₃ N ₄ or the like having a higher dielectric constant may be used.

Further, the structures of the first, second, and third inventions may be arranged horizontally on the substrate or upside down.

[0068]

As described above, the present invention can suppress the short channel effect by using a high dielectric constant material for the gate insulating film.

Further, the capacitance between the gate electrode and the diffusion layer can be reduced without increasing the parasitic resistance.

Further, by forming the gate oxide film and the gate electrode after forming the diffusion layer, it is possible to prevent the high dielectric constant material from contaminating the device itself and the manufacturing apparatus due to the thermal process.

Therefore, a transistor having a small parasitic capacitance and a small parasitic resistance and a short channel length can be formed, which is effective for high integration and high speed of LSI.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a first embodiment.

FIG. 2 is a diagram illustrating a second embodiment.

FIG. 3 is a diagram illustrating a third embodiment.

FIG. 4 is a diagram illustrating a third embodiment.

FIG. 5 is a diagram illustrating a third embodiment.

FIG. 6 is a diagram illustrating a third embodiment.

FIG. 7 is a diagram illustrating a third embodiment.

FIG. 8 is a diagram illustrating a fourth embodiment.

FIG. 9 is a diagram illustrating a fourth embodiment.

FIG. 10 is a diagram illustrating a fourth embodiment.

FIG. 11 is a diagram illustrating a fifth embodiment.

FIG. 12 is a diagram illustrating a fifth embodiment.

FIG. 13 is a diagram illustrating a fifth embodiment.

FIG. 14 is a diagram illustrating a sixth embodiment.

FIG. 15 is a diagram illustrating a sixth embodiment.

FIG. 16 is a diagram illustrating a seventh embodiment.

FIG. 17 is a diagram illustrating an eighth embodiment.

FIG. 18 is a diagram illustrating a ninth embodiment.

FIG. 19 is a diagram illustrating a conventional example.

FIG. 20 is a diagram illustrating a conventional example.

FIG. 21 is a diagram illustrating a conventional example.

FIG. 22 is a diagram illustrating a conventional example.

FIG. 23 is a diagram illustrating a conventional example.

FIG. 24 is a diagram illustrating a conventional example.

FIG. 25 is a diagram illustrating a conventional example.

FIG. 26 is a diagram illustrating a problem of the conventional technique.

FIG. 27 is a diagram for explaining the problems of the conventional technology.

FIG. 28 is a diagram illustrating an effect of the invention.

FIG. 29 is a diagram illustrating an effect of the invention.

FIG. 30 is a diagram illustrating an effect of the invention.

[Explanation of symbols]

1, 11, 21, 31, 41, 51, 71, 81, 9
5, 111, 121, 131, 191 Silicon substrate 43, 53, 93 SOI layer 101, 199 Semiconductor layer 6, 56, 96, 134, 176, 192 Channel region 54 LDD region 174 Offset region 2, 12, 22, 32, 47, 55, 72, 82, 9
7, 113, 122, 132, 172, 193 Diffusion layer 102 Source electrode 103 Drain electrode 4, 73, 83, 115, 123, 133, 173 S
iO ₂ film 13,23,33,59 first SiO ₂ film 7,15,24,34,58,118 second SiO ₂
Film 16,36 Third SiO ₂ film 17 Fourth SiO ₂ film 44 PSG film 14,35 Si ₃ N ₄ film 92 Gate oxide film 112 Field oxide film 105 Dielectric layer 3,177 High dielectric constant material 18,25 , 37, 45, 57, 75, 85, 116,
124 Ta ₂ O ₅ film 104 Barium tin titanate layer 106 Barium tantalate layer 194 Insulating film 108 Insulating substrate 42, 52, 94, 171, 198 Buried oxide film 5, 19, 26, 38, 46, 60, 74, 84 Tungsten layer 114 Tantalum silicide film 125 Aluminum layer 91, 107, 117, 135, 175, 195 Gate electrode 119 Wiring electrode 136 Gate insulating film 196 Capacitance C1 197 Capacitance C2 200 Capacitance C20 201 Capacitance C21

Claims (7)

[Claims] 1. In a field effect transistor having a diffusion layer protruding above a substrate, a lower part of a gate electrode faces a substrate via a first insulating film made of a high dielectric constant material, and a first insulating film. Extends toward the diffusion layer side from the end of the gate electrode, the side surface of the gate electrode and the diffusion layer face each other through the second insulating film, and the second insulating film has a dielectric constant lower than that of the first insulating film. A field-effect transistor, which is made of a low material or a composite film including a film made of a material having a dielectric constant lower than that of the first insulating film. 2. In a field effect transistor in which a diffusion layer projects above a substrate, the lower part of the gate electrode is opposed to the substrate via a first insulating film made of a composite film of a high dielectric constant material and a low dielectric constant material. In addition, the first insulating film extends to the diffusion layer side from the end of the gate electrode, the side surface of the gate electrode and the diffusion layer face each other through the second insulating film, and the second insulating film has a low dielectric constant. A field effect transistor, which is made of a high-permittivity material or a composite film in which the film thickness of the low-dielectric constant material is larger than that of the first insulating film. 3. The field-effect transistor according to claim 1, wherein the first insulating film does not extend to the diffusion layer side from the end of the gate electrode, but the first insulating film does not extend to the diffusion layer or the LDD region. A field effect transistor characterized by being in contact with each other. 4. A sidewall of a semiconductor substrate having a concave shape,
After forming the first insulating film made of a material having a low dielectric constant, the semiconductor substrate is isotropically etched using the first insulating film as a mask, and a high dielectric constant material or a high dielectric constant is formed on the surface of the resulting depression. Of a field effect transistor characterized by forming a gate insulating film made of a composite film of a dielectric material and a low dielectric constant material, and then forming a gate electrode by embedding a conductive material on the upper part of the gate insulating film. Method. 5. An insulating film made of a low dielectric constant material isotropically deposited on the surface of a concave type semiconductor substrate having a sloped side wall, and anisotropic etching back is performed to expose the bottom semiconductor substrate. After that, a gate insulating film made of a high dielectric constant material or a composite film of a high dielectric constant material and a low dielectric constant material is formed on the surface, and then a gate electrode is formed by embedding a conductive material on the gate insulating film. A method of manufacturing a field effect transistor, which is characterized by being formed. 6. A dummy pattern is provided on a semiconductor substrate, and ion implantation or impurity diffusion is performed using this dummy pattern as a mask to provide both the LDD region and the diffusion layer or only the diffusion layer, and then the diffusion layer and the LDD. After covering the area and the dummy pattern with the deposition of the spacer material,
An opening is provided in the spacer material above the dummy pattern, the dummy pattern is selectively removed by introducing an etchant from the opening to expose the substrate, a gate insulating film is formed on the surface, and the dummy pattern is removed. A method of manufacturing a field effect transistor, comprising forming a gate electrode by embedding a conductive material in the obtained opening. 7. BSG, BPSG or P on a semiconductor substrate
After depositing SG, these are removed in the region forming the channel to provide a slit-shaped region, and then BS is formed.
Impurities are diffused from G, BPSG or PSG to a semiconductor substrate to form a diffusion layer, a gate insulating film is formed on the substrate surface in the slit-shaped region, and a conductive material is embedded in the slit-shaped region to form a gate electrode. A method of manufacturing a field effect transistor, which is characterized by being formed.