JPH0799496B2 - Floating point mantissa digit matching circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floating point mantissa digit alignment circuit for performing mantissa digit alignment required before addition and subtraction of floating point data.

2. Description of the Related Art A conventional floating point mantissa digit matching circuit is disclosed as one of the constituent elements of the invention in, for example, Japanese Patent Laid-Open No. 60-263230. FIG. 4 shows only the floating point mantissa digit aligning circuit extracted from the embodiment of the present invention. 1 and 2 are input registers that hold floating-point data, and 3 is an exponent comparison circuit that outputs the magnitude relationship between the exponents of the floating-point data held in the input registers 1 and 2 and the absolute value of the difference between them. , 4,5 are registers for holding the output of the exponent comparison circuit 3, 6 is a mantissa selector for selecting one mantissa of the floating point data held in the registers 1, 2 by the output of the register 4, 7 Is a digit alignment right shifter for shifting the output of the mantissa selector 6 to the right according to the output of the register 5.

In the conventional floating-point digit mantissa part matching circuit configured as above, the exponent parts of the floating-point data held in the input registers 1 and 2 are compared by the exponent part comparison circuit 3, and the output of the register 4 is compared. The mantissa part of the floating-point data having the smaller exponent part is taken out by the mantissa part selector 6 in the magnitude relationship judgment result shown by and the digit shift right shift is performed by the absolute value of the exponent difference indicated by the output of the register 5. Do.

Problems to be Solved by the Invention However, in the above configuration, the exponent comparison circuit 3
The exponent difference calculated in step 1 needs to be an absolute value, and the exponent part comparison circuit 3 cannot be configured by a simple subtractor, so that the circuit scale becomes large. Further, since the absolute value calculation is required, there is a problem that the shift number instruction data given to the digit alignment right shifter 7 cannot be supplied at high speed.

In view of this point, the present invention has an object to provide a floating-point mantissa digit aligning circuit which has a simple exponential part comparing circuit and performs mantissa digit aligning at high speed.

Means for Solving the Problems The present invention provides first and second floating-point data composed of an n-bit exponent part and a mantissa part, and the exponent part of the first floating-point data to the second floating-point data. A subtracter that subtracts the exponent part of floating-point data and finds the difference by a two's complement system; and a mantissa part of the second floating-point data is "1" when the most significant bit of the subtractor output is "0". When ", a multiplexer that outputs the mantissa part of the first floating-point data, a right 1-bit shifter that shifts right 1 bit when the most significant bit of the subtractor output is" 1 ", and a subordinate to the right 1-bit shifter Connected and shifted right 2 ^k bits {k
= 0 to (n-1)} n stages of right 2 ^k bit shifts, and when the most significant bit of the subtractor output is "0", the subtractor output bit having a weight of 2 ^k is set to the right 2 the control input of the ^k bit shifter, and a control unit to control the input of the subtractor output bit inversion to the right 2 ^k bit shifter having a weight of 2 ^k when the most significant bit is "1" of the subtraction output This is a floating point mantissa digit matching circuit provided.

With the above-described configuration, the present invention subtracts the exponent part of the second floating-point data from the exponent part of the first floating-point data by the subtracter, and when the most significant bit of the subtraction result is "0", The mantissa part of the second floating point data is shifted by the right 2 ^k- bit shifter according to the output bits of the subtractor,
When the most significant bit of the subtraction result is "1", the mantissa part of the first floating-point data is shifted right 1 bit by the right 1-bit shifter, and the right 2 bit is shifted according to the bit obtained by inverting the output bit of the subtracter. Shift with a ^k- bit shifter to align mantissa digits.

Practical Example FIG. 1 shows the configuration of a floating point mantissa digit matching circuit in an embodiment of the present invention. In Figure 1
Input registers 10 and 11 hold floating-point data. Also, consider the format of floating-point data as shown in FIG. That is, the exponent part e is represented by 2's complement, the mantissa part f is represented by an absolute value, and the sign is represented by the sign bit s. As a whole, the number of (−1) ^s · 2 ^e · f is represented. However, it is not necessary to make any changes to the configuration of the present invention even if the expression method of the exponent part is biased. Further, for simplification of description, the exponent part e has 3 bits. Therefore, the 3 bits of the exponent part e are
Taking the values shown in Table 1, the numbers from ± 2 ⁻⁴ · f to ± 2 ³ · f and 0 can be expressed.

12 in FIG. 1 subtracts the exponent part e ₂ in the floating point data held in the input register 11 from the exponent part e ₁ in the floating point data held in the input register 10 A subtracter indicated by 2's complement, 13 indicates the mantissa part f ₁ in the floating point data held in the input register 10 when the most significant bit d ₃ of the subtractor 12 is “1”. Sometimes it is a multiplexer that selects the mantissa part f ₂ in the floating point data held in the input register 11. 14 is
When the most significant bit d ₃ of the subtractor 12 is “1”, the multiplexer
It is a right 1-bit shifter that shifts the output of 13 right 1-bit. Reference numeral 15 is a right 1-bit shifter for performing a 1-bit shift to the right, 16 is a right 2-bit shifter for performing a 2-bit shift to the right, and 17 is a right 4-bit shifter for performing a 4-bit shift to the right. Reference numeral 18 denotes a control unit for controlling the shifters 15, 16 and 17 through the control lines R ₁ , R ₂ and R ₄ , the configuration of which is shown in FIG.

The operation of the floating point mantissa digit aligning circuit of the present embodiment having the above configuration will be described below.

First, the floating point data, N ₁ and N ₂ shown in the following equations are stored in the input registers 10 and 11, respectively.

N ₁ = (− 1) ^s1 · 2 ^e1 · f ₁ N ₁ = (− 1) ^s2 · 2 ^e2 · f ₂ Next, the subtracter 12 subtracts e1−e2. The subtraction result is a bit pattern (d ₃ , d ₂ , d ₁ , d ₀ ), Is expressed as The mantissa f ₁ or f ₂ is then | e ₁ −e ₂ |
Only the bits are shifted to the right by the shifters 14, 15, 16 and 17, and the mantissa digits are aligned. The control of the shifters 14, 15, 16, 17 differs depending on the state of d ₃ .

When d ₃ = 0 d ₃ = 0 indicates e1 ≧ e2. Therefore, the multiplexer 13 selects the mantissa part f ₂ of the floating point data in the register 11. Also, the number of shifts required for digit alignment is e1−e2
Is Given in. Therefore, the shifters 15, 16 and 17 may be operated with the bits d ₀ , d ₁ and d ₂ , respectively. Therefore, the third
The control circuit 18 in the figure outputs R ₁ = d ₀ , R ₂ = d ₁ , and R ₄ = d ₂ .

When d ₃ = 1 d ₃ = 1 means that e1 <e2. Therefore, the multiplexer 13 selects the mantissa part f ₁ of the floating point data in the register 10. The number of shifts required for digit alignment is e2-e1.
Is Becomes Therefore, it is sufficient to operate the shifters 15, 16 and 17, respectively, by inverting each bit of d ₀ , d ₁ and d ₂ . Therefore, the control circuit 18 in FIG. 3 outputs R ₁ = ₀ , R ₂ = ₁ and R ₄ = ₂ . Further, the constant term 1 in the above equation indicates that it is necessary to further shift the right 1 bit, so that the right 1 bit shifter 14 is operated by d ₃ bits which is "1".

As described above, according to the present embodiment, the shifter configured to realize the right shift by using the subtracter 12 for calculating the exponent part and the subtraction result represented by the complement of 2 as it is.
By providing 14,15,16,17 and a simple control unit for controlling these shifters, the shifter 14,15, 1
6 and 17 can be controlled, and mantissa digit alignment can be performed at high speed.

EFFECTS OF THE INVENTION As described above, according to the present invention, comparison of exponent parts can be realized by a simple subtractor, and moreover, the result of the subtraction is efficiently used to control the shifter, so that the high-speed mantissa part of floating-point data can be controlled. Digit alignment can be realized, and its practical effect is great.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a floating point mantissa digit alignment circuit according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing an example of a floating point data format, FIG. 3 is a circuit diagram of a shifter control unit, and FIG. The figure is a block diagram of a conventional floating point digit matching circuit. 12 ... Subtractor, 13 ... Multiplexer, 14,15,16,17 ...
… Shifter, 18… Control circuit.

Claims (1)

[Claims] 1. First and second floating-point data composed of an n-bit exponent part and a mantissa part, wherein the exponent part of the first floating-point data to the exponent part of the second floating-point data. And a subtractor for obtaining the difference between them by a two's complement system, and the mantissa part of the first and second floating point data as input, and the second bit when the most significant bit of the subtractor output is "0". A multiplexer that outputs the mantissa part of the floating-point data, when it is “1”, and a multiplexer that outputs the mantissa part of the first floating-point data, and right when the most significant bit of the subtractor output is “1”. A right 1-bit shifter for performing a 1-bit shift and a right connection to the right 1-bit shifter are cascade-connected, and right 2 ^k bit shifts {k = 0 to (n-
1)} and right 2 ^k bit shifter n stages performing, when the most significant bit is "0" of the subtraction output is the subtractor output bit having the weight of 2 ^k to a control input of the right 2 ^k-bit shifter , 2 ^k when the most significant bit of the subtractor output is "1"
The right 2 ^k inverts the subtracter output bit having the weight of
A floating point mantissa digit matching circuit, comprising: a control unit which is a control input of a bit shifter.