JPH08102496A - Method of manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: To eliminate a gate offset region on the side of a source and reduce on-resistance of a transistor by a method wherein a thin film region of a gate oxide film forming a heavily doped source and drain layer is self-alizningly formed for a gate electrode of a high breakdown strength MOS transistor. CONSTITUTION: A gate electrode 26B of a normal breakdown strength MOS transistor is formed on a thin gate oxide film 24 and a gate electrode 26A of a high breakdown strength MOS transistor is formed on a thick gate oxide film 22. With the use of these gate electrodes 26A, 26B as a mask, gate oxide films 24, 25 are dry-etched up to substantially 300Å or less. Thereafter,<31> P<+> ions are ion-implanted on one side of the gate electrode 26A, whereby a lightly doped drain layer 28 is formed. Next<75> As<+> ions are ion-implanted, whereby heavily doped source and drain layers 30, 31 of a normal breakdown strength MOS transistor and heavily doped source and drain layers 32, 33 of a high breakdown strength MOS transistor are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device in which a high breakdown voltage MOS transistor and a normal breakdown voltage MOS transistor are mixedly mounted on the same substrate.

[0002]

2. Description of the Related Art In an LCD driver IC, a high breakdown voltage MOS transistor and a normal breakdown voltage MOS transistor are formed on the same substrate, and a high power source (4
The circuit to which 0 V is supplied is composed of high voltage MOS transistors and uses a low power supply (3 V) such as a shift register.
It is generally practiced that a circuit supplied with the (degree) is normally composed of a withstand voltage MOS transistor.

However, since the two types of MOS transistors have different gate oxide film thicknesses, different ion species (phosphorus and arsenic) are used for the normal breakdown voltage MOS transistor and the high breakdown voltage MOS transistor when forming the source / drain layers. However, the ion implantation process for forming the source / drain layers cannot be shared.

Therefore, the applicant of the present application has filed a patent application for an invention relating to a method for manufacturing a semiconductor device in which the ion implantation steps for forming source / drain layers, which have conventionally been separately performed, are made common and the manufacturing steps are greatly reduced. (Japanese Patent Application No. 6-202
284). Hereinafter, a method of manufacturing such a semiconductor device will be described with reference to FIGS.

In FIG. 7, a LOCOS oxide film 2 is formed on a P-type Si substrate 1 by a selective oxidation method, and a thick gate oxide film 3 of about 1000 Å is formed by thermal oxidation in a region excluding the LOCOS oxide film 2. Next, in FIG. 8, the thick gate oxide film 3 in the normal breakdown voltage MOS transistor formation region and the thick gate oxide film 3 on the high concentration source / drain formation region of the high breakdown voltage MOS transistor are removed by etching. Then, in FIG. 9, thermal oxidation is performed again to form a thin gate oxide film 4A having a thickness of about 300Å on the normal breakdown voltage MOS transistor formation region, and a thin oxide film is formed on the high concentration source / drain formation region of the high breakdown voltage MOS transistor. 4B is formed. Since this thin oxide film 4B is formed in the same step as the thin gate oxide film 4A,
It has the same film thickness (about 300Å).

Next, in FIG. 10, gate electrodes 5A and 5B made of polysilicon or the like are formed on the thick gate oxide film 3 and the thin gate oxide film 4A. At this time, if the gate electrode 5A protrudes from the thick gate oxide film 3 and extends over the thin oxide film 4B due to the mask shift, the gate breakdown voltage deteriorates. Therefore, the gate electrode 5A has a certain distance L (about 1 micron) from the end of the thick gate oxide film 3.
Are separated and formed.

Then, a resist film 6 is normally formed on the region for forming the withstand voltage MOS transistor, and ³¹ P ⁺ ions are ion-implanted under the conditions of, for example, 5E12 / cm ² and 100 KeV, a predetermined thermal diffusion is performed, and an n ⁻ type is formed. The source layer 7 and the drain layer 8 are formed. Next, in FIG. 11, a resist film 9 having an opening is formed in the normal breakdown voltage MOS transistor formation region and the high concentration source / drain formation region of the high breakdown voltage MOS transistor, and ⁷⁵ As ⁺ ions, for example, 5E15 / cm ² are formed from the opening. , 80 KeV, and ion implantation is performed to simultaneously form the n ⁺ type source layer 10 and the drain layer 11 of the normal breakdown voltage MOS transistor and the high concentration source layer 12 and the drain layer 13 of the high breakdown voltage MOS transistor. In this step, since the thin oxide film 4B is formed on the high-concentration source / drain formation region of the high breakdown voltage MOS transistor, the ion range (Rp) is increased in order to form the source / drain layers 10 and 11 shallowly. Even if) is reduced, the ions can pass through the oxide film 24. As a result, the ion implantation steps for forming high-concentration source / drain layers, which have been separately performed conventionally, can be made common.

Next, in FIG. 12, an interlayer insulating film 14 such as a BPSG film is formed on the entire surface, and an Al electrode layer 15 contacting the n ⁺ type source / drain layers 10, 11, 12, 13 is formed. As a result, the normal breakdown voltage MOS transistor (the one on the left side in the figure) and the high breakdown voltage MOS transistor (the one on the right side in the figure) are completed. As described above, according to this embodiment, the thin gate oxide film 4A of the normal breakdown voltage MOS transistor and the oxide film 4 on the formation region of the high concentration source / drain layer of the high breakdown voltage MOS transistor are formed.
Since B and B are formed in the same oxidation step, the normal withstand voltage M
Even if ⁷⁵ As ⁺ ions are adopted as the ion species to form the source / drain layers 10 and 11 of the OS transistor shallow and the range (Rp) thereof is reduced, the ions can pass through the thin oxide film 44. As a result, the ion implantation steps for forming high-concentration source / drain layers, which have been separately performed conventionally, can be made common.

[0009]

By the way, in general, when a source of a high breakdown voltage MOS transistor is grounded and used, a high voltage is not applied to the source. Therefore, the source layer 7 of low concentration is originally provided. There is no need. That is, it is sufficient to provide the low-concentration drain layer 8 only on the drain side.

However, according to the above manufacturing method, as shown in FIG.
As shown in FIG. 0, in order to secure the gate breakdown voltage, the gate electrode 5A is separated from the end of the thick gate oxide film 3 by a constant distance L.
It was necessary to form them apart (about 1 micron). Moreover, when forming the high-concentration source layer 12, ⁷⁵ As ⁺
Since ions are used, they cannot pass through the thick gate oxide film 3. Therefore, it is necessary to form an unnecessarily low-concentration source layer 7, and a gate offset region F is also formed on the source side, which causes a problem that the on-resistance of the transistor increases accordingly. It was

[0011]

According to the present invention, in order to solve the above problems, as shown in FIG. 3, a gate electrode 26 of a normal voltage MOS transistor is formed on a thin gate oxide film 24.
B is formed on the thick gate oxide film 22 to form the gate electrode 26A of the high breakdown voltage MOS transistor, and the gate electrodes 26A and 26B are used as masks to form the gate oxide films 24 and 25.
Is dry-etched to approximately 300 Å or less, and then ³¹ P is formed on one side of the gate electrode 26A as shown in FIG.
⁺ By the ions are implanted to form the lightly doped drain layer 28, then, as shown in FIG. 5, ⁷⁵ As
By implanting ⁺ ions, the normal withstand voltage MOS
Transistor high concentration source / drain layers 30, 31
And the high-concentration source / drain layers 32 and 33 of the high breakdown voltage MOS transistor, and the high breakdown voltage M
The high-concentration drain layer 33 of the OS transistor was formed at a position offset from the gate electrode 26A.

[0012]

According to the present invention, the thinned region of the gate oxide film forming the high-concentration source / drain layer is formed in self-alignment with the gate electrode 26A of the high breakdown voltage MOS transistor. The gate offset region F can be eliminated. As a result, the on-resistance of the transistor can be reduced and the pattern size of the transistor can be reduced as compared with the related art.

[0013]

Next, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. FIG.
At the P-type Si substrate 21 by the selective oxidation method.
A COS oxide film 22 is formed, and a thick gate oxide film 23 of about 1000 Å is formed by thermal oxidation in a region excluding the LOCOS oxide film 22.

Next, in FIG. 2, the thick gate oxide film 21 in the normal voltage MOS transistor formation region is etched and removed. Thermal oxidation is performed again to form a thin gate oxide film 24 of about 300 Å on the normal voltage MOS transistor formation region. Next, referring to FIG. 3, a gate electrode material such as phosphorus-doped polysilicon is deposited on one surface of the substrate 21, and the gate electrode material is dry-etched by using the photoresist 25 as a mask to form the gate electrodes 26A and 26B. And then using the photoresist 25 and the gate electrodes 26A and 26B as a mask,
The thick gate oxide film 22 is dry-etched until the film thickness becomes approximately 300 Å or less, and a thinned region where a high concentration source / drain layer is to be formed is formed.

In this step, dry etching of polysilicon is performed by using, for example, He or HB as an etching gas.
r, Cl ₂ used, pressure 400mT, RF power 200W
Under the conditions of. For dry etching of the oxide film, CHF ₃ , CH ₄ and Ar are used as the etching gas, and the pressure is 1
It is performed under the conditions of 300 mT and RF power of 250 W. In addition,
When etching the thick gate oxide film 22, after removing the photoresist 25, the gate electrodes 26A and 26A are removed.
You may etch using only B as a mask. Further, when the thick gate oxide film 22 is etched to approximately 300 Å or less, the thin gate oxide film 24 is naturally removed entirely.

Next, as shown in FIG. 4, ³¹ P ⁺ ions are ion-implanted on one side of the gate electrode 26A under the conditions of, for example, 5E12 / cm ² and 100 KeV using the photoresist 27 as a mask, and the non-heat of about 1000 ° C. is applied. A low concentration drain layer 28 is formed by performing thermal diffusion in an oxidizing atmosphere. Next, as shown in FIG. 5, ⁷⁵ As ⁺ ions are ion-implanted by using the photoresist 29 covering the gate offset region on the drain side of the high withstand voltage MOS transistor as a mask, so that the high withstand voltage MOS transistor with high concentration is formed. The source / drain layers 30 and 31 and the high-concentration source / drain layer 3 of the high-voltage MOS transistor
2 and 33 are formed, and the high-concentration drain layer 33 of the high breakdown voltage MOS transistor is formed at a position offset from the gate electrode 26A. In this process, the oxide film on the region where the source / drain layer is formed is approximately 300 Å or less due to the above etching process, so even if ⁷⁵ As ⁺ ions pass through it sufficiently. can do. This allows
The high-concentration source / drain layers 30, 31, 32, and 33 can be formed by one-time ion implantation as in the conventional case.

Then, as shown in FIG. 6, the BPS is formed on the entire surface.
An Al insulating film 34 such as a G film is formed and is in contact with the n ⁺ type source / drain layers 30, 31, 32 and 33.
The electrode layer 35 is formed. As a result, the normal breakdown voltage MOS transistor (the one on the left side in the figure) and the high breakdown voltage MOS transistor
The transistor (the one on the right side in the figure) is completed.

As described above, according to the present invention, the thinned region of the gate oxide film forming the high-concentration source / drain layers is formed in self-alignment with the gate electrode 26A of the high breakdown voltage MOS transistor. Therefore, unlike the conventional case, it is not necessary to provide a low-concentration source layer on the source side, and the high-resistance gate offset region F on the source side can be eliminated. As a result, the on-resistance of the transistor can be reduced and the pattern size of the transistor can be reduced as compared with the related art.

Although the present embodiment has been described by taking an N-channel MOS transistor as an example, the present invention is not limited to this and can be applied to a P-channel MOS transistor and further to a CMOS structure. Is clear. When applied to a P-channel MOS transistor, boron ( ¹¹ B ⁺ ) is used as an ion species for forming a low-concentration drain layer, and a high-concentration source / drain layer is formed. For this, boron difluoride ( ⁴⁹ BF2 ⁺ ) can be used.

[0020]

As described above, according to the present invention,
In a method of manufacturing a semiconductor device in which a normal withstand voltage MOS transistor and a high withstand voltage MOS transistor having a high withstand voltage structure only on the drain side are mounted together, a thinned region of a thick gate oxide film 23 for forming high concentration source / drain layers 32, 33. Are formed in a self-aligned manner with the gate electrode 26A of the high breakdown voltage MOS transistor.
It is possible to form the high-concentration source layer 32 in a self-aligned manner with respect to the edge of, and the gate offset region F on the source side can be eliminated. As a result, the on-resistance of the transistor can be reduced and the pattern size of the transistor can be reduced as compared with the related art.

Further, in the thinned region of the thick gate oxide film 23, the high-concentration source of the normal breakdown voltage MOS transistor and the high breakdown voltage MOS transistor can be formed by one-time ion implantation.
The drain layers 30, 31, 32, and 33 can be formed, and there is an advantage that the manufacturing process can be shortened.

[Brief description of drawings]

FIG. 1 is a first sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a second cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a third cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a fourth sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a fifth cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 6 is a sixth cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 7 is a first cross-sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

FIG. 8 is a second cross-sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

FIG. 9 is a third cross-sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

FIG. 10 is a fourth cross-sectional view explaining the method for manufacturing the semiconductor device according to the conventional example.

FIG. 11 is a fifth cross-sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

FIG. 12 is a sixth cross-sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 29/78 301 S (72) Inventor Yuji Tsukada 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd.

Claims (2)

[Claims] 1. A normal voltage MOS transistor having a high concentration source / drain layer 29 and a thin gate oxide film 22, a low concentration drain layer 27, a high concentration source / drain layer 30, and a thick gate oxide film 22. High breakdown voltage MO
In a method of manufacturing a semiconductor device in which an S transistor is formed on the same semiconductor substrate 21, a selective oxide film 22 is formed on a semiconductor substrate 21 of one conductivity type, and a substrate other than a region where the selective oxide film 22 is formed is formed. 21
A step of forming a thick gate oxide film 23 on the upper surface, a step of removing the thick gate oxide film 22 on the normal breakdown voltage MOS transistor forming region, and a step of forming a thin gate oxide film 24 on the area where the thick gate oxide film 22 is removed. And a step of applying a gate electrode material to one surface of the substrate 21 and dry etching the gate electrode material using the photoresist 25 as a mask.
B, and then dry-etching the thick gate oxide film 22 using the photoresist 25 and the gate electrodes 26A and 26B as a mask until the film thickness becomes approximately 300 Å or less, and one side of the gate electrode 26A. A step of forming a low-concentration drain layer 28 by ion-implanting a first reverse-conductivity-type impurity, and a step of forming a low-concentration drain layer 28 by ion-implanting a second reverse-conductivity-type impurity. The drain layers 30 and 31 and the high concentration source / drain layers 32 and 33 of the high breakdown voltage MOS transistor are formed, and the high concentration drain layer 33 of the high breakdown voltage MOS transistor is formed.
And a step of forming the semiconductor device at a position offset from the gate electrode 26A. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the first opposite conductivity type impurity is phosphorus, and the second opposite conductivity type impurity is arsenic.