JPH08102744A - Exchange, exchange method, and network system - Google Patents

Abstract

PURPOSE: To select and connect a line provided with appropriate features by selecting a transmission enable line by the transmission destination identification information of a data frame based on the characteristics of the data of a hierarchy higher than a specified hierarchy. CONSTITUTION: When hit data are present in the data inputted to an address processor 102, a CPU 121 reads a hit segment address, adds '1', writes it in an address register AR, specifies a port address and sets connection to an output port in a switching element unit SEU 111. Then, a port to which loss priority display CLP correspond corresponding to the propriety of the cancellation of the data is selected. Then, the CPU 121 sets data transfer from the AP 102 to the SEU 111 in a DMAC 103 and transfers the data of the AP 102 to the SEU 111. At the time the AP 102 outputs the data of 32 bits of the OR of the value of a compound data register storing the PT and CLP of input data in lower four bits and the VPI and VCI of an output side line stored in a segment by 8 bits.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention receives a data frame assembled based on a communication protocol composed of a plurality of layers, and based on a destination address of a specific layer in the data frame, the data frame is received. The present invention relates to an exchange, an exchange method, and a network system for identifying a destination of a message.

[0002]

2. Description of the Related Art An exchange selects a line based on destination identification information. Here, the "destination identification information" includes, for example, the VPI and VC of the ATM header in the ATM network.
I, Ethernet type or DA (destination address) in data frame of IEEE802.3, TCP / IP
DEST (destination address) included in the IP header of
This corresponds to the ISDN number of the other party on the SDN line. A network system in which multiple routes are connected to the same destination has also been put into practical use. In such a network system, an exchange system has been put into practical use that selects a line that is not congested when some lines are congested.

The conventional multi-path lines that can be selected by the exchange are guaranteed to have sufficient security, communication speed, bandwidth (transmission capacity), and quality. Further, the fee charged to the user is constant regardless of which line is selected. In this application,
Such high security, communication speed, bandwidth (transmission capacity), quality, charges, etc. are called "features" of the line.

[0004]

In recent years, internetworking for connecting a plurality of networks to each other has been promoted. A data frame may be transmitted from a specific source to a specific destination via networks of many vendors. In the future, even when a data frame is transmitted from a specific transmission source to a specific transmission destination, it depends on which line of which vendor is used to transmit the data, that is, by the transmission route. It is considered that there may be cases where the security level, delay, charges, etc. of the communication differ. In this case, if the exchange arbitrarily selects the route of the line, high security of communication, delay, charge, etc. cannot be guaranteed.

On the other hand, a data frame transmitted to a one-dimensional network such as a moving image, voice, data transmission, etc., such as an ATM network, includes a data frame which does not require high reliability like a moving image and a data frame. Data frames that require high reliability such as electric transmission are mixed.
In addition, there are mixed data frames such as call data that are severe in data delay and data frames that are not severe in data delay such as data transmission. In this case, if high security, short delay time, etc. are guaranteed for all data frames, it is not possible to fully utilize a plurality of line paths. In addition, it may be uneconomical to select an expensive communication path more than necessary.

At the time of call setup, a call setup sequence that requires a required communication quality is also used. However, in the future, it is considered that lines with extremely diverse "features" will be connected to each other, so it will be difficult to select an appropriate communication line only by such a sequence that requires quality. .

Further, since it is necessary to select a line to which a received frame is to be sent at a high speed, it has been conventionally difficult to select an appropriate line each time a data frame is received.

[0008]

In order to achieve such an object, the invention according to claim 1 receives a data frame assembled based on a communication protocol composed of a plurality of layers, and An exchange that identifies a transmission destination of the data frame based on transmission destination identification information in a specific layer among the plurality of layers described in the data frame, and that is capable of transmitting to the transmission destination. Means for connecting the lines, and one line of the plurality of lines based on the data of the specific layer, which represents the characteristics of the data of the layer higher than the specific layer included in the data frame. And a selecting unit for selecting.

The invention according to claim 2 is the exchange according to claim 1, further comprising means for storing data representing characteristics of each of the plurality of lines, and the selecting means further includes the characteristics. One line is selected from the plurality of lines based on the data representing

The invention according to claim 3 is the exchange according to claim 1 or 2, wherein the data frame is an AT.
M cells, the specific layer is an ATM layer, the destination identification information is VPI and VCI, and the data of the specific layer is CLP.

According to a fourth aspect of the present invention, in the exchange according to the second or third aspect, the data representing the characteristic is data based on the level of security of each of the plurality of lines. And

The invention as defined in claim 5 is defined by claim 1 through claim 4.
The exchange according to any one of the items,
Means for storing position information indicating the position of the destination identification information in the data frame in advance, and means for selecting the identification information from the data string based on the position information,
Means for searching the destination of the data string using the selected identification information, and storing start position information indicating in advance what number of data in the data frame has been input. And a means for outputting a search start means for starting a search by the search means when the data indicated by the start position information is input, and a means for outputting information indicating the searched destination. It is characterized by having.

According to a sixth aspect of the present invention, a data frame assembled based on a communication protocol composed of a plurality of layers is received, and a specific one of the plurality of layers described in the data frame is received. A switching method applied to a switch for identifying a transmission destination of the data frame on the basis of transmission destination identification information in a hierarchy, wherein the exchange is connected with a plurality of lines capable of transmitting to the transmission destination. 1 of the plurality of lines based on the data of the specific layer, which represents the characteristic of the data of the layer higher than the specific layer included in the data frame.
The feature is that one line is selected.

The invention according to claim 7 is the exchange method according to claim 6, wherein data representing the characteristics of each of the plurality of lines is stored, and the selection is further made into data representing the characteristics. It is characterized by performing based on.

The invention described in claim 8 is the exchange method according to claim 6 or 7, wherein the data frame is A
It is a TM cell, the specific layer is an ATM layer, the destination identification information is VPI and VCI, and the data of the specific layer is CLP.

According to a ninth aspect of the present invention, a data frame assembled based on a communication protocol composed of a plurality of layers is received, and a specific one of the plurality of layers described in the data frame is received. A network system including an exchange that identifies a transmission destination of the data frame based on transmission destination identification information in a hierarchy, wherein the exchange is connected with a plurality of lines capable of transmitting to the transmission destination. , The switch selecting one line of the plurality of lines based on the data of the specific layer, which is characteristic of the data of the layer higher than the specific layer included in the data frame It is characterized by having means.

The invention according to claim 10 is the network system according to claim 9, wherein the exchange further comprises means for storing data representing the characteristics of each of the plurality of lines, and the selection. The means further comprises selecting one of the plurality of lines based on the data representing the feature.

The invention according to claim 11 is the network system according to claim 9 or 10, wherein the data frame is an ATM cell and the specific layer is A.
In the TM layer, the destination identification information is VPI and VC
I, and the data of the specific layer is a CLP.

[0019]

According to the present invention, the exchange receives a data frame assembled based on a communication protocol composed of a plurality of layers and transmits the data frame in a specific layer among the plurality of layers described in the data frame. The destination of the data frame is identified based on the destination identification information, and one of the plurality of lines that can be transmitted to the identified destination is defined as a layer higher than a specific layer included in the data frame. The selection is based on the data of the specific layer, which represents the characteristics of the data.

Further, according to the present invention, one of the plurality of lines that can be transmitted to the identified destination is selected based on the data representing the characteristics of each of the plurality of lines.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings.

[Embodiment 1] (1) Configuration of network system In FIG. 1, 10 is an ATM network as an example of the network system of the present invention, and 11 to 17 are ATM exchanges as an example of the exchange of the present invention. The network system of the present invention may include exchanges other than the exchange of the present invention. 21 to 23 are terminals for transmitting and receiving ATM cells. Reference numerals 31 and 32 are IWUs (Inter Working Units), which convert connectionless type data received from a LAN using TCP / IP into ATM cells to convert the ATM network 1
0 to the ATM cell received from the ATM network
Convert to CP / IP data frame and send to LAN. Reference numerals 44 to 49 are LAN terminals.

(2) Hardware Configuration of ATM Switch FIG. 2 is a hardware block diagram of the ATM switches 11-17. In FIG. 1, 301 is a network terminator (NT), which performs insulation between the ATM communication line 150 and the device, serial / parallel conversion, and data buffering. Network terminator 301
Has a CPU bus and a data transfer bus. The CPU bus is connected to the CPU 121.

Reference numeral 102 is an address processor (AP) as an example of the "semiconductor device for communication" described in the claims. The AP 102 searches the input data and outputs the search result according to a preset sequence. In this embodiment, the address processor 102 is used when cell data is transferred from the NT 301 to the switching element unit (SEU) 111.
The data output from the switching element (SEU) 111 is transferred to D
It is directly transferred to the NT 301 by the MAC 103.

A direct memory access controller (DMAC) 103 transfers data between the NT 301, the address processor 102 and the SEU 111. The DMAC 103 has a CPU bus and a data transfer bus, and the CPU bus is connected to the CPU 121. The data transfer bus is the NT301 data transfer bus,
It is connected to the input and output ports of the address processor 102 and the port of the SEU 111.

The SEU 111 has a plurality of data ports (referred to simply as ports) and one control port, and connects the ports according to the data input from the control port. 121 is a CPU that controls the entire ATM switch,
Reference numeral 122 is a ROM that stores programs executed by the CPU 121, and 123 is a RAM. Reference numeral 124 is a timer (TIMER), which is used by the CPU 1 for each set time.
21 is interrupted. Reference numeral 125 is an input device for inputting various settings and the like to the ATM exchange, and is typically composed of a keyboard and a mouse. 12
Reference numeral 6 denotes a display device that displays the operating state of the device.

An ATM line 150 is connected to an external network. 160 is an ATM data bus insulated from the ATM line 150 by the NT 301. 170 is a CPU bus.

(3) Configuration of Address Processor (AP) The hardware configuration of the address processor 102 will be described with reference to FIG. Like many programs, this device can be easily produced and used by those skilled in the art by clarifying specifications. Therefore, the specifications of the port configuration, CAM array configuration, register configuration, etc. of this device will be described in detail below.

(3-1) Port Configuration As shown in FIG. 3, the address processor 102 has an input port (INPUT PORT) 210 and an output port (OUTPUT PORT).
) 220, and a CPU port 230.

(3-1-1) Input Port The input port 210 is a port for inputting search key data. The port width is 32 bits but can be set so that only 16 or 8 bits are valid. The data (ID: 0 to 31) needs to be input in synchronization with the WR pulse. The extreme positive of WR can be set to positive logic or negative logic.

In FIG. 3, the IPB of the input port 210
The USY terminal is a terminal that outputs a signal indicating whether data can be input to the input port, and outputs LOW when another port (output port or CPU port) is operating and does not accept data input to the input port. To be done.

The input data input to the input port 210 is combined (compounded) by the data formatter 211 in accordance with a pre-defined input port sequence to become 32-bit data (comparand data). Processing such as search is performed according to the comparand data.

(3-1-2) Output Port The output port (OUTPUT PORT) 220 is a port for outputting data such as search results. The data width is 32 bits, but it can also be set so that only 16 or 8 bits are valid. Output data (OD) is output by inputting a LOW pulse (RD pulse) to the RD terminal of the output port 220 while LOW is input to the OE terminal of the output port 220.

The OPBUSY terminal of the output port 220 is
It is a terminal that outputs a signal that indicates whether or not data can be output from the output port, and the other port (input port or CPU
Port) is operating and data cannot be output from the output port, LOW is output.

(3-1-3) CPU Port The CPU port is a 16-bit input / output data bus for interfacing with the host processor. Data width is 1
It has 6 bits and an address width of 8 bits. The address is
Used to specify the address of various registers in the address processor. The following operations can be performed from the CPU port.

(3-1-3-1) Reading / Writing Registers Data can be written in and read from various registers in the chip.

(3-1-3-2) CAM table writing / reading CAM table writing / reading is performed by Memory_A
This is done via access to the R, Memory_HHA, and Memory_HEA registers.

(3-1-3-3) Execution of various commands Commands are executed by writing execution commands in the command register. For example, when a search execution instruction is written, the address processor 102 inputs data from an input port and outputs a result from an output port according to a defined sequence without requiring CPU intervention. Definition of search conditions performed before writing a search execution command is also performed from the CPU bus 230.

(3-1-3-4) Search It is also possible to search through the CPU port. The command is executed by writing an operation code in the IP command register.

(3-2) Configuration of CAM Array The CAM array 250 has 2048 CAM basic words shown in FIG. In FIG. 4, empty bit 2
51 indicates whether or not valid table data is written in the word. Set to 0 when valid data is being written. The hit / miss hit flag 255 indicates whether or not the search result is a hit.
The access bit 256 indicates whether or not there is a hit or a miss hit in the past search.

The logical configuration of the CAM array 250 will be described with reference to FIG. As shown in FIG. 5, the CAM array 25
0 has a logical configuration of row (horizontal row in FIG. 5) × column (vertical column in FIG. 5). The row and column sizes are shown in Figure 5.
Is defined by the segment number bit 253 and the boundary bit 252 of the. These bits are pre-written before the address processor 102 begins execution.

The segment bits shown in FIG. 4 are 3 bits, and the value of 000 to 111 indicates the segment number. The segment number represents the position in the column direction. If the segment bit value is from 000 words to 111 words, the table column size is 8, and if the segment bit 253 value is only 000 words, the table column size is 1. . Thus, the column size of the table is defined by the value written in the segment bit.

A word with a segment bit of 000 indicates that a new row in the CAM table begins.
1 is written in the boundary bit (see FIG. 4) of this word. The column size n and the row size m of the CAM table must satisfy n × m ≦ 2048. The remaining words defined by 2048-nxm cannot be used. Search is
Do this for each column of the table. One segment 254 in the same column is used by using one comparand data.
Refer to times.

When the definition of the table is completed, the segment 254 of each basic word is transferred to the segment 254 through the CPU port 230.
You can write data. The CPU port 2 determines whether the data written in each segment is used as search data (key data) and whether it is used as target data to be output when the search hits.
It is defined by the CPU 121 via 30. The data written in each segment can be used as both key data and target data. Also, a different number of segments for each column can be used as search data or target data. C after power on
Since the values in the AM table are indefinite, the CAM table is set by writing the boundary bits in all the segments (2048 segments) of the CAM.

(3-3) Register Configuration The address processor 102 includes a control register,
It has a CUT register, a SEARCH register, an HHA register, 16 comparand registers, 16 CS registers, 16 mask registers, 32 AOC registers, 32 AOSC registers, and an address register. The CS register and the mask register are divided into 8 channels each for A channel and B channel. AOC
The 16 registers and the AOSC register are divided into 16 A channels and B channels.

The data width of the input data is set by the control register. Input data used for search is set by the CUT register. The SEARCH register sets the condition for executing the search. The HHA register has
The address of the hit CAM data is stored. 16
Up to 16 comparand data are stored in each comparand register. 16 CS registers,
Set the number of bytes to shift comparand data when performing each search. The masked bits of each comparand data are set in the 16 mask registers.

A sequence of output data is set by 16 AOC registers of each channel. That is, the output data set in the 1st to 16th AOC registers are sequentially output from the output port. When it is defined that the CAM table data is output by the AOC register, the segment number of the CAM table to be output is set by the AOSC register corresponding to the AOC register. The address register sets the address of the CAM accessed from the CPU port. The setting contents of these registers are described in detail in “(3-4) Input sequence setting method” and “(3-5) Output sequence setting method”.

(3-4) Setting method of input sequence Two types (A channel and B channel) of input sequence of data (capture of data on input port, masking of comparand data, etc.) are set in the address processor 102. You can do it.

The maximum input sequence for each channel is 64.
It can be set for each input data. Up to 6
Which of the four input data is to be taken into the address processor is set by the 64-bit CUT register. That is, each bit of the CUT register is made to correspond to each input data, 1 is set to the bit corresponding to the fetched data, and 0 is set to the bit corresponding to the non-fetched input data. The 16-bit and 8-bit input data are combined (compounded) in the address processor and treated as a maximum of 16 32-bit wide data (referred to as comparand data). The 32-bit input data is treated as it is as 32-bit width comparand data. The comparand data is stored in 16 comparand registers.

The maximum amount of data that can be used for a search by the input sequence of one channel among the data fetched in the comparand register is the maximum column size of the CAM table, that is, eight. Therefore, when the effective input data width is 32 bits, 16 bits, and 8 bits, 8, 16, and 32 pieces of input data can be used for the search, respectively.

The input data set by the CUT register when fetched by the address processor is sequentially stored in the accumulation buffer of the address processor 102 in synchronization with the WR pulse. The 64-bit SEARCH register sets which input data is searched when stored in the accumulation buffer. That is, each bit of the SEARCH register corresponds to each of 64 input data, and the bit of the SEARCH register corresponding to the input data to be searched is set to 1. The search can be executed even when the 4-byte data is not stored in the comparand register. In this case, the value of the comparand data of the field in which no data is input is set to 0.

When performing the search, 1 to 3 bytes of the input data stored in the previous comparand register can be shifted to the comparand register to be searched. The number of bytes to be shifted when performing each search is set in the 2-bit shift amount field in the CS register. Further, the 3-bit segment designation field in the CS register is used to set the number of the segment in the CAM array to search for the input data. Eight CS registers are provided for each channel, and the shift amount and the segment to be searched can be set for each of the eight searches.
When the shift is not performed, the shift amount field is set to 0 as the default.

When a part of the comparand data is masked when executing the search, the bit corresponding to the masked bit in the mask register corresponding to the search is set to 0. Set 1 to the bits that are not masked. In the address processor, the value of the masked bit is masked to 0 by calculating the logical product (AND) of the value of the mask register and the comparand data when executing the search.

The input sequence advances one by one by inputting a WR pulse. Also, LOW for the SQRST pin
The input sequence returns to the beginning by inputting a pulse or an SQRST command from the CPU port.

(3-5) Output Sequence Setting Method When a search is executed, the register address of the hit data in the CAM table (CAM table data that matches the input data) is stored in the HHA register. When a plurality of segments are searched by the AND condition of a plurality of comparand data, the lowest addresses of the plurality of hit segments are stored in the HHA register.

After executing the search, data can be output from the comparand register, the HHA register, and the CAM table to the output port. The output data and the output order are determined by the output sequence. Two output sequences (A channel and B channel)
Can be set. For each channel
The following settings can be made.

Which of the 16 comparand registers, the HHA register, and the data of the hit row in the CAM table is output is set to 16 AO.
Set in each of the C registers. By setting the AOC register, the logical OR of the value of the comparand register and the value of the data of the hit row in the CAM table can be output. The data set in the first AOC register to the data set in the 16th AOC register are sequentially output from the output port. By setting the AOC register to output only the data of the comparand register, the data input to the input port 210 can be output from the output port 220 as it is.

The data of each segment of the hit row in the CAM table is irrespective of whether it is used for retrieval or not.
It can be output arbitrarily. The segment number of the output CAM table data is set in 16 AOSC registers associated with each of the 16 AOC registers. The output sequence advances one by one by the input of the RD pulse. Also, LOW for the SQRST pin
The output sequence returns to the beginning by inputting a pulse or an SQRST command from the CPU port.

(3-6) Execution of Search When the SWIOP command is input after the setting of the search conditions is completed, the address processor (AP) 102 shifts to the input / output mode (IOP mode) and follows the input from the input port 210. Perform a search. Which of the A channel and the B channel is used for each of the input sequence and the output sequence is set by a command from the CPU port.

However, the A channel or the B channel may be selected based on the first input data from the input port.

(3-7) Search from CPU Port Search data can also be input from the CPU port 210. The input search data is set in the CPU input register. When the SRCH command is subsequently input, the address processor 102 executes the search.

The search result can be output from the CPU port. The address of the hit CAM data is HH
Read from A register. The CAM data of the segment address set in the address register can be read by reading the Memory_AR register.

(4) Structure of Data Frame Using FIG. 6, an AT as an example of a “data frame”
The data structure of the M cell will be described. As shown in FIG. 6 (A), an ATM cell has a cell header of 5 octets and 48 octets.
It is composed of octet information fields. UNI (User Net) used between users and networks
work interface) and NN used between networks
The structure of the cell header in I (Network Network Interface) is shown in FIGS. 6 (B) and 6 (C).

In FIGS. 6B and 6C, the VPI
Is a virtual path identification, and VCI is a virtual channel identification. The VPI and VCI identify which communication the cell belongs to. VPI and VCI
Corresponds to the "destination identification information" in the present invention.
The values of VPI and VCI are usually set when an ATM connection is established and held until the ATM connection is released. PT is a payload type and indicates whether the information contained in the information field of the cell is user information or network information. CLP is a cell loss priority indication. By setting this bit, the AT
It is shown that the data contained in the data field of the M cell has a low priority regarding loss. A cell for which CLP is set is allowed to be selectively discarded when the network is congested. The CLP corresponds to the "data representing the characteristics of the data in the upper layer" in the present invention.

(5) Address process in this embodiment
Initial Setting of Server 102 (5-1) CAM Array Setting FIG. 7 shows the definition (table configuration) of the CAM array 250 of the address processor 102 in the ATM switching apparatus of the present invention. In this embodiment, the column size is set to 3. This setting is performed by the CPU 121 when the power of the ATM switching device is turned on or when the definition change is input from the input device 125.

When performing PVC type communication, each VPI and VCI used in the input side line to which the address processor is connected are stored in advance in two rows in the column of segment 0. deep. As shown in FIG. 6, in UNI, the upper 4 bits of the ATM cell header are GF.
C, and VPI and VCI are not stored. There UN
0 is stored in the upper 4 bits of the column of segment 0 of the address processor connected to the I line. Also, 0 is stored in the lower 2nd bit to the 4th bit of the column of segment 0 corresponding to PT. Each VPI and V
0 is stored in the least significant bit of segment 0 of one row of two rows associated with CI, and 1 is stored in the least significant bit of segment 0 of another row.

The AT is assigned to the least significant bit of segment 0.
The port number of the line in which the ATM cell may be discarded is stored in the row segment 1 that stores the value of the CLP that allows the M cell to be discarded. Segment 0
In the row 1 in which the value of CLP that does not allow the ATM cell to be discarded is stored in the least significant bit of, the port number of the line in which the ATM cell is not likely to be discarded is stored. The segment 2 stores the VPI and VCI used in each output side line. The lower 4 bits of segment 2 store the same value as the lower 4 bits of segment 0 of the row. When the line on the output side is UNI, 0 is stored in the 4 most significant bits.

When performing VC type communication, when a call is set up, various data are stored in columns 0 to 2 of the CAM array by the same method as the method of storing data of the CAM array in the PVC described above. That is, each time a call is set, VPI and VCI are set in two rows, 0 is stored in the least significant bit of segment 0 of one row, and 1 is stored in the least significant bit of segment 0 of another row. . On this occasion,
The empty bit of each word of the row that stores VPI and VCI is set to 0 (LOW) to indicate that word is in use. When the ATM connection ends, the CPU 121 determines that the VP for the connection is
A 1 (HIGH) is written to the empty bit of each word that was writing the I, VCI, and port number to indicate that those words are not used.

(5-2) Setting of Input Sequence In this embodiment, only the input sequence of A channel is set. The CPU 121 selects the input sequence of the A channel, and sets the effective data width of the input data to 8 bits which is the same as the width of the output data of NT by the control register. As shown in FIG. 6, VPI in NNI
And VCI are stored in the first to fourth octets. Therefore, the CPU 121 sets the 0th bit to the 3rd bit of the CUT register to 1 and sets the other bits to 0.
Set to. The input 4-byte data is combined in the address processor to form a single comparand data, which is stored in the comparand register.

Next, the third bit of the SEARCH register is set to 1 and the other bits are set to 0. Thus, the search is executed only when the input data corresponding to the third bit, that is, the fourth input data is input. Although the PT is stored in the lower 1st bit to the 4th bit of the 4th input data, the PT is not used for the search in this embodiment. Therefore, the CPU 121 sets the lower second bit to the fourth bit of the mask register (first mask register) corresponding to the first comparand data to 0. When connected to the UNI line, the most significant 4 bits are also set to 0. Other bits are set to 1. As a result, the data corresponding to the PT of the received ATM cell and the GF of the UNI
The data corresponding to C is masked to 0.

(5-3) Setting of output sequence The output sequence of the A channel is selected, and the effective data width of the output data is set to 8 bits which is the same as the width of the output data of NT by the control register. Next, the sequence of output data is set by the AOC register. In this embodiment, the VPI and VCI in the output side line are
The PT and CLP in the input data are combined and output.
Therefore, the AOC register is set to output the logical OR of the CAM data and the value of the first comparand register to the first AOC register. Further, since the VPI and VCI in the line on the output side are stored in the segment 2, the segment 2 is set in the first AOSC register.

When these settings are completed, the CPU 121
Issues a SWIOP command to the address processor 102 to transition the address processor 102 to the input / output mode.

(6) Search Operation of ATM Switching Device With reference to FIG. 8, the search operation of the exchange of the present invention after the initialization of each address processor 102 is completed and the mode is changed to the input / output mode will be described.

(6-1) Data input to address processor When the data of one cell is stored in the internal FIFO, the NT301 determines whether the received information is network information or user information depending on the value of PT. A judgment is made (S120). If the received cell is network information, an interrupt is issued to the CPU 121. Then, the CPU 121 reads the data of the information field (see FIG. 11) from the NT 301 and performs necessary processing according to the read data (S130). If the receiving cell is user information, the NT 301 sends DM
It requests the AC 103 to transfer 4-byte data to the address processor 102. DMAC 103 is NT
An address signal (ADR), a read signal (RD) and a chip select signal (CS) are output to the data transfer bus 301 to read data, and a write signal (WT) is output to the input port of the address processor to output the data. Is written to transfer the data (S140).

Since the address processor 102 has transited to the input / output mode, when the WT signal is input from the input port, the data on the input port is read and processed according to the preset input sequence. Ie 4
When byte data is input, these are treated as a single comparand data, the lower 2nd to 4th bits are masked to 0, and when connected to UNI, the upper 4 bits are also masked. Do a search. As a result of the search, if there is hit data in the data stored in the CAM, the AP 102 causes an interrupt to the CPU 121 (S150). CLP of received ATM cell
Indicates that the data can be discarded,
A row that stores the VPI and VCI of the received ATM cell and the CLP value indicating that the discarding of the data is permitted is hit in the segment 0. If the CLP of the received ATM cell does not indicate that the discarding of the data is permitted, the row that stores the VPI and VCI of the received ATM cell and the value of the CLP indicating that the discarding of the data is not permitted is hit in segment 0. To do.

The CPU 121 reads the segment address of the hit segment from the HHA register of the address register 102 of the address processor (S16).
0). Next, the value obtained by adding 1 to the read segment address is written in the address register of the address processor 102 to specify the port address of the hit data (S170). Next, the value of the output port is read from the Memory_AR register (S180), and the connection from the port to which the address processor is connected to the read output port is set for the SEU 111 (S19).
0). Thereby, the corresponding port is selected depending on whether or not the CLP allows the discarding of the data. CP
The U121 further rewrites bits other than the lower 4 bits of the first comparand register of the address processor 102 to 0 (S200). However, when connected to the UNI, bits other than the lower 4 bits and the upper 4 bits are rewritten to 0.

(6-2) Data Output from Address Processor 102 Next, the CPU 121 sends S from the address processor 102.
4-byte data transfer to EU111 via DMAC103
(S210). The DMAC 103 transfers data by outputting an output enable signal (OE) and RD to the output port 220 of the address processor 102 to read data, and outputting CS and WR to the SEU 111 to write data.

When the RD signal is input to the output port, address processor 102 outputs data from the output port according to a predetermined output sequence. That is,
The logical sum (OR) of the VPI and VCI values of the line on the output side stored in segment 2 and the value of the first comparand register is calculated, and the obtained 32-bit data is calculated every 8 bits. Output. Since the PT and CLP of the input data are stored in the lower 4 bits of the first comparand register and the other bits are set to 0, the output port of the address processor is set to FIG.
The information of the first octet to the fourth octet of the NNI on the output side line is output. When connected to the UNI, the GFC of the received ATM cell is stored in the output ATM cell.

When the 4-byte data transfer from the address processor is completed, the DMAC 103 issues an interrupt to the CPU 121. Then, the CPU 121
Subsequently, a 48-byte data transfer from NT301 to SEU111 is set (S220). This allows S
The ATM cell shown in FIG. 5 is input to the EU 111.

The cell data input to the SEU111 is
The data is transferred to the output port, and is transferred to the output port NT301 by the output port DMAC 103 based on the setting from the CPU 121 (S230). The output port NT 301 converts the transferred data into serial data and sends it to the output AT network 150. As a result, the ATM input to the ATM switching device is
Cell transfer can be done. When the transfer is completed, C
The PU 121 sends an SQ to the address processor 102.
The RST command is issued and the input / output sequence is returned to the beginning (S240).

[Other Embodiments] The network system shown in FIG. 1 and the exchange shown in FIG. 2 can be applied to a network using Ethernet type data frames. FIG. 9 shows an Ethernet type data frame.
In FIG. 9, DA is a destination address and corresponds to the destination identification information of the present invention. TYPE is a type of protocol used in the upper layer and corresponds to “data representing characteristics of data in the upper layer” of the present invention. CA
The M array has VPI, VCI, and CL of Example 1.
Instead of P, DA, SA, and TYPE are stored.

When a protocol for which a short delay time needs to be guaranteed is indicated by TYPE, the destination port shown in FIG. 7 is set to the number of the port connected to the network for which the short delay time is guaranteed. Store. When the protocol that requires high reliability is indicated in TYPE, the destination port shown in FIG. 7 stores the number of the port connected to the line with high reliability. The present invention can also be applied to a network using IEEE802.3 data frames. In FIG.
The data structure of the data frame of EEE802.3 is shown. DA corresponds to the destination identification information, and TYPE corresponds to “data representing the characteristics of the data in the upper layer”. In this case, the CAM array includes the VPI and VC of the first embodiment.
I and CLP instead of IEEE802.3 D
Stores A, SA, and SNAP TYPEs.

The present invention can also be applied to a network system using a TCP / IP data frame. FIG. 11 shows the structure of the IP data frame. FIG.
In 1, TOS is the type of service and describes the quality of service required for that datagram. TOS
Indicates the priority of the datagram and the required certainty. PROT indicates a protocol used in the upper layer of IP, and TCP or UDP is specified by PROT. The TOS and PROT correspond to the "data representing the characteristics of the upper layer data" of the present invention. DEST
Is a destination address and corresponds to the "destination identification information" of the present invention. When the destination line is selected by PROT, DEST and PROT are stored instead of VPI, VCI, and CLP of the first embodiment. When the destination line is selected by TOS and PROT, DEST, TOS, and PROT are stored instead of VPI, VCI, and CLP of the first embodiment.

[0084]

As described above, according to the present invention, an exchange identifies a transmission destination of a data frame based on transmission destination identification information of a specific layer among a plurality of layers described in the data frame. Then, one of the plurality of lines that can be transmitted to the identified destination can be selected based on the characteristics of the data in the layer above the specific layer. Therefore, even when lines of various networks provided by a plurality of vendors are connected to the exchange, the exchange can select a line having appropriate characteristics according to the information to be transmitted.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a configuration of a network system of the present invention.

FIG. 2 is a hardware block diagram of the exchange of the present invention.

FIG. 3 is a hardware block diagram of an address processor.

FIG. 4 is an explanatory diagram showing a structure of a CAM basic word.

FIG. 5 is an explanatory diagram showing a configuration of a CAM array.

FIG. 6 is an explanatory diagram showing the structure of an ATM cell.

FIG. 7 is an explanatory diagram showing setting of a CAM array.

FIG. 8 is a flowchart showing a search operation by the address processor of the present invention.

FIG. 9 is an explanatory diagram of an Ethernet type data frame.

FIG. 10 is an explanatory diagram of an IEEE802.3 data frame.

FIG. 11 is an explanatory diagram of an IP data frame.

[Explanation of symbols]

10 ATM Network 11-13 ATM Switching Device 21-24 Terminal 31 IWU 44-46 LAN Terminal 101 Address Processor (AP) 103 Dynamic Memory Access Controller (D
MAC) 104 bus arbiter 111 switching element unit (SEU) 121 CPU 122 ROM 123 RAM 124 timer 125 input device 126 display device 131-134 address processor 150 ATM communication line 160-161 ATM data bus 170 CPU bus 210 input port 211 data formatter 212 Input port sequencer 220 Output port 222 Output port sequencer 230 CPU port 231 Flag logic 250 CAM array 251 Empty bit 252 Boundary bit 253 Segment number bit 254 Segment 255 Hit / miss hit flag 256 Access bit 301-308 Network terminator (NT)

Claims (11)

[Claims] 1. A data frame assembled on the basis of a communication protocol composed of a plurality of layers is received,
An exchange that identifies a transmission destination of the data frame based on transmission destination identification information in a specific layer among the plurality of layers described in the data frame, which can be transmitted to the transmission destination. A plurality of lines are connected, and one line of the plurality of lines is selected based on the data of the specific layer, which represents the characteristic of the data of the layer higher than the specific layer included in the data frame. An exchange equipped with a selection means for selecting. 2. The exchange according to claim 1, further comprising means for storing data representing characteristics of each of the plurality of lines, wherein the selecting means further includes data representing the characteristics, An exchange characterized by selecting one of the plurality of lines. 3. The exchange according to claim 1, wherein the data frame is an ATM cell, the specific layer is an ATM layer, and the destination identification information is VPI and VCI. An exchange characterized in that data of a specific layer is a CLP. 4. The exchange according to claim 2 or 3, wherein the data representing the characteristic is data based on the level of security of each of the plurality of lines. 5. The exchange according to any one of claims 1 to 4, wherein the selection means stores in advance position information indicating a position in the data frame of the destination identification information, Means for selecting the identification information from the data string based on position information, means for searching the destination of the data string using the selected identification information, and inputting in advance what number data in the data frame And a means for storing start position information indicating whether to perform the search, and a search start means for starting the search by the search means when the data indicated by the start position information is input. An exchange having a communication semiconductor device provided with means for outputting information indicating the destination. 6. A data frame assembled based on a communication protocol composed of a plurality of layers is received,
A switching method applied to an exchange that identifies a transmission destination of the data frame based on transmission destination identification information in a specific layer among the plurality of layers, which is described in the data frame, wherein: Is connected to a plurality of lines that can be transmitted to the destination, and represents characteristics of data in a layer higher than the specific layer included in the data frame, based on the data in the specific layer. A switching method, wherein one of the plurality of lines is selected. 7. The exchange method according to claim 6, wherein data representing characteristics of each of the plurality of lines is stored, and the selection is further performed based on the data representing the characteristics. How to exchange. 8. The exchange method according to claim 6, wherein the data frame is an ATM cell, the specific layer is an ATM layer, and the destination identification information is VPI and VCI. An exchange method, wherein the data of the specific layer is a CLP. 9. A data frame assembled based on a communication protocol composed of a plurality of layers is received,
A network system comprising an exchange that identifies a transmission destination of the data frame based on transmission destination identification information in a specific layer among the plurality of layers described in the data frame, wherein the exchange has A plurality of lines that can be transmitted to the destination are connected, and the exchange is configured to store data in the specific layer, which indicates characteristics of data in a layer higher than the specific layer included in the data frame. A network system having a selecting means for selecting one of the plurality of lines based on the above. 10. The network system according to claim 9, wherein the exchange further includes means for storing data representing characteristics of each of the plurality of lines, and the selection means further includes the characteristics. A network system, characterized in that one of the plurality of lines is selected based on the data represented. 11. The network system according to claim 9, wherein the data frame is an ATM cell, the specific layer is an ATM layer, and the destination identification information is VPI and VCI. A network system, wherein the data of the specific layer is a CLP.