JPH0810531B2 - Time axis compression circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The following description will be given.

A Industrial field B Outline of invention C Conventional technology D Problems to be solved by the invention E Means for solving problems (Fig. 1) F Action G Example H Effect of invention A Industrial TECHNICAL FIELD The present invention relates to a time axis compression circuit.

B Outline of the Invention The present invention is, for example, in an electronic still camera or a reproducing apparatus thereof, in the case of compressing a time axis of an audio signal,
By utilizing the data interpolation, the compression of the time axis can be performed with one memory.

C Prior Art In an electronic still camera, a video signal of one field is recorded on a video floppy as one annular magnetic track. And in such a camera,
Further, it is considered that when the recording switch is pressed, the audio signal is recorded on a track different from that of the video signal.

In this case, the audio signal has a time axis length of, for example, 1 /
It is compressed to 640 times and recorded, and the track is 1/4
Used in units. That is, one track is divided into four sectors, an audio signal for about 2.5 seconds is time-axis compressed and recorded in one sector, and a required number of sectors are used. For example, when recording a voice of 15 seconds, 6 seconds (1.5 tracks) are used because 15 seconds / 2.5 seconds = 6.

FIG. 3 shows an example of such an electronic still camera. In FIG. 3, (1) is a subject, (2) is an imaging lens, (3) is a shutter, (10) is a video signal system, and (2)
0) indicates an audio signal system, and in this example, the shutter (3) is an electromagnetic shutter, and the video signal system (1
The image sensor (11) of 0) is a CCD having a color separation filter.

Further, (4) indicates a video floppy, and the magnetic sheet contained in this floppy (4) is rotated at a field frequency by a motor (6) through a rotating shaft (5), and the magnetic sheet is used for video signals. The magnetic head (17) and the magnetic head (29) for audio signals are brought into contact with each other. And these heads (17), (2
The motors (31) and (32) are mechanically coupled to the motor (9), and a predetermined drive voltage is supplied from the control (33) to the motors (31) and (32).
The track positions in 7) and (29) can be changed arbitrarily.

Further, (40) indicates a system controller for controlling the entire operation of this camera. The syscon (40) is composed of a microcomputer, and the syscon (40) includes a shutter switch (41) for image pickup.
And the voice recording switch (42) are connected.

Further, for example, the pulse generating means (7) is provided on the rotating shaft (5), and each time the magnetic sheet of the floppy (4) makes one rotation, one pulse Pg is taken out as a signal indicating the rotation phase. The pulse Pg is supplied to the syscon (40) through the shaping amplifier (8), and various control signals are extracted from the syscon (40) at a predetermined timing in response to the operation of the switches (41) and (42).

Further, (90) indicates a clock forming circuit, to which a pulse Pg and a control signal from the syscon (40) are supplied to form various clocks at a predetermined timing and are supplied to the respective circuits.

Then, as shown in FIG. 4A, when the shutter switch (41) is pressed at an arbitrary time point t ₁ , a control signal is supplied from the syscon (40) to the shutter (3), and as shown in FIG. The shutter (3) is opened during the period t _{1 to} t _2, the image of the subject (1) is projected on the CCD (11), and the charge image is accumulated on the CCD (11).

Then, as shown in C and D of the same figure, when the time t ₃ of the first pulse Pg after the time point t ₂ comes, the next pulse Pg starts from this time point t _3.
The read clock RDCK is supplied from the forming circuit (44) to the CCD (11) for one field period up to the time point t _{4 of} time, and the CCD (11) outputs the color video signal Sc for one field as shown in FIG. Is taken out.

Then, the signal Sc is supplied to a video processing circuit (13) through a preamplifier (12) to extract a luminance signal and a chrominance signal from the signal Sc, and these signals are supplied to a recording circuit (14) so that an electronic still camera and The recording signal of the format in the video floppy (addition signal of the FM signal modulated by the luminance signal and the line-sequential FM signals modulated by the color difference signals of red and blue) is Sv. Then, the signal with the signal Sv is supplied to the switch circuit (15), as shown in the control signal is supplied figure F to the system controller (40) from the switch circuit (15), in the period t ₃ ~t ₄ Sv is taken out, and this signal Sv is supplied to the recording head (17) through the recording amplifier (16) and recorded on the floppy (4) as one annular track.

When the recording switch (42) is turned on during an arbitrary period, the audio signal is recorded during the on period.
That is, the audio signal Sa from the built-in microphone (21) is supplied to the low-pass filter (23) through the preamplifier (22) and is band-limited to the signal Sa of 5 kHz or less, for example, and this signal Sa is recorded as noise for recording. It is supplied to the time axis compression circuit (25) through the reduction circuit (24). The compression circuit (25) time-compresses the signal Sa by 1/640 times every 2.5 seconds. Therefore, the compression circuit (25) outputs the signal Sa of 2.5 seconds every 2.5 seconds. The signal St, which is compressed in the time domain, is taken out in approximately 1/4 field period. The band of the signal Sa before compression on the time axis is 5 kHz.
Therefore, the bandwidth of the signal St after compression on the time axis is 640 times 3.2 MHz.
z, which is almost the same band as the video signal recorded on the floppy disk (4).

Then, this signal St is supplied to the FM modulation circuit (26)
Converted to FM signal Sf, and this signal Sf is switched circuit (27)
To the switch circuit (27) from the syscon (40) and the signal Sf during the period of the signal St.
Is taken out and this signal Sf is supplied to the recording head (29) through the recording amplifier (28), and one signal St is sequentially recorded as one sector on another track of the floppy (4).

Therefore, according to such a camera, it is possible to conveniently record the sounds and comments around the camera while shooting, which is convenient.

The screen and sound recorded on the floppy disk (5) can be reproduced by the signal processing reverse to the above. (Reference:
SUMMARY OF THE INVENTION Problems to be Solved by the Invention By the way, in the time axis compression circuit (25), the time axis of the audio signal Sa is compressed 1/640 times to be the signal St. Can be done as shown in FIG. Ie the original signal
Sa is supplied to the A / D converter (251) and is sequentially converted into a digital signal Sd, and as shown in FIG. 6, of this signal Sd, a 1/4 field period Ts (this is because the head (29) is 1
The signal Sd of one sector is scanned sequentially to the sub memory (254) and continues (2.5 seconds −
1/4 field period) Tm signal Sd is switch circuit (252)
Through the main memory (253). Then, at this time, during the period Ts, the signal S of the main memory (253) is
d is read at 640 times the speed at the time of writing,
At the end of the period Ts, the signal Sd of the sub memory (254) is instantaneously transferred to the main memory (253) through the switch circuit (252). Therefore, from the main memory (253), the digital signal Su time-compressed by 1/640 times for each period Ts for each period (Ts + Tm) is extracted.

Then, this signal Su is supplied to the D / A converter (255), and the analog signal St whose time axis is compressed 1/640 times is transmitted for the period T.
Every s, this signal St is
It is supplied to the modulation circuit (26) through 56).

Thus, according to this time axis compression circuit (25), 2.5
It is possible to obtain a signal St that is time-axis compressed 1/640 times every second.

However, in the compression circuit (25), the sub memory (254) is required and its capacity becomes large.
Hereinafter, the capacity of the sub memory (254) will be calculated.

Frequency of signal Su: 2 × 3.58MHz (color subcarrier frequency 2
If the number of bits of the signal Sd is 8 bits / 1 sample (hence, 1 sample is 1 byte), the frequency of the signal Sd, that is, the sampling frequency in the A / D converter (251) is the frequency of the signal Su. Divide by 640 to obtain the value as shown below.

2 × 3.58MHz / 64011.19kHz Therefore, the sampling number x of the signal Sd in the 1/4 field period Ts is 11.19kHz × 1000.
2.5: 2.5 × 11190 = 1/4 field period: x
Can be obtained by

That is, x is 27975 x (1/60) x (1/4) ÷ 2.5 x 46.6
This requires 47 bytes of sub memory (254).

The sub memory (254) cannot use the vacant address of the main memory (253) due to the access of the signal Sd, and must be provided separately from the main memory (253).

Moreover, as shown in FIG. 6, the main memory (253)
Also, since the relationship between the timing and frequency of writing and reading with respect to the sub memory (254) becomes complicated, the control circuits of the main memory (253) and the sub memory (254) become complicated.

On the other hand, in the main memory (253) alone, as shown in FIG. 7, the writing of the signal Sd and the reading of the signal Su overlap each other by a quarter field period every 2.5 seconds. The main memory (25
3) can not be done to.

The present invention seeks to eliminate these problems.

E Means for Solving Problems Now, regarding the signal Sd before the time axis compression and the signal Su after the time axis compression, the signal Sd is continuous as shown in FIG. 1/4 field period every 2.5 seconds
The signals Su are intermittently taken out by Ts, and the signal Su thereof is recorded as one sector in the floppy disk (4) in the 1/4 field period Ts. In this case, in the period Ts, the frequency ratio between the signal Sd and the signal Su is 1: 640, and the signal Sd of 1 sample exists with respect to the signal Su of 640 samples.

Therefore, the present invention pays attention to such a point, and provides only one memory for 2.5 seconds, and during the recording period Ts, the signal Su is read out during the 639 sample periods of the 640 sample periods of the signal Su. And signal during the remaining 1 sample period
While writing Sd, the signal Su necessary for this period
Is replaced by interpolation.

F action That is, when data writing and reading overlap in time, the slower one of writing and reading is performed at the timing of the earlier processing, and the earlier processing is not performed. Substitute by interpolation.

G Embodiment In FIG. 1, an audio signal Sa from a noise reduction circuit (24) is supplied to an A / D converter (51), and a formation circuit (44) supplies an A / D converter (5).
1) is supplied with the above-mentioned clock having the frequency of 11.19 kHz, and the signal Sa is converted into the digital signal Sd as shown in FIG. 2A. The signal Sd is a parallel signal of, for example, 8 bits per sample, and in FIG. 2A, (d + i), (d + (i + 1)), ... Are the sample (data) numbers of the signal Sd. Indicates.

This signal Sd is the data input terminal of the memory (52).
Supplied to DI. The memory (52) of this is signal Sd 2.5
It has a capacity (address) of seconds and is of 8 bits / 1 address.

Further, a clock is supplied from the forming circuit (44) to the address counters (61) and (62) as count inputs, and the address changes from the counter (61) in synchronization with the signal Sd as shown in FIG. 2B. The write address signal SLAD is taken out, and the read address signal FSAD whose address changes at a speed 640 times that of the signal SLAD is taken out from the counter (62) as shown in FIG. However, in this case, in the signals SLAD and FSAD, (m + 1), (m +
2), ... and (n + 0), (n + 1), ... are signals
Indicates the address of SLAD, FSAD, which is incremented by one, but when incremented to the address corresponding to 2.5 seconds, it is reset to the address corresponding to 0 seconds and incremented again by one. ,
That is, it circulates and changes according to the capacity of the memory (52).

Then, these address signals SLAD and FSAD are supplied to the multiplexer (63), and the audio signal is written to the floppy (4) (2.5 seconds- (1/4) field period). The signal SLAD is taken out as the output signal ADRS, this signal ADRS (= SLAD) is supplied to the address terminal AD of the memory (52), and the write signal MWRT from the forming circuit (44) to the write terminal WE of the memory (52). Is supplied to. Therefore, the digital signal Sd is sequentially written in the memory (52) during the period Tm.

Then, in the 1/4 field period Ts during which the audio signal is written to the floppy (4), as shown in FIG. 2D, the output signal ADRS from the multiplexer (63) is one cycle (period Tw). Write address signal
SLAD and read address signal FSAD for 639 consecutive cycles (period Tr) are alternately taken out. That is, the second
As shown in FIG. D, the address signal ADRS supplied to the memory (52) is the write signal (write enable signal) MW shown in FIG. 2E during the first one cycle period of one sample.
Since RT becomes active, it is used as an address for writing. Since the read signal (read enable signal) MEMR shown in FIG. 2F becomes active during the remaining 639 cycles, it is used as an address for reading.

Therefore, in this signal ADRS, the write address signal SLAD exists for only one cycle in the period Tw of every 640 cycles, and the address indicated by the signal SLAD is
(M + 1), (m + 2), and so on, while
The read address signal FSAD has addresses (n + 1), (n + 2), 639 cycles of the period Tr out of 640 cycles.
Although it is continuous like this, one cycle of the remaining period Tw does not exist (the signal SLAD exists here), and this period
Tw is at No. 1.

This signal ADRS is the address terminal of the memory (52).
As shown in FIG. 2E, the signal is supplied to the AD and is transmitted from the forming circuit (44) to the write terminal WE of the memory (52) for a period
The write signal MWRT is supplied to Tw. Therefore, the period
Also in Ts, the signal Sd is correctly written in the memory (52) for each sample in the period Tw.

Further, at this time, the forming circuit (44) to the memory (52).
As shown in FIG. 2F, the read terminal OE of the
A read signal MEMR is provided. Therefore, in the period Ts, as shown in FIG. 2G, 639 samples of the signal Sd are sequentially read one sample at a time in the period Tr, and 640 at the time of writing from the data output terminal DO of the memory (52).
The signal Su will be obtained at twice the speed. However, in this case, this signal Su is missing in each period Tr. This is because as shown in FIG. 2D, writing is performed by the write address in the first one cycle period of one sample period.

This signal Su is supplied to the latch (53), and at the same time, the forming circuit (44) supplies the latch (53) with the latch clock FCLK which does not rise during the period Tw as shown in FIG. 2H. Therefore, as shown in FIG. 2I, the latch (53) provides a signal Su of data equal to the data one cycle before in the period Tw. That is, from the latch (53), the signal for which the previous value was held during the period Tw.
You get Su.

Then, this signal Su is supplied to the D / A converter (54), and is also supplied with a clock from the forming circuit (44) to be converted into an analog signal St whose time axis is compressed 1/640 times. St is supplied to the low pass filter (55) to remove unnecessary components and then supplied to the modulation circuit (26).

Thus, according to the present invention, the time base compression is performed. In this case, in particular, according to the present invention, when the writing and reading of the signal with respect to the memory (52) overlap in time, as shown in the period Tw. In addition, the writing of the slow signal Sd is given priority, and the fast signal during this period Tw
Since Su is read by interpolating the previous value to obtain the signal Su, the memory (52) only needs to have a capacity of 2.5 seconds, and only one memory is required. Therefore, the configuration is simple and its peripheral circuits are also simple.

In the example of FIG. 1, the write address signal SLAD
Interpolation can be performed by the processing of. Further, average value interpolation or the like can be performed as signal interpolation.

H Effect of the Invention According to the present invention, the time base compression is performed. In this case, in particular, according to the present invention, when the writing and reading of the signal with respect to the memory (52) overlap in time,
As shown in the period Tw, the writing of the slow signal Sd is given priority, and the reading of the fast signal Su in this period Tw is performed by interpolating by the previous value hold to obtain the signal Su. ) Is sufficient if it has a capacity of 2.5 seconds, and only one is required. Therefore, the configuration is simple and its peripheral circuits are also simple.

[Brief description of drawings]

1 and 3 are system diagrams of an example of the present invention, and FIGS. 2 and 4 to 7 are diagrams for explaining the same. (51) is an A / D converter, (52) is a memory, (53) is a latch, and (54) is a D / A converter.

Claims (1)

[Claims] 1. An information signal of a first frequency within an m-th unit period equal to n samples of the information signal is stored in a storage means by a first address signal equal to one sample period of the information signal. The information signal stored in the storage means,
In the m + 1st unit period, a time axis compression circuit that reads out with a second address signal having a frequency n times (n> 1) the frequency of the first address signal to compress the time axis of the information signal. A first address signal generating means for generating a first address signal equal to the time of one sample of the information signal, and a first address signal generating means having a frequency n times (n> 1) the frequency of the first address signal. Second address signal generation means for generating two address signals, storage means for storing the information signal, and one cycle defined by a predetermined 1 / m cycle period within one sample period of the information signal In the period, the first address signal from the first address signal generation means is selected, and the first address signal is supplied to the storage means for writing the information signal, In the remaining n-1 cycle period within the period of one sample, the second address signal from the second address signal generating means is selected, and the second address signal is read out to the storage means. And a control means to be supplied for use, and at least when reading the information signal from the memory, a period corresponding to the predetermined one cycle period corresponds to a cycle period before or after the predetermined one cycle period. A time axis compression circuit including an interpolation means for interpolating using an information signal.