JPH0810560B2 - Semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device that has a memory cell group and performs reading and writing of data from the memory cell group, and in particular, a plurality of bits of data from a memory cell array. The present invention relates to a semiconductor memory device having a parallel function test function of simultaneously reading and judging the quality of memory cells in the memory cell array.

(Prior Art) As a readable / writable semiconductor memory device, there are a static random access memory (hereinafter referred to as static RAM), a dynamic random access memory (hereinafter referred to as dynamic RAM), and the like.
Such a semiconductor memory device includes a memory cell group having a large number of memory cells, data for decoding an address signal to select a memory cell, a data bus having a plurality of data lines connected to the memory cell group, and this data bus. And an input / output circuit for inputting and outputting data to and from the memory cell group, and a plurality of control signal lines for transmitting control signals for controlling the entire device.

In this type of semiconductor memory device, when performing a functional test for determining the quality of a memory cell, the decoder sequentially selects the memory cells in the memory cell group bit by bit, and stores the storage data of each bit in the data bus and the input / output. The data was sequentially read out through the circuit and the quality of each memory cell was judged.

However, in such a functional test, the test time becomes extremely long as the capacity of the memory cell group increases. Therefore, various proposals have been made in order to reduce the test time.

Conventionally, as this type of semiconductor memory device, for example, there is one described in JP-A-61-59700. In this semiconductor memory device, a detection circuit whose operation is controlled by a control signal is connected to a data bus, the same data is written in advance in each memory cell for a functional test, and the detection circuit simultaneously reads a plurality of bits. Whether or not all the logical values of the data are the same is detected, and the quality of each memory cell is judged. By performing such a parallel functional test, it becomes possible to significantly reduce the test time.

(Problems to be Solved by the Invention) However, the semiconductor memory device having the above configuration has the following problems.

When the memory cell group has a large capacity, the power consumption for driving them increases. Therefore, in order to reduce the power consumption, the memory cell group is divided into a plurality of memory cell blocks, and each memreal block is randomly distributed. The split drive method is used to select and operate. Also, the chip size increases as the capacity of the memory cell group increases, but it is necessary to make the chip size smaller in order to mount them in a case of a certain size. As one method for adopting the divided driving method and reducing the chip size, it has been proposed to make the wiring area, particularly the area for forming a data bus having many data lines, smaller. In this method, the wiring area is reduced by arranging a large number of data lines forming the data bus substantially in parallel along the ends of the plurality of memory cell blocks.

However, as the memory cell size gradually increases to 256 kbits, 1 Mbits, and 4 Mbits, it is not only necessary to narrow the pitch between each data line, but also the data bus increases as the number of memory cell blocks increases. The wiring length is also increased. For example, in a megabit class semiconductor memory device, a data bus has been wired up to a length of about 10 mm with a minimum width and interval allowed in a wafer process. When the length of the data bus is increased in this way, the statistical probability of metal residue between the data lines formed of metal increases, and the probability that adjacent data will short-circuit with each other increases.

If each data line is short-circuited due to the presence of metal residue,
The shorted data lines will have the same logical value. Then, as in the above-mentioned document, a parallel function test in a state where the device is equipped with a detection circuit that determines a normal function when the logical values of the data bus match and determines an abnormal function when the logical values do not match, when mounted on a wafer or case. However, there is a problem in that an abnormal function is erroneously determined as a normal function.

The present invention has a problem that the prior art has a problem that, when an increase in power consumption and an increase in chip size due to an increase in memory capacity are suppressed, the pitch between data lines becomes narrow and the data bus The present invention provides a semiconductor memory device that solves the problem that the length is increased, which causes a short circuit between the data lines to reduce the reliability of the parallel function test.

(Means for Solving Problems) In order to solve the above problems, the present invention relates to a memory cell group having a plurality of memory cells for storing data and a memory cell group connected in parallel with each other. A data bus having a plurality of selected data lines and a coincidence state of logical values of a plurality of data simultaneously read from the memory cell through the data bus at the time of a functional test for the memory cell connected to the data bus. In a semiconductor memory device including a detection circuit and a plurality of control signal lines for transmitting a control signal for controlling writing and reading of data to and from the memory cell group, a plurality of control signal lines are provided between the plurality of data lines. The control signal line is arranged adjacent to the data line.

(Operation) According to the present invention, since the semiconductor memory device is configured as described above, by arranging the control signal line between each data line, those data and the control signal line are short-circuited by a metal residue or the like. , The signals on the data lines and the signals on the control signal lines have an influence on each other, so that the logical values of the respective data lines when reading a plurality of bits having the same logical value at the same time are the same. Disappear. Therefore, the detection circuit that determines the normal function when the logical values match is determined as the abnormal function. This prevents erroneous determinations and improves reliability in parallel function tests. Therefore, the above problems can be eliminated.

(Embodiment) FIG. 1 is a configuration block diagram of a semiconductor memory device showing an embodiment of the present invention.

This semiconductor memory device is a readable / writable memory device of a memory cell group division drive system, and includes a plurality of divided memory cell blocks 1-1 to 1-4 and their respective memory cell blocks 1-1 to 1- 4 and a control signal generation circuit 21 for inputting a clock signal φ and a write / read signal Si to generate various control signals S1 to S7 for controlling the operation of the memory device. A plurality of control signal lines 22-1 to 22-7 for transmitting the control signals S1 to S7 are connected to the output side of the control signal generation circuit 21. The data bus 20 comprises a plurality of data lines 20-1 to 20-4, and each of the data lines 20-1 to 20-4 has a plurality of memory cell blocks 1-1 to 1
-4 adjacent to each other along the edge of -4, extending substantially parallel,
Further, all or part of the control signal lines 22-1 to 22-7 are arranged between the respective data lines 20-1 to 20-4 and adjacent to them.

A memory cell array 10 in which a large number of memory cells for storing data are arranged in a matrix is provided in each of the memory cell blocks 1-1 to 1-4, and the row data 11, the column decoder 12, and the memory cell array 10 are provided in the memory cell array 10. And a plurality of preamplifiers 13-1
~ 13-4 are connected, and each of the preamplifiers 13-1 to 13-4 is connected.
A plurality of main amplifiers 14-1 to 14-4 and read / write control circuits 15-1 to 15-4 are connected to each other. The row decoder 11 decodes a plurality of address signals AD to select a memory cell in a row in the memory cell array 10, and the column decoder 12 decodes a plurality of address signals AD to select a column memory cell in the memory cell array 10. It is a circuit to do. The preamplifiers 13-1 to 13-4 are circuits for amplifying the read data of the selected memory cells, and the main amplifiers 14-1 to 14-5 are the preamplifiers 13-1 to 13-4.
It is a circuit that amplifies the read data amplified in 13-4 until the high level is near the power supply potential and the low level is near the ground potential. The read / write control circuits 15-1 to 15-4 are
Based on S1, the outputs of the main amplifiers 14-1 to 14-5 are output to the data bus 20 side at the time of data read, and the signals on the data bus 20 are sent to the main amplifiers 14-1 to 14-5 and the preamplifier at the time of data write.
It is a circuit for transmitting to the memory cell array 10 side through 13-1 to 13-4.

Further, this semiconductor memory device is provided with an address buffer 23 for inputting a plurality of address signals AD at a predetermined timing based on the control signal S2, and the output side of the address buffer 23 is one of the memory cell blocks 1-1 to 1-1. -4 are connected to the row decoder 11 and the column decoder 12 respectively, and are also connected to the input side of the multiplexer 25, and the other input side of the multiplexer 25 is connected to the data bus 20. The input side of the detection circuit 26 is connected to the data bus 20, and the output side of the detection circuit 26 and the multiplexer.
The output side of 25 is connected to the output circuit 28 via the control circuit 27. The input side of the multiplexer 25 is the input circuit
Connected to 29.

Here, the block decoder 24 is a circuit that decodes the address signal AD from the address buffer 23 and selects one of the plurality of memory cell blocks 1-1 to 1-4. The multiplexer 25 uses the address signal AD from the address buffer 23.
Based on the above, the plurality of data lines 20 that make up the data bus 20
-1 to 20-4 is selected and the selected 1-bit data is supplied to the control circuit 27, and the output of the input circuit 29 is changed to the data line based on the control signal S3. 20-1 ~
It has a function to supply to 20-4. The detection circuit 26, based on the control signal S4, detects a plurality of data lines during the parallel function test.
A circuit that detects whether or not all the logical values of 20-1 match and provides the detection result to the control circuit 27, which is configured by an AND gate and the like. The control circuit 27, based on the control signal S5,
The output of the multiplexer 25 is applied to the output circuit 28 during the normal data read operation, and the detection circuit 26 is provided during the parallel function test.
Is a circuit for giving the output of the above to the output circuit 28. The output circuit 28 is a circuit that outputs the output data Do of the control circuit 27 at a predetermined timing based on the control signal S6, and the input circuit 29 is a control signal.
It is a circuit that inputs the input data Di at a predetermined timing based on S7 and gives it to the multiplexer 25.

FIG. 2 is a sectional view taken along the line AA of FIG. In FIG. 2, the data line 20-1 is formed on the semiconductor substrate 30 with the insulating film 31 interposed therebetween.
20-4 are arranged, and further control signal lines 22-5 to 22-7 are arranged between the respective data lines 20-1 to 20-4.

The operation of the semiconductor memory device configured as above will be described.

In a normal data write operation, the input signal Di is input to the input circuit 29 by the control signal S7 output from the control signal generation circuit 21, and the data bus is passed through the multiplexer 25.
Transmitted on 20. Multiple address signals AD supplied
Is input to the address buffer 23 by the control signal S2,
The input address signal AD is decoded by the block decoder 24 and 1 of the plurality of memory cell blocks 1-1 to 1-4 is decoded.
One, for example, 1-1 is selected. In the selected memory cell block 1-1, the row decoder 11 and the column decoder 12 decode the input address signal AD and select the memory cell in the memory cell array 10 to be written. Then, the write / read control circuits 15-1 to 15-4 take in the input data Di on the address bus 20 by the control signal S1 and input the input data Di.
Is passed through the main amplifiers 14-1 to 14-4 and the preamplifiers 13-1 to 13-4 to write data in the selected memory cell.

In a normal data read operation, for example, when reading the data in the memory cell array 10 in the memory cell block 1-1, the stored data of the memory cells selected by the row decoder 11 and the column decoder 12 is stored in the preamplifier 13-1. It is amplified by 13-4 and the main amplifiers 14-1 to 14-4 and transmitted to the data bus 20 through the write / read control circuits 15-1 to 15-4. Then, the multiplexer 25 selects 1-bit data on the data bus 20 based on the input address signal AD,
Output it through the control circuit 27 and the output circuit 28.
Output in the form of.

In such write and read operations, the block decoder 24 causes the plurality of memory cell blocks 1-1 to 1
-4 is selected one by one. Therefore, the power consumption of the memory cell block in the non-selected and standby state is sufficiently smaller than the power consumption of the memory cell block in the selected and operating state, so that the power consumption of the entire device can be small.

Next, the operation of the parallel function test on the memory cell array 10 will be described.

For example, when the memory cell array 10 in the memory cell block 1-1 selected by the block decoder 24 is tested, for example, 4 corresponding to the number of data lines 20-1 to 20-4 is used.
The same input data Di of bits is input from the input circuit 29 and transmitted to the data bus 20 through the multiplexer 25. Then, in the memory cell block 1-1, the write / read control circuits 15-1 to 15-4 take in the 4-bit input data Di on the data bus 20 at the same time, and the main amplifiers 14-1 to 14-4 and the preamplifier 14-1. Through 13-1 to 13-4, the 4-bit memory cells selected by the row decoder 11 and the column decoder 12 are simultaneously written. In this way, the same data is written into all memory cells in the memory cell array 10 by 4 bits.

After that, the row decoder 11 and the column decoder 12 select four memory cells in the memory cell array 10,
Pre-amplifier 13-1 to 13-4 and main amplifier 12 bit data
Amplified by -1 to 14-4, and simultaneously supplied to the data bus 20 through the read / write control circuits 15-1 to 15-4. Then, the detection circuit 26 operated by the control signal S4 detects whether or not the logical values of the 4-bit data on the data bus 20 match, and outputs a detection signal corresponding to the detected detection signal to the control circuit 27 and the output circuit 28.
Output through. Therefore, based on the output of the output circuit 28,
It is possible to determine a normal function when the logical values of the 4-bit data match and an abnormal function when the logical values do not match. In this way, the function is determined by reading from the memory cell array 10 by 4 bits. If the logical values of the 4-bit data do not match, a normal read operation is performed and the 4-bit data is read bit by bit, whereby a memory cell having an abnormal function can be found.

The test time can be shortened by performing the parallel functional test for each 4 bits as described above.

Here, it is assumed that the data lines 20-1 to 20-4 and the control signal lines 22-5 to
It is assumed that any part of 22-7 is short-circuited due to metal residue or the like.

Generally, the control signals S1 to S7 have a logical value and a time at which the logical value occurs determined by the function of the device.
On the other hand, since the logical value of the data bus 20 changes depending on the random logical value data that is input to the device, the control signal lines 22-5 to 22-7 and the data lines which are arranged adjacent to each other and substantially parallel to each other.
If there is a metal residue between 20-1 and 20-4 and there is a short circuit,
Those control signal lines 22-5 to 22-7 and data lines 20-1 to 20-4
Influence each other, and the logic values on the data bus 20 change the logic values of the control signals S5 to S7 and the time at which the logic values occur, thereby hindering normal functions. Data bus as well
The logic value on 20 changes depending on the logic values of the control signals S5 to S7 and the time at which the logic value occurs. Therefore, when a plurality of bits having the same logical value are read simultaneously, the logical values of the data lines 20-1 to 20-4 do not coincide with each other. Therefore, the detection circuit that determines the normal function by the coincidence of the logical values. 26 is judged as an abnormal function. As a result, it is possible to prevent an erroneous determination as in the conventional device and improve the reliability of the parallel function test. Further, since the control signal lines 22-5 to 22-7 are arranged between the data lines 20-1 to 20-4, it is possible to prevent the area of the wiring region from increasing.

The present invention is not limited to the illustrated embodiment, and for example, the number of write and read bits at the time of the parallel function test may be set to a number other than 4 bits, or the number of the control signals S1 to S7 may be set to another number. Further, the entire structure of the semiconductor memory device can be modified to another structure. Further, the present invention can be applied to other semiconductor memory devices in which the memory cell group is not divided and driven.

(Effects of the Invention) As described in detail above, according to the present invention, the control signal line is arranged between the plurality of data lines arranged substantially parallel to each other, so that the wiring region The effect of improving the reliability of the parallel function test can be expected without increasing the area of the.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a semiconductor memory device showing an embodiment of the present invention, and FIG. 2 is a sectional view taken along the line AA of FIG. 1-1 to 1-4 …… Memory cell block, 10 …… Memory cell array, 11 …… Row decoder, 12 …… Column decoder, 15-1 to 15
-4 …… Read / write control circuit, 20 …… Data bus, 20-1
~ 20-4 ... data line, 21 ... control signal generation circuit, 22-1 ~
22-7 …… Control signal line, 24 …… Block decoder, 25 ……
Multiplexer 26 ... Detection circuit 27 ... Control circuit 28
...... Output circuit, 29 …… Input circuit, AD …… Address signal,
Di …… input data, Do …… output data, S1 to S7 …… control signals.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 27/10 491

Claims (1)

[Claims] 1. A memory cell group having a plurality of memory cells for storing data, a data bus having a plurality of data lines connected to the memory cell group and arranged substantially in parallel, and a data bus A detection circuit for detecting a coincidence state of logical values of a plurality of data simultaneously read from the memory cell through the data bus at the time of a functional test for the connected memory cell, and controlling writing and reading of data to and from the memory cell group. In a semiconductor memory device having a plurality of control signals for transmitting a control signal for controlling, the control signal lines are arranged between the plurality of data lines and adjacent to the data lines. Semiconductor memory device.