JPH08122017A - Position recognition method for multiple chip elements - Google Patents

Position recognition method for multiple chip elements

Info

Publication number
JPH08122017A
JPH08122017A JP7264233A JP26423395A JPH08122017A JP H08122017 A JPH08122017 A JP H08122017A JP 7264233 A JP7264233 A JP 7264233A JP 26423395 A JP26423395 A JP 26423395A JP H08122017 A JPH08122017 A JP H08122017A
Authority
JP
Japan
Prior art keywords
electrodes
corners
multiple chip
angled
side faces
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7264233A
Other languages
Japanese (ja)
Inventor
Masayuki Negoro
雅之 根来
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP7264233A priority Critical patent/JPH08122017A/en
Publication of JPH08122017A publication Critical patent/JPH08122017A/en
Pending legal-status Critical Current

Links

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  • Length Measuring Devices By Optical Means (AREA)
  • Non-Adjustable Resistors (AREA)

Abstract

PURPOSE: To obtain a position recognition method in which a connected series of rectangular multiple chip elements can be positioned easily by forming corners at end parts of the element to be right-angled and forming side faces, the surface and the rear of side-face electrodes at the end parts out of right- angled corners. CONSTITUTION: Cutouts 3 are formed in central parts on both side faces 2c of a ceramic substrate 2 whose plane shape is rectangular, and electrodes 4 which come into contact with the side faces 2c are formed on the surface 2a. The electrodes 4 are divided at the cutouts 3, resistors 5 are formed between the electrodes 4, and they are protected by, and covered with, an overcoat layer 6. Side-face electrodes 7 which come to the surface 2a and the rear 2b are formed on the side faces 2c, corners of the electrodes 7 are formed to be right-angled, and the surface 2a, the rear 2b and the side faces 2c are formed out of right-angled corners. A resistor 1 is positioned so as to be sandwiched between guides 8, and it is not sandwiched and held obliquely because its corners are right-angled. In addition, since the corners can be recognized as sharp feature points, a multiple chip elements can be positioned by optical measures.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】この発明は、多連チップ抵抗
器、多連ジャンパチップ等の多連チップ素子の位置認識
方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a position recognition method for multiple chip elements such as multiple chip resistors and multiple jumper chips.

【0002】[0002]

【従来の技術】多連チップ素子は、種々のものがあり、
例えば先行技術として特開昭52−135048号公
報、特開昭62−256406号公報、実開昭61−1
42402号、実開平1−156509号、実開昭63
−155270号、実開昭63−3070号等にも記載
されている。
2. Description of the Related Art There are various types of multiple chip elements,
For example, as prior arts, JP-A-52-135048, JP-A-62-256406 and JP-A-61-11-1.
No. 42402, Actual Kaihei 1-156509, Actual Kaisho 63
It is also described in No. 155270, No. Sho 63-3070 and the like.

【0003】図5の(a)は、多連チップ素子の一例と
して、従来の多連(ここでは二連)のチップ抵抗器を示
している。このチップ抵抗器21は、セラミック基板2
2上に、抵抗体25,25を形成し、オーバーコート層
26で被覆している。セラミック基板22側面には、各
抵抗体25,25に接続する側面電極27,…,27が
形成されている。隣接する側面電極27,27間は、切
欠部23(スルーホールが分割されたもの)で分離され
ている。
FIG. 5A shows a conventional multiple (here, double) chip resistor as an example of a multiple chip element. This chip resistor 21 is a ceramic substrate 2
Resistors 25, 25 are formed on the surface 2 and covered with an overcoat layer 26. Side electrodes 27, ..., 27 connected to the resistors 25, 25 are formed on the side surface of the ceramic substrate 22. The side surface electrodes 27, 27 adjacent to each other are separated by a notch 23 (divided through hole).

【0004】[0004]

【発明が解決しようとする課題】上記従来の多連チップ
素子は、図5の(b)に示すように一対の位置決めガイ
ド28,28で挟んで位置決めされ、印刷回路基板に実
装される。ところが、切欠部23’がセラミック基板2
2の角にもあるため、図6に示すように傾いた状態でガ
イド28,28に挟持され、位置ずれした状態で実装さ
れる問題点があった。又、光学的手段、例えばビデオカ
メラ等で位置決めしようとしても、シャープな特徴点が
なく、位置決めが困難である問題点があった。
The above-mentioned conventional multiple chip element is positioned by being sandwiched by a pair of positioning guides 28, 28 as shown in FIG. 5B, and mounted on a printed circuit board. However, the notch 23 ′ has the ceramic substrate 2
Since there are also two corners, there is a problem that they are sandwiched between the guides 28, 28 in an inclined state as shown in FIG. In addition, even if an optical means such as a video camera is used for positioning, there is no sharp feature point and there is a problem that positioning is difficult.

【0005】一方、従来の多連チップ素子では、各側面
電極27の面積が大きく取れないため、印刷回路基板へ
の固着性が劣る問題点があった。又、側面電極27は、
はんだ又はニッケルをめっきして形成されるが、このめ
っき性に劣るという問題点もあった。このような問題点
は、上記先行技術にもみられるが、それらの問題点につ
いては何ら記載且つ示唆されておらず、解決策も全く講
じられていないのが現状である。
On the other hand, in the conventional multiple chip element, since the area of each side electrode 27 cannot be made large, there is a problem that the adherence to the printed circuit board is poor. The side electrode 27 is
It is formed by plating solder or nickel, but there is also a problem that this plating property is poor. Such problems are also found in the above-mentioned prior arts, but at present the problems are not described or suggested and no solution is taken at all.

【0006】この発明は、上記に鑑みなされたもので、
位置決めが容易で、且つ固着性、めっき性を向上させる
ことを目的としている。
The present invention has been made in view of the above,
The purpose is to facilitate positioning, and improve adhesion and plating properties.

【0007】[0007]

【課題を解決するための手段】上記目的を達成するため
に、この発明の多連チップ素子の位置認識方法は、一対
の対向側面にそれぞれ側面電極を2以上配置し、隣接す
る側面電極間を切欠きにより分離してなる矩形状の多連
チップ素子の位置認識方法であって、前記矩形状の多連
チップ素子の端部の角を直角とし、端部に位置する側面
電極を側面、表面及び裏面ともに直角の角まで形成して
なる多連チップ素子の直角の角を認識し、この直角の角
により多連チップ素子の位置決めを行うことを特徴とす
る。
In order to achieve the above object, the position recognizing method for a multiple chip element according to the present invention is such that two or more side surface electrodes are arranged on a pair of opposing side surfaces, and the side surface electrodes are arranged between adjacent side surface electrodes. A method for recognizing a rectangular multiple chip element separated by a notch, wherein the corners of the ends of the rectangular multiple chip element are right angles, and the side electrodes located at the ends are side surfaces and surfaces. It is characterized in that the right angle of the multiple chip element formed by forming up to the right angle on both the rear surface and the back surface is recognized, and the multiple chip element is positioned by this right angle.

【0008】この位置認識方法によると、多連チップ素
子の端部の角が直角とされるため、直角の角の部分をシ
ャープな特徴点として認識することができ、直角の角を
認識することで、多連チップ素子の位置決めを容易にす
ることができる。又、端部に位置する側面電極は、その
面積が大きくなるから、固着性及びめっき性を向上させ
ることもできる。
According to this position recognition method, since the corners of the ends of the multiple chip element are right angles, the right angle corners can be recognized as sharp feature points, and the right angle corners can be recognized. Thus, the positioning of the multiple chip element can be facilitated. Further, since the side surface electrode located at the end portion has a large area, it is possible to improve the sticking property and the plating property.

【0009】[0009]

【発明の実施の形態】以下、この発明の実施の形態を図
1乃至図4に基づいて以下に説明する。ここでは、位置
認識を行う多連チップ素子として二連のチップ抵抗器を
取り上げたものであり、図1の(a),(b)は、それ
ぞれ二連チップ抵抗器1の外観斜視図、Ib−Ib線に
おける断面図を示している。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to FIGS. Here, a double chip resistor is taken up as a multiple chip element for position recognition. FIGS. 1A and 1B are external perspective views of the double chip resistor 1 and Ib, respectively. The sectional view in the line -Ib is shown.

【0010】2はセラミック基板であり、その平面形状
は長方形となっている。セラミック基板2の両側面2
c,2cの中央には、切欠き3,3が形成されている。
セラミック基板2の表面2aには、側面2cに接するよ
うに電極4,…,4が形成され、これら電極4,4は切
欠き3,3により分割されている。又、電極4,4間に
跨がるように抵抗体5が形成されている。これら抵抗体
5,5はオーバーコート層6で被覆保護される。
Reference numeral 2 is a ceramic substrate, which has a rectangular planar shape. Both sides 2 of the ceramic substrate 2
Notches 3 and 3 are formed at the centers of c and 2c.
Electrodes 4, ..., 4 are formed on the surface 2a of the ceramic substrate 2 so as to be in contact with the side surface 2c, and these electrodes 4, 4 are divided by notches 3, 3. A resistor 5 is formed so as to extend between the electrodes 4 and 4. These resistors 5 and 5 are covered and protected by the overcoat layer 6.

【0011】一方、セラミック基板2の側面2cには、
表面2a、裏面2bにも回り込むように側面電極7が形
成される。側面電極7は、導電ペーストを印刷・焼成し
て形成される厚膜電極7aと、はんだ又はニッケルをめ
っきして形成されるめっき層7bとにより構成される。
セラミック基板2が長方形であるから、側面電極7の角
も直角となっている。側面電極7は、側面2c、表面2
a及び裏面2bともに直角の角まで形成されている。
On the other hand, on the side surface 2c of the ceramic substrate 2,
The side electrode 7 is formed so as to wrap around the front surface 2a and the back surface 2b. The side surface electrode 7 is composed of a thick film electrode 7a formed by printing and firing a conductive paste, and a plating layer 7b formed by plating solder or nickel.
Since the ceramic substrate 2 is rectangular, the corners of the side electrodes 7 are also right angles. The side surface electrode 7 has a side surface 2c and a surface 2
Both a and the back surface 2b are formed to a right angle.

【0012】次に、この実施例の二連チップ抵抗器1の
製造工程を図2及び図3を参照しながら説明する。ま
ず、大型のセラミック基板12を用意し、図2の(a)
に示すように、スルーホール13を形成すると共に、ス
リット14,15を形成して、セラミック基板12の表
面を区画する。次に各区画内に、導電ペーストをスクリ
ーン印刷し、これを焼成して電極4,4とする。更に抵
抗ペーストをスクリーン印刷し、これを焼成して抵抗体
5とする〔図2の(b)参照〕。この抵抗体5は、例え
ばレーザトリミングによりその抵抗値が所定の値となる
よう調整される。
Next, the manufacturing process of the double chip resistor 1 of this embodiment will be described with reference to FIGS. First, a large ceramic substrate 12 is prepared, and as shown in FIG.
As shown in, the through hole 13 is formed and the slits 14 and 15 are formed to partition the surface of the ceramic substrate 12. Next, a conductive paste is screen-printed in each section, and the paste is baked to form the electrodes 4 and 4. Further, a resistance paste is screen-printed and fired to form a resistor 5 [see FIG. 2 (b)]. The resistor 5 is adjusted by laser trimming so that its resistance value becomes a predetermined value.

【0013】セラミック基板12上には、ガラスペース
トがスクリーン印刷され、これを焼成して、オーバーコ
ート層6が各区画内に形成される。この状態でセラミッ
ク基板12が、スリット14に沿ってブレイクされ、短
冊状のセラミック基板12’とされる〔図3の(a)参
照〕。各セラミック基板12’の側面2cには、導電ペ
ーストが付着され、これを焼成して厚膜電極7aとす
る。更にこの厚膜電極7aの表面を、はんだ又はニッケ
ルでめっきして、めっき層7bを形成し、側面電極7と
する〔図3の(b)参照〕。最後にスリット15に沿っ
てブレイクして二連チップ抵抗器1が完成する。
A glass paste is screen-printed on the ceramic substrate 12, and the glass paste is fired to form the overcoat layer 6 in each section. In this state, the ceramic substrate 12 is broken along the slits 14 to form a strip-shaped ceramic substrate 12 '[see FIG. 3 (a)]. A conductive paste is attached to the side surface 2c of each ceramic substrate 12 ', and the paste is fired to form the thick film electrode 7a. Further, the surface of the thick film electrode 7a is plated with solder or nickel to form a plating layer 7b, which is used as the side electrode 7 (see FIG. 3B). Finally, a break is made along the slit 15 to complete the double chip resistor 1.

【0014】この実施例の二連チップ抵抗器1は、図1
の(c)に示すように、ガイド8,8に挟持されて位置
決めされるが、角が直角であるため、傾いた状態で挟持
されることはない。又、直角の角をシャープな特徴点と
して認識できることにより、例えば光学的処理により、
位置決めを行うことが可能となる。又、側面電極7の外
形の角が直角となることにより、側面電極7の面積が大
きくなって、印刷回路基板上のはんだ付けパッドとはん
だで結ばれる面積が大きくなり、印刷回路基板への固着
性が高くなる。又、側面電極7の面積が広くなることに
より、めっき層7bの形成も容易となる。
The dual chip resistor 1 of this embodiment is shown in FIG.
As shown in (c), the guides 8 and 8 are sandwiched and positioned, but since the corners are right angles, they are not sandwiched and sandwiched. Also, by recognizing a right angle as a sharp feature point, for example, by optical processing,
It becomes possible to perform positioning. Further, since the outer shape of the side surface electrode 7 has a right angle, the area of the side surface electrode 7 becomes large, and the area where the side surface electrode 7 is connected to the soldering pad on the printed circuit board by soldering becomes large, and the side surface electrode 7 is fixed to the printed circuit board. Will be more likely. Further, since the area of the side surface electrode 7 is increased, the plating layer 7b can be easily formed.

【0015】なお、この発明は二連チップ抵抗器のみな
らず、図4の(a),(b)に示すように三連、四連或
いは図示しないが五連以上のチップ抵抗器1’,1”に
も適用可能である。又、この発明は抵抗器ばかりでな
く、コンデンサ、ジャンパ等各種の多連チップ素子に適
用可能である。
It should be noted that the present invention is not limited to a double chip resistor, but may be a triple chip resistor, a quadruple chip resistor as shown in FIGS. The present invention can be applied not only to resistors but also to various multiple chip elements such as capacitors and jumpers.

【0016】[0016]

【発明の効果】以上説明したように、この発明の多連チ
ップ素子の位置認識方法は、多連チップ素子を、その端
部の角を直角とし、端部に位置する側面電極を側面、表
面及び裏面ともに直角の角まで形成してなるものとし、
この多連チップ素子の直角の角を認識し、この直角の角
により多連チップ素子の位置決めを行うものであるか
ら、位置決めを正確且つ容易に行うことができると共
に、実装時の印刷回路基板への固着性の向上、製造時の
めっき性の向上を図ることができる。
As described above, according to the position recognition method for a multiple chip element of the present invention, the multiple chip element is formed such that the corners of the ends are right angles and the side electrodes located at the ends are side surfaces and surfaces. And both the back surface and the right angle,
Since the right angle of this multiple chip element is recognized and the multiple chip element is positioned by this right angle, the positioning can be accurately and easily performed and the printed circuit board at the time of mounting can be mounted. It is possible to improve the sticking property of and the plating property during manufacturing.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の一実施形態に係る二連チップ抵抗器
の外観斜視図(a)、(a)のIb−Ib線における断
面図(b)、及び同二連チップ抵抗器が位置決めガイド
で位置決めされた状態を説明する図(c)である。
FIG. 1 is an external perspective view (a) of a dual chip resistor according to an embodiment of the present invention, a cross-sectional view (b) taken along line Ib-Ib of (a), and the dual chip resistor is a positioning guide. It is a figure (c) explaining the state positioned by.

【図2】同二連チップ抵抗器の製造工程を説明する図で
ある。
FIG. 2 is a diagram illustrating a manufacturing process of the dual chip resistor.

【図3】図2に続く製造工程を説明する図である。FIG. 3 is a diagram for explaining the manufacturing process subsequent to FIG.

【図4】別の実施形態に係る三連チップ抵抗器の外観斜
視図(a)、及び四連チップ抵抗器の外観斜視図(b)
である。
FIG. 4 is an external perspective view of a triple chip resistor according to another embodiment (a) and an external perspective view of a quad chip resistor (b).
Is.

【図5】従来例に係る二連チップ抵抗器の外観斜視図
(a)、及び同従来の二連チップ抵抗器が正しく位置決
めされた状態を説明する図(b)である。
FIG. 5A is an external perspective view of a dual chip resistor according to a conventional example, and FIG. 5B is a diagram illustrating a state in which the conventional dual chip resistor is correctly positioned.

【図6】同二連チップ抵抗器が傾いて位置決めされた状
態を説明する図である。
FIG. 6 is a diagram illustrating a state in which the dual chip resistor is tilted and positioned.

【符号の説明】[Explanation of symbols]

2a セラミック基板表面 2b セラミック基板裏面 2c セラミック基板側面 3 切欠き 7 側面電極 2a Ceramic substrate front surface 2b Ceramic substrate back surface 2c Ceramic substrate side surface 3 Notch 7 Side electrode

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】一対の対向側面にそれぞれ側面電極を2以
上配置し、隣接する側面電極間を切欠きにより分離して
なる矩形状の多連チップ素子の位置認識方法であって、 前記矩形状の多連チップ素子の端部の角を直角とし、端
部に位置する側面電極を側面、表面及び裏面ともに直角
の角まで形成してなる多連チップ素子の直角の角を認識
し、この直角の角により多連チップ素子の位置決めを行
うことを特徴とする多連チップ素子の位置認識方法。
1. A method for recognizing a position of a rectangular multiple chip element, wherein two or more side surface electrodes are arranged on a pair of opposing side surfaces, and adjacent side surface electrodes are separated by a notch. The angle of the end of the multiple chip element is defined as a right angle, and the side electrode located at the end is formed up to the right angle on the side surface, front surface and back surface. A method for recognizing the position of a multiple chip element, characterized in that the multiple chip elements are positioned by the corners of the.
JP7264233A 1995-10-12 1995-10-12 Position recognition method for multiple chip elements Pending JPH08122017A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7264233A JPH08122017A (en) 1995-10-12 1995-10-12 Position recognition method for multiple chip elements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7264233A JPH08122017A (en) 1995-10-12 1995-10-12 Position recognition method for multiple chip elements

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP15885198A Division JP3415770B2 (en) 1998-06-08 1998-06-08 Multi-chip electronic components

Publications (1)

Publication Number Publication Date
JPH08122017A true JPH08122017A (en) 1996-05-17

Family

ID=17400347

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7264233A Pending JPH08122017A (en) 1995-10-12 1995-10-12 Position recognition method for multiple chip elements

Country Status (1)

Country Link
JP (1) JPH08122017A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001143913A (en) * 1999-11-11 2001-05-25 Matsushita Electric Ind Co Ltd Multiple chip resistor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH022896B2 (en) * 1982-02-09 1990-01-19 Mitsubishi Kasei Vinyl

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH022896B2 (en) * 1982-02-09 1990-01-19 Mitsubishi Kasei Vinyl

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001143913A (en) * 1999-11-11 2001-05-25 Matsushita Electric Ind Co Ltd Multiple chip resistor

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