JPH08123773A - Interprocessor communication device - Google Patents

Abstract

(57) [Abstract] [Object] The present invention relates to an interprocessor communication device, and an object thereof is to provide an interprocessor communication device capable of reliably transferring data between both devices. [Configuration] DM between two central control units via a bus
A device for transferring data such as A transfer and registers, which includes a data transfer register group of its own device (self transfer register group) and a data transfer register group of another device (other transfer register group) Managing the currently operating register group and the currently set register group, and when one device receives a data transfer request from the other device during data transfer, or when data transfer requests from both devices collide. Further, a control register control unit for storing a later or inferior transfer request in the data transfer register group, and a control register control unit connected to the control register control unit for issuing a data transfer request to the partner device, An interface control unit that receives an acknowledge and the output of the interface control unit controls the ; And a data buffer control unit that performs transmission and reception of data configured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interprocessor communication device.

[0002]

2. Description of the Related Art There is known a device (interprocessor communication device = IPC) for performing DMA transfer or data transfer between two central control devices (CPU) via a bus (IP-bus). FIG. 24 is a conceptual diagram of a conventional system. In the figure, 10 is two central control units (CPU), and these CPUs are connected by a bus (IP-bus) 11. Each CPU is composed of a processor (CC) 1, a main memory (MM) 2, a channel controller (CHC) 3, and an interprocessor communication device (IPC) 20.
The IP-bus is connected between IPCs.

In the system configured as described above,
When a data transfer request command is issued from one IPC to the other IPC, this command is notified to the other side IPC via the IP-bus. When the other party's IPC decodes this command, it reads the necessary data from the MM in its own system, and the IPC of the data transfer request side.
The data is transferred to the side via the IP-bus.

[0004]

When data is transferred in such a conventional system, various problems as described below occur.

25 and 26 show an operation sequence in the conventional system. FIG. 25 and FIG. 26 are combined into one sequence, and the connected portions are partially overlapped and shown. In the conventional IPC, when a data transfer request command is issued from both IPCs at the same time as in frame 1 (frame 1:
Command collision), the data transfer request of the slave IPC is rejected (the data setting of the frame 2 is rejected), and the data setting of the master IPC (frame 0) becomes valid. Then, the command of the master IPC is executed (from frame 3 to before frame 4). The data transfer request (frame 2) of the rejected slave IPC cannot be resumed without resetting as shown in frame 4. As described above, when the data transfer requests collide with each other, one of the data transfer requests is rejected. Therefore, there is a problem that the software processing takes time correspondingly and the data transfer capability is reduced.

Further, in the conventional IPC, the register (DSR) for displaying the status of the device and the contents of failure is used as its own IP.
I only have one for C. In this case, if some failure occurs in the other IPC, it can be known that the own IPC has failed, but it is not possible to identify the failure location and confirm the details of the failure. Therefore, it may take a long time to perform software processing, or it may not be possible to take an optimal measure.

In a general IPC, the CPU
When the CPU is added, it is necessary to confirm the normality of the IPC in advance even if the connection destination CPU is not in the operating state, and a data loopback function is provided for isolating the failure. However, in the conventional IPC, in order to realize the data loopback function, first, the data of the main memory (MM) is stored in the data buffer register (DBR) of the IPC by the first command, and the DBR of the IPC is stored by the next command. The method of storing data in MM is adopted. In this method, it is necessary to issue the command twice to fold back the data, which cannot be said to be the actual diagnosis of the control circuit. Further, the size of the foldback data is limited to the DBR capacity in the IPC, which is effective. There was a problem that it could not be diagnosed.

In a system using a bus,
It is common to distinguish between a master that gives priority to the bus and a slave that is inferior to operate. The CPU and the input / output device have a clear master-slave relationship, and any device that maintains that relationship permanently can be used, but even in a bus that connects 1: 1 devices that do not distinguish between a processor and a master-slave, Bus arbitration is required to obtain the right to use the bus, and an arbitration circuit for giving priority to either device is required.

Even so, the same IPC is not configured in the form of one having an arbitration circuit and the other having no arbitration circuit. In the case of the same device, it is general to provide arbitration circuits in both so that both can be used. Therefore, conventionally, a dip switch or the like is provided to fix the use / non-use (presence / absence of priority) of the arbitration circuit. In that case, the device that uses the arbitration circuit (master) side cannot diagnose the operation when the arbitration circuit is not used, while the device that does not use the arbitration circuit (slave) cannot diagnose the arbitration circuit online. was there.

For example, the IPC used as the master
If there is a suspicion of a failure, when you try to operate it by replacing it with the IPC used as a slave to isolate the failure, you do not know even if there is a potential failure because the arbitration circuit has not been used until then. It is possible that there is a wait.

Further, when the master / slave can be set by the program from the host device, the interprocessor communication device may have the master setting by both devices because the host device is different. When both devices become masters, the bus interface protocol may be wrong and communication may not be possible.

Further, in order to improve the processing capacity, a CPU may be added. In this case, IPC is required,
The diagnosis of the IPC must be connected to the IPC of the processor to be added. Even if there is a malfunction in the IPC to be added, there is a problem that it is difficult to determine which IPC is the failure. In addition, the diagnosis that causes an operation similar to the actual one has a restriction that the processor on the other side must also be booted up, and similarly, even if there is a malfunction in the operation at that time, it is determined which IPC is the failure. Is difficult.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an interprocessor communication device capable of reliably transferring data between both devices.

[0014]

FIG. 1 is a block diagram showing the principle of the present invention. The same parts as those in FIG. 24 are designated by the same reference numerals. In the figure, 20 is an interprocessor communication device (self IPC). Another IPC (not shown) is a bus I
It is connected via a P-bus. Configuration of other IPC Same as configuration of own IPC.

In the figure, reference numeral 21 denotes a control register section, which is composed of a data transfer register group (self transfer register group) 21A of its own device and a data transfer register group (other transfer register group) 21B of the other device. ing. In the self-transfer register group 21A, CMR is a self-instruction control register, WCR is a self-word count register, MAR is a self-memory address register, D
SR is a self-status display register (for own IPC), and MDSR is a self-status display register (for other IPC). In the other transfer register group 21B, #CMR is another instruction control register, #WCR is another word count register, and #MA.
R is another memory address register, #DSR is another state display register (for own IPC), #MDSR is another state display register (for other IPC).

Here, the MDSR stores a failure that occurred in another IPC while the own IPC is transferring data, and the #MDSR occurs in another IPC when the other IPC is transferring data. It remembers the fault. As described above, the present invention sets the register group to the own IPC.
The feature is that it has two sides, 21A for use and 21B for other IPC.

Reference numeral 22 manages the register group currently in operation and the register group currently set, and when one device (IPC) is transferring data and the other device (IPC) requests data transfer, When data transfer requests from both devices collide with each other, subsequent or inferior transfer requests are sent to the data transfer register groups 21A and 21B.
The control register control unit 23, which is stored in the device, is connected to the control register control unit 22, issues the data transfer request REQ to the partner device, and receives the acknowledge (ACK: response) from the partner device, the IPC interface controller 24 is The IPC interface controller 2
3 is a data buffer control unit which is controlled by the output of 3 and sends and receives data between the respective devices. The IPC interface control unit 23 and the interface control unit 23 (not shown) of another IPC are connected not by IP-bus but by a dedicated communication line, and exchange REQ and ACK.

The data buffer control unit 24 includes a data buffer register DBR and a transmission data buffer register S.
It comprises a BR and a reception data buffer register RBR. The data buffer control unit 24 uses the IP-bu
It is connected to s and transfers data with another device (another IPC). 25 is a DMA when performing DMA transfer between IPCs
It is a control circuit. The address bus 26 connected to the control register control unit 22 and the data bus 27 connected to the data buffer control unit 24 include a processor (CC) 1 and a main memory device (MM) 2 (not shown in FIG. 2).
5, FIG. 26). The data transfer system using the IPC of the present invention is the same as the system configuration diagram of FIG.

In this case, in the self-transfer register group 21A, status display registers for displaying the status and fault contents of the device are provided for the self device (DSR) and for the other device (MDSR), respectively. If the DSR of the device changes, the DSR of the device itself is added to the MDSR of another device as necessary.
It is preferable to provide a circuit for transferring the contents of SR so that it is possible to determine where the failure occurs.

Further, the other transfer register group 21.
In B, a status display register (#MDS) for displaying the status of the other device in operation and the content of the failure that occurred while the other device was operating.
It is preferable to provide R) because fault analysis can be performed regardless of which device requests transfer.

The self-transfer register group 21 is also provided.
It is possible to set a command for data wrapping within its own device and a data wrapping within another device as a diagnostic command in its own command control register (CMR) in A, and to provide a wrapping control unit that realizes these wrapping tests once. This is preferable in that the IPC data route can be diagnosed by the return command.

In addition, a transmission data buffer register (SBR) and a reception data buffer register (RBR) are provided in the data buffer control unit 24, and when the internal data return command is set, the return control unit It is preferable that the data output from the device itself be input at the same time via the bus driver in order to perform the data loopback diagnosis.

The other transfer register group 21 is also provided.
The other memory address register (#MAR) in B can be set from its own device, and a control circuit for controlling this #MAR is provided so that when executing the loopback command, the address of the main memory device (MM) is set. It is preferable to use #MAR as the setting register in order to send data from an arbitrary address of the MM and store the return data at the arbitrary address.

When data is returned by the return command, the address of the main memory to be written in #MAR is set to the content of the own memory address register (MAR) plus the content of the own word count register (WCR). It is preferable to automatically set the write address of the return data.

The return destination of the return command is
Providing a command to set an arbitrary register in the other transfer register group 21B and providing a circuit to set this command is the same as the other transfer register group I.
It is preferable for diagnosing the setting of PC within the own IPC.

Software for storing a master / slave setting flag for giving priority to command execution in advance in each device in the case where a data transfer request command is issued from two devices at the same time. It is preferable to provide a register that can be controlled by the above in order to freely change the master / slave setting.

Further, when the self device receives the master setting command, if it is found from the response information from the other device via the bus that the other device is already set as the master, the master setting can be immediately stopped. It is preferable to prevent both devices from becoming the master.

Further, in the case where the device is duplicated into the 0 system and the 1 system, the 0 system bus and the 1 system bus are interconnected, and one of them is set as a master and the other is set as a slave so that the 0 system and the 1 system are connected.
In order to diagnose the normality of the data transfer route in the IPC, it is preferable to enable communication between the systems and execute the diagnostic program between the devices of the 0 system and the 1 system.

[0029]

The data transfer register group of the own device (self transfer register group), the data transfer register group of the other device (other transfer register group), and the data transfer register group are provided on two sides. That is, I
One of the devices is transferring data by managing the control register group so that the PC transfer uses the own transfer register group for data transfer and the other IPC uses the other transfer register group for data transfer started. When there is a data transfer request from the other device or when the data transfer requests from both devices collide with each other, the later or inferior transfer request is saved in the data transfer register group, There is no need to reset the transfer request, the time required for software processing is short, and the data transfer capability is not reduced.

In this case, in the self-transfer register group 21A, status display registers for displaying the status and failure contents of the device are provided for the self device (DSR) and for the other device (MDSR), respectively. If the DSR of the device changes, the DSR of the device itself is added to the MDSR of another device as necessary.
By providing a circuit that transfers the contents of SR, it is possible to determine where the failure occurs.

Further, the other transfer register group 21.
In B, a status display register (#MDS) for displaying the status of the other device in operation and the content of the failure that occurred while the other device was operating.
By providing R), failure analysis can be performed regardless of the transfer requested by either device.

The self-transfer register group 21 is also provided.
By setting a command for data wrapping within its own device and a data wrapping within another device as a diagnostic command in its own command control register (CMR) in A, and by providing a wrapping control section for realizing these wrapping tests, it is possible to execute once. The IPC data route can be diagnosed with the return command.

In addition, a transmission data buffer register (SBR) and a reception data buffer register (RBR) are provided in the data buffer control unit 24, and when the own device data return command is set, the return control unit Data loopback diagnosis can be performed by simultaneously inputting the data output from the device itself via the bus driver.

The other transfer register group 21
The other memory address register (#MAR) in B can be set from its own device, and a control circuit for controlling this #MAR is provided so that when executing the loopback command, the address of the main memory device (MM) is set. By using #MAR as a register for setting, it is possible to send data from any address of the MM and store the return data at any address.

When data is returned by the return command, the address of the main memory to be written in #MAR is set to the content of the own memory address register (MAR) plus the content of the own word count register (WCR). As a result, the write address of the return data can be automatically set.

The return destination of the return command is
By providing a command for setting an arbitrary register in the other transfer register group 21B and providing a circuit for setting this command, the setting of another IPC of the other transfer register group can be diagnosed in the own IPC. it can.

Software for storing a master / slave setting flag for giving priority to command execution in advance in each device in the case where a data transfer request command is issued from two devices at the same time. The master / slave setting can be freely changed by providing a register controllable by.

When the own device receives the master setting command, if it is found from the response information from the other device via the bus that the other device is already set as the master, the master setting is immediately stopped. It is possible to prevent both devices from becoming the master.

Further, in the case where the device is duplicated into the 0-system and the 1-system, the 0-system bus and the 1-system bus are interconnected, and one of them is set as the master and the other is set as the slave, and the 0-system and the 1-system are set.
Communication is enabled between the systems, and the diagnostic program is executed between the 0-system and 1-system devices. As a result, it is possible to diagnose the normality of the data transfer route in its own IPC before adding a processor.

[0040]

Embodiments of the present invention will be described below in detail with reference to the drawings. 2 and 3 are diagrams showing an operation sequence example when data transfer requests from both IPCs collide.
2 and 3 are combined to show one sequence. The outline of the operation is as follows.

First, in order to start data transfer, each of the master IPC and the slave IPC sets data in its own transfer register group by the control register control unit 22 (frame 1-1, frame 1-2).

I from each IPC to the other IPC
The PC interface control unit 23 issues a data transfer request command REQ. If the commands collide, the master IPC has priority (box 2).

The self-transfer register group 21 A of the master IPC is copied to the other transfer register group 21 B of the slave IPC by the control register control unit 22. However, when transferring the register data to another IPC at the same time as setting the register of the own IPC, it is already necessary
This operation is not necessary because it has been copied to the other transfer register group 21B of the PC (frame 3).

Data transfer of the master IPC is performed.
That is, the data stored in the MM on the master IPC side designated by the MAR is read and transferred from the data buffer control unit 24 to the slave side via the IP-bus. At this time, when the data transfer is DMA transfer,
The DMA control circuit 25 controls data transfer.

Next, the data transfer on the slave IPC side is started. In this case, according to the present invention, the frame 1-2
Since the data has already been set in, it is not necessary to reset the data.

The contents of the own transfer register group 21A of the slave IPC are copied to the other transfer register group 21B of the master IPC. However, when the register data is transferred to another IPC at the same time when the register of the own IPC is set, another transfer register group 21 for another IPC is already transferred.
This operation is not necessary because it has been copied to B (frame 4, frame 5).

Data transfer of the slave IPC is performed. That is, M on the slave IPC side designated by MAR
The data stored in M is read and transferred from the data buffer control unit 24 to the master side via the IP-bus.

FIGS. 4 and 5 are diagrams showing an operation sequence example when one IPC receives a data transfer request from the other IPC during data transfer. 1 in both FIG. 4 and FIG.
Shows two sequences. The outline of the operation is as follows.

The own IPC starts data transfer (frame 1, frame 2). While the own IPC is transferring data, another IPC sets data in its own transfer register group 21A (frame 3).

The data transfer of the own IPC is completed. Start data transfer of another IPC. In the present invention, since the frame 3 is stored, it is not necessary to reset the data.

The contents of the self-transfer register group 21 A of the other IPC are changed to the other transfer register group 2 of the own IPC.
Copy to 1B. However, when the register contents of the own IPC are set and transferred to another IPC at the same time, this operation is not necessary because it has already been copied to the other transfer register group 21B of the own IPC (frame 4, frame 5). .

The data transfer of the other IPC is completed. FIG. 6 is a configuration block diagram showing a main part of one embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals. In the figure, the IPC 20 of the own CPU and the IPC 20 of the other CPU are I
It shows a state of being connected by P-bus. FIG. 7 shows FIG.
It is a figure which shows the operation sequence example of the Example shown in FIG. The operation sequence of this embodiment is as follows.

Data is being transferred from its own IPC to another IPC. Something went wrong with another IPC. The other IPC writes the failure content in its DSR.

Depending on the content of the failure, the other IPC sends the content of DSR to the MDSR of its own IPC. When the own IPC recognizes that the MDSR has been written, it notifies the own CC according to the degree of the failure.

In response to the notification from the IPC, the own CC reads MDSR and executes appropriate processing according to the failure content. In this case, in the self-transfer register group 21A, a status display register for displaying the status and failure content of the device is provided in the self-device DSR and the other-device MD.
When each SR is provided and the DSR of its own device changes,
By transferring the contents of the DSR of the own device to the MDSR of the other device as necessary, it is possible to identify where the failure occurs in each IPC.

Further, by providing a status display register #MDSR for displaying the status of the other device in operation and the details of the fault occurring while the other device is operating in the other transfer register group 21B, which device requests The failure analysis can be performed even for the transferred data.

FIG. 8 is an explanatory diagram of the data folding operation according to the present invention. In the figure ,, is the internal I
The data flow when the PC is returned, and the data flow when the IPC return in the partner processor is shown. In the case of, the data sent from the CC returns in the own IPC and returns to the own CC. On the other hand, in the case of, the data sent from the CC is transferred to the partner IPC, and the partner IPC
It returns inside and returns to its own CC via its own IPC. ,
The same applies to.

In the case of (1), the normality of the data transfer route in the own IPC can be diagnosed, and in the case of (2), the normality of the data transfer route including other IPCs can be diagnosed.
In case of, when adding a new CPU, the added CPU
It is effective in diagnosing the normality of the operation of.

FIG. 9 is an explanatory diagram of the IPC data loopback command in the own IPC at this time. In FIG. 9, 28 is a loopback control unit that executes a data loopback command, and 2
Reference numerals 9 and 30 are bus drivers for buffering data, and 31 is a gate control unit for controlling the gates of the bus drivers. The operation of the apparatus thus configured will be described.

When the own IPC bus data return command is set in the own instruction control register CMR, the return control unit 28 is activated. The loopback control unit 28 reads data from the designated address (set in MAR) of the main memory device MM, and the data buffer register D
Store in BR.

The loopback control unit 28 transfers the data of the DBR to the transmission data buffer SBR and starts the data transmission. At this time, the loopback control unit 28 commands the gate control unit 31 to close the gates of the bus drivers 29 and 30 so as not to be affected by the IP-bus cable.

The data sent from the SBR is received by the own buffer register RBR via the bus driver 29 → bus driver 30. The RBR data is returned to the DBR.

The data returned to the DBR is further stored in the original MM. In this way, the data sent from the MM and the data returned to the MM can be compared to diagnose the normality of the data transfer route in the own IPC.

FIG. 10 is an explanatory diagram of a data loopback command in another IPC. The same parts as those in FIG. 9 are designated by the same reference numerals. When the other IPC return command is executed, the data is transferred to the other IPC and sent back from the other IPC to the own IPC. The operation is shown below.

When the data return command in the other IPC bus is set to CMR, the return control unit 28 is activated. The loopback control unit 28 reads data from the designated address (set in MAR) of the main storage device MM and stores it in the DBR.

The loopback control unit 28 transfers the data in the DBR to the SBR and starts the data transmission. The loopback control unit 28 puts the data read from the SBR on the IP-bus via the bus driver 27.
This data enters the other IPC and is transferred to the reception data buffer RBR via the bus driver 30 of the other IPC.

On the other IPC side, the return control unit 28
Transfers data from RBR to DBR. The loopback control unit 28 reads the data in the DBR and transfers it to the transmission data buffer register SBR.

On the other IPC side, a new command (data return command return command in other IPC) is used to load the IP-bus via the bus driver 27 and transfer it to the RBR on the own IPC side.

The loopback control unit 28 reads the RBR data and returns it to the DBR. The data returned to the DBR is further stored in the original MM. In this way, the data sent from the MM and the MM
It is possible to diagnose the normality of the data transfer route including up to another IPC by comparing the data returned to. According to this, as described above, when adding a new CPU, it is effective in diagnosing the normality of the operation of the added CPU.

FIG. 11 is a diagram showing an operation sequence example of the data return command in the own IPC. The following operations
This is performed by the loopback control unit 28. The sequence will be described below.

The test data is prepared in the main memory device MM. The number of words of test data is set in the own word number count register WCR in the own IPC.

The storage address of the test data is set in the own memory address register MAR in the own IPC. The storage address of the returned data is set in #MAR in the own IPC.

Own instruction control register CM in own IPC
Set the loopback command in its own IPC bus to R. At this time, the IPC starts data folding. The own IPC fetches the MM test data into the data buffer register DBR and transfers it from the DBR to the SBR.
The data is returned from the SBR to the RBR, and the returned data is stored again from the RBR to the address of the MM indicated by #MAR via the DBR. This operation is automatically executed until WCR = 0, and when WCR = 0, the command end is C
Notify C.

The own IPC diagnoses the normality of the own IPC by comparing the test data with the folded data. The diagnosis result is displayed in the self-status display register DSR.

According to this embodiment, the other memory address register (#MA) in the other transfer register group 21B is used.
R) can be set from its own device, and
By providing a control circuit for controlling the MAR and using #MAR as a register for setting the address of the main memory (MM) when executing the loopback command, M
Data can be sent from any address of M and the return data can be stored at any address.

12 and 13 are diagrams showing an operation sequence example of the data return command in another IPC. FIG.
13 is one sequence, and the connected portions are partially overlapped and shown. The following operation is performed by the turnback control unit 28. The sequence will be described below.

The test data is prepared in the main memory device MM. The number of words of test data is set in the own word number count register WCR in the own IPC.

The storage address of the test data is set in the own memory address register MAR in the own IPC. The storage address of the returned data is set in #MAR in the own IPC.

Own instruction control register CM in own IPC
Set a return command in another IPC bus to R. At this time, the own IPC transfers the contents of the CMR to the CMR (or #CMR) of the other IPC, and simultaneously starts data loopback.

The own IPC fetches the test data of the MM into the data buffer register DBR, and from the DBR to SB.
Transfer to R and transfer from SBR to RBR of other IPC. In the other IPC, the return instruction is confirmed by the CMR (or #CMR), and the own IP is transmitted via the DBR and SBR.
Data is returned to RBR of C.

The own IPC uses the returned data as M
It is stored in the address indicated by #MAR of M. Are automatically executed until WCR = 0, and WCR =
When it becomes 0, the command completion is notified to CC.

The own IPC compares the test data with the folded data, and
Diagnose the normality of the data transfer route to the end. The diagnosis result is displayed in the self-status display register DSR.

According to this embodiment, at the time of data folding back by the folding command, the address of the own memory address register (MA
By setting the content of R) to the content of the self-word count register (WCR), the write address of the folded data can be automatically set.

FIG. 14 is a diagram showing another operation sequence example of the data return command in the own IPC. The following operation is performed by the turnback control unit 28. The sequence will be described below.

The test data is prepared in the main memory MM. The number of words of test data is set in the own word number count register WCR in the own IPC.

The storage address of the test data is set in the own memory address register MAR in the own IPC. Own IPC in own command control register CMR in own IPC
Set the loopback command in the bus. At this time, own IPC
In #MAR, MAR + WCR (or MAR-WCR) is set as the storage address of the folded data, and at the same time, the data folding is started.

The own IPC fetches the test data of MM into the data buffer register DBR, and from the DBR to SB.
Transfer to R, return from SBR to RBR, then DBR again
And is stored in the address indicated by #MAR of the MM.
This operation is automatically executed until WCR = 0,
When WCR = 0, the command completion is notified to CC.

The own IPC diagnoses the normality of the data transfer route of the own IPC by comparing the test data with the folded data. The diagnosis result is displayed in the self-status display register DSR.

According to this embodiment, when the data is folded back by the folding command, the address of the main memory device (MA) is written in #MAR as the address of the main memory.
By setting the content of R) to the content of the self-word count register (WCR), the write address of the folded data can be automatically set.

FIGS. 15 and 16 are diagrams showing another operation sequence example of the data return command in another IPC. FIG. 15 and FIG. 16 are combined into one sequence, and the connected portions are partially overlapped and shown. The following operation is performed by the turnback control unit 28. The sequence will be described below.

Test data is prepared in the main memory MM. The number of words of test data is set in the own word number count register WCR in the own IPC.

The storage address of the test data is set in the own memory address register MAR in the own IPC. Other IPC in own instruction control register CMR in own IPC
Set the loopback command in the bus. At this time, own IPC
In #MAR, MAR + WCR (or MAR-WCR) is set as the storage address of the folded data, and at the same time, the data folding is started.

The own IPC fetches the test data of the main storage device MM into the DBR and transfers the data to the RBR of another IPC via the SBR of the own IPC. In the other IPC, the return instruction is recognized by the CMR (or #CMR), and the own IP is transmitted via the DBR and SBR.
Data is returned to RBR of C.

The own IPC returns the returned data to #M.
It is stored in the address of the main memory MM indicated by AR. The operation from is automatically executed until WCR = 0,
When WCR = 0, the command completion is notified to CC.

The own IPC compares the test data with the returned data, and
Diagnose the normality of the data transfer route to the end. The diagnosis result is displayed in the self-status display register DSR.

According to this embodiment, when the data is folded back by the folding command, the address of the own memory address register (MA
By setting the content of R) to the content of the self-word count register (WCR), the write address of the folded data can be automatically set.

FIG. 17 is an explanatory diagram of a diagnostic embodiment of the own IPC. The same parts as those in FIG. 9 are designated by the same reference numerals.
The operation of this embodiment is as follows. The test data is prepared in the main memory MM.

The storage address of the test data is set in the MAR of the own IPC. A register group return write command for other transfer in the own IPC is set in the CMR of the own IPC.

The own IPC fetches the contents of the MM into the DBR, and passes the SBR of the own IPC to the RBR of the own IPC.
And stores it in any one of the other transfer register groups 21B.

The normality of the other transfer register group is confirmed by reading the other transfer register group 21B stored in and comparing it with the test data on the MM. According to this embodiment, by providing a command for setting the return destination of the return command to an arbitrary register in the other transfer register group 21B, and providing a circuit for setting this command, the other transfer register group The setting of another IPC can be diagnosed within the own IPC.

FIG. 18 is an operation explanatory diagram of another embodiment of the present invention. In this embodiment, software for storing a master / slave setting flag for giving priority to command execution in each device in advance when data transfer request commands are issued from two devices at the same time. It is provided with a register that can be controlled by.

Specifically, as shown in the figure, a master / slave setting bit is provided in the IPC control register SSR. The SSR is a register that is readable and writable by a higher-level device. For example, when the setting bit is "1", the master,
When it is "0", it becomes a slave. When set as the master, the arbitration circuit is configured to have the priority when a conflict occurs with the communication with the partner device.

According to this embodiment, the master / slave setting can be freely changed. FIG. 19 is a diagram showing an example of a normal master setting sequence. This operation is as follows.

The own IPC has IP-bus to other IPC.
The information is transferred via the notification that it has been set as the master. Upon receiving this notification information, the other IPC receives its own S
Referring to SR, if self is set as slave,
The normal response information is returned to the own IPC side.

Upon receiving the normal response information, the own IPC issues a normal termination interrupt to the CPU. FIG. 20 is a diagram showing an operation sequence example when another IPC is set as a master. This operation is as follows. The own IPC transfers information that notifies the other IPC via the IP-bus that it has been set as the master.

Upon receiving this notification information, the other IPC refers to its own SSR and, if it is set as the master, returns abnormal response information to its own IPC side. When the own IPC receives the abnormal response information, the own IPC
SR is returned to the slave and an abnormal interrupt is issued to the CPU.

According to this embodiment, when the self device receives the master setting command, if it is found from the response information from the other device via the bus that the other device is already set as the master, the master setting is immediately performed. By canceling
It is possible to prevent both devices from becoming the master.

FIG. 21 is a diagram showing an operation sequence example when the master setting command is simultaneously received. This operation is as follows. Each IPC transfers information to notify the other IPC via the IP-bus that it has been set as a master.

Upon receipt of this notification information, the other IPCs become master settings for both IPCs, so they are configured not to send back the request acceptance signal (ACK) with their own priority, and each device detects a timeout. Then, an abnormal end interrupt is issued to the CPU.

In this case, it is possible to prevent the collision of the master settings from the respective devices. In this case, each device resets the master setting command again.

FIG. 22 is an operation explanatory diagram of another embodiment of the present invention. In this embodiment, when the central control unit (CPU) is duplicated in the 0 system and the 1 system, the IP-system is connected between the 0 system and the 1 system.
The bus is connected to diagnose the normality of the data transfer route of the own system. The procedure of the diagnosis is as follows.

One of the IPCs is set as a master and the other is set as a slave. Then, normal diagnosis is performed in the connection state of FIG.
At this time, since the diagnostic result is written in the same MM, it is necessary that the diagnostic program also supports this.

If necessary, the master and the slave may be reversed and the second diagnosis may be performed. As a result, it is possible to diagnose the normality of the data transfer route in its own IPC before adding a processor.

FIG. 23 is a diagram for explaining the operation of another embodiment of the present invention. In this system, when there are a plurality of IPCs in the same system, one IPC is used as the 0 system and the other IPC is used as the 1 system, and the 0 system and the 1 system are connected by the IP-bus for diagnosis. The diagnostic procedure is as follows.

One of the IPCs is set as a master and the other is set as a slave. Then, normal diagnosis is performed in the connection state of FIG.
At this time, since the diagnostic result is written in the same MM, it is necessary that the diagnostic program also supports this.

If necessary, the master and the slave may be reversed and the diagnosis may be performed again. As a result, it is possible to diagnose the normality of the data transfer route in its own IPC before adding a processor.

[0117]

As described above in detail, according to the present invention, the data transfer register group of its own device (self transfer register group) and the data transfer register group of the other device (other transfer register). Group) and two groups of data transfer register groups. That is, I
One of the devices is transferring data by managing the control register group so that the PC transfer uses the own transfer register group for data transfer and the other IPC uses the other transfer register group for data transfer started. When there is a data transfer request from the other device or when the data transfer requests from both devices collide with each other, the later or inferior transfer request is saved in the data transfer register group, There is no need to reset the transfer request, the time required for software processing is short, and the data transfer capability is not reduced.

In this case, in the self-transfer register group 21A, the status display registers for displaying the status and failure contents of the device are provided for the self device (DSR) and for the other device (MDSR), respectively. If the DSR of the device changes, the DSR of the device itself is added to the MDSR of another device as necessary.
By providing a circuit that transfers the contents of SR, it is possible to determine where the failure occurs.

Further, the other transfer register group 21
In B, a status display register (#MDS) for displaying the status of the other device in operation and the content of the failure that occurred while the other device was operating.
By providing R), failure analysis can be performed regardless of the transfer requested by either device.

Further, the self-transfer register group 21
By setting a command for data wrapping within its own device and a data wrapping within another device as a diagnostic command in its own command control register (CMR) in A, and by providing a wrapping control section for realizing these wrapping tests, it is possible to execute once. The IPC data route can be diagnosed with the return command.
As a result, when an IPC failure occurs, it is possible to determine whether it is the own device or another device.

In addition, a transmission data buffer register (SBR) and a reception data buffer register (RBR) are provided in the data buffer control unit 24, and when the own device data return command is set, the return control unit Data loopback diagnosis can be performed by simultaneously inputting the data output from the device itself via the bus driver.

The other transfer register group 21
The other memory address register (#MAR) in B can be set from its own device, and a control circuit for controlling this #MAR is provided so that when executing the loopback command, the address of the main memory device (MM) is set. By using #MAR as a register for setting, it is possible to send data from any address of the MM and store the return data at any address.

When data is returned by the return command, the address of the main memory to be written in #MAR is set to the content of its own memory address register (MAR) plus the content of its own word count register (WCR). As a result, the write address of the return data can be automatically set.

The return destination of the return command is
By providing a command for setting an arbitrary register in the other transfer register group 21B and providing a circuit for setting this command, the setting of another IPC of the other transfer register group can be diagnosed in the own IPC. it can.

Software for storing a master / slave setting flag for giving a command execution priority right to each device in the case where a data transfer request command is issued from two devices at the same time. The master / slave setting can be freely changed by providing a register controllable by.

When the own device receives the master setting command, if it is found from the response information from the other device via the bus that the other device is already set as the master, the master setting is immediately stopped. It is possible to prevent both devices from becoming the master.

Further, in the case where the device is duplicated into the 0-system and the 1-system, the 0-system bus and the 1-system bus are interconnected, and one of them is set as the master and the other is set as the slave, and the 0-system and the 1-system are set.
Communication is enabled between the systems, and the diagnostic program is executed between the 0-system and 1-system devices. As a result, it is possible to diagnose the normality of the data transfer route in its own IPC before adding a processor.

As described above, according to the present invention, it is possible to provide an interprocessor communication device capable of reliably transferring data between both devices.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a diagram showing an operation sequence example when data transfer requests from both IPCs collide.

FIG. 3 is a diagram showing an operation sequence example when data transfer requests from both IPCs collide.

FIG. 4 is a diagram showing an operation sequence example when a data transfer request is made from one IPC while another IPC is transferring the data.

FIG. 5 is a diagram showing an example of an operation sequence when a data transfer request is made from one IPC while another IPC is transferring the data.

FIG. 6 is a configuration block diagram showing a main part of one embodiment of the present invention.

FIG. 7 is a diagram showing an example of an operation sequence of the embodiment shown in FIG.

FIG. 8 is an explanatory diagram of a data folding operation according to the present invention.

FIG. 9 is an explanatory diagram of a self-IPC data loopback command.

FIG. 10 is an explanatory diagram of another IPC data loopback command.

FIG. 11 is a diagram showing an operation sequence example of a data return command in the own IPC.

FIG. 12 is a diagram showing an operation sequence example of a data loopback command in another IPC.

FIG. 13 is a diagram showing an operation sequence example of a data return command in another IPC.

FIG. 14 is a diagram showing another operation sequence example of a data return command in own IPC.

FIG. 15 is a diagram showing another operation sequence example of a data return command in another IPC.

FIG. 16 is a diagram showing another operation sequence example of a data return command in another IPC.

FIG. 17 is an explanatory diagram of a diagnosis example of self IPC.

FIG. 18 is an operation explanatory diagram of another embodiment of the present invention.

FIG. 19 is a diagram showing an example of a normal master setting sequence.

FIG. 20 is a diagram showing an example of an operation sequence when another IPC is set as a master.

FIG. 21 is a diagram showing an example of an operation sequence when the master setting command is simultaneously received.

FIG. 22 is an operation explanatory diagram of another embodiment of the present invention.

FIG. 23 is an operation explanatory diagram of another embodiment of the present invention.

FIG. 24 is a conceptual diagram of a conventional system.

FIG. 25 is a diagram showing an operation sequence of a conventional system.

FIG. 26 is a diagram showing an operation sequence of a conventional system.

[Explanation of symbols]

 11 IP-bus 20 Inter-Processor Communication Device (IPC) 21 Control Register Unit 21A Self Transfer Register Group 21B Other Transfer Register Group 22 Control Register Control Unit 23 IPC Interface Control Unit 24 Data Buffer Control Unit 25 DMA Control Circuit 26 Address Bus 27 data bus

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yu Fukuda 3-9-18 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa Prefecture Fujitsu Communication Systems Limited (72) Inventor Shigeaki Kawamata 3 Shin-Yokohama, Kohoku-ku, Yokohama, Kanagawa Prefecture Inc. 9-18 No. Fujitsu Communication Systems Ltd. (72) Inventor Noko Higuchi 3-9-18 Shin-Yokohama, Kohoku Ward, Yokohama City, Kanagawa Prefecture Inc. Fujitsu Communication Systems Ltd. (72) Inventor Jun Roppongi Kanagawa 3-9-18 Shin-Yokohama, Kohoku-ku, Yokohama-shi, FUJITSU Communication Systems Limited

Claims (11)

[Claims] 1. A device for transferring data such as a DMA transfer and a register between two central control devices via a bus, and a data transfer register group (own transfer register group) of the own device. It manages the data transfer register group (other transfer register group) of the other device, the register group currently operating and the register group currently set, and while one device is transferring data, the other device transfers data. A control register control unit that stores a later or inferior transfer request in the data transfer register group when there is a request or when data transfer requests from both devices collide; and the control register control unit. The interface system is connected to the other device and issues a data transfer request to the other device and receives an acknowledge from the other device. Parts and are controlled by the interface control unit outputs, interprocessor communication apparatus characterized by comprising a data buffer control unit, the sending and receiving of data between the devices. 2. A status display register for displaying the status and failure content of the device is provided in the self-transfer register group for the self device (DSR) and for the other device (MDSR) respectively, and the DSR of the self device is 2. The interprocessor communication device according to claim 1, further comprising a circuit for transferring the contents of the DSR of the own device to the MDSR of the other device if necessary. 3. A status display register (#MDSR) is provided in the other transfer register group for displaying the status of another operating device and the details of a failure that occurred while the other device was operating, and which device requested 3. The interprocessor communication device according to claim 2, wherein the failure analysis can be performed even with the transferred data. 4. A self-instruction control register (CMR) in the self-transfer register group is set with commands for data wrapping within its own device and data wrapping within another device as diagnostic commands, and these wrapping tests are realized. The interprocessor communication device according to claim 1, further comprising a loopback control unit. 5. A data buffer register for transmission (SBR) and a data buffer register for reception (RBR) are provided in the data buffer control unit, and when the data loopback command in the own device is set, the loopback control unit is in the own device. 5. The interprocessor communication device according to claim 4, wherein the data output by the processor is simultaneously input via a bus driver. 6. The other memory address register (#MAR) in the other transfer register group can be set from its own device, and a control circuit for controlling this #MAR is provided to execute the loopback command. The main memory (M
6. The interprocessor communication device according to claim 5, wherein #MAR is used as a register for setting the address of M). 7. When returning data by a return command, the address of the main memory to be written to #MAR is set to the content of its own memory address register (MAR) plus the content of its own word count register (WCR). 7. The interprocessor communication device according to claim 6, wherein 8. The processor according to claim 4, further comprising a command for setting a return destination of the return command to an arbitrary register in the other transfer register group, and a circuit for setting the command. Intercommunication device. 9. Software for storing a master / slave setting flag for giving a command execution priority right to each device in the case where a data transfer request command is issued from two devices at the same time. 2. The interprocessor communication device according to claim 1, further comprising a register controllable by. 10. When the self device receives the master setting command, if it is found from the response information from the other device via the bus that the other device is already set as the master, the master setting is immediately stopped. 10. The interprocessor communication device according to claim 9. 11. When a device is duplicated into a 0-system and a 1-system, a 0-system bus and a 1-system bus are interconnected,
11. One of the devices is set as a master and the other is set as a slave to enable communication between the 0-system and the 1-system, and the diagnostic program is executed between the devices of the 0-system and the 1-system. An inter-processor communication device according to claim 1.