JPH08124800A - Capacitor array - Google Patents

Abstract

PURPOSE: To provide a capacitor array capable of reducing crosstalk, regarding a capacitor array wherein a plurality of individual inner electrodes and common inner electrodes are formed inside dielectrics via a dielectric layer. CONSTITUTION: Individual inner electrodes 2a-2f are divided into groups for a plurality of electrodes. Common inner electrodes 3a, 3b which inclusively face the whole group are divided and arranged in each of the groups. The divided and arranged common inner electrodes 3a, 3b are connected, on outer electrodes 5a, 5b of dielectric side surfaces.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is constructed by stacking layers by a film forming method such as a sheet method or a printing method, and a plurality of individual internal electrodes are opposed to each other in a dielectric body through a dielectric layer common to them. And a common internal electrode for forming a plurality of capacitors therein.

[0002]

2. Description of the Related Art A capacitor array has a large number of capacitors built in one chip. Therefore, when a large number of capacitors are required, only one chip is needed, and the mounting cost and the area occupied by the board are reduced. It is advantageous. As such a capacitor array, as disclosed in Japanese Utility Model Laid-Open No. 1-79817, the comb-shaped internal electrodes are individually formed with respect to the individual internal electrodes arranged like a comb in a dielectric. There is one in which these common internal electrodes are faced to each other and are drawn out to the side surface of the dielectric through a common internal conductor pattern and connected to the external electrodes.

FIG. 4A is a perspective view of a conventional capacitor array developed by the present inventors, FIG. 4B is a sectional view taken along line EE of FIG. 4A, and FIG. ) Is a cross-sectional view taken along line FF in FIG. This capacitor array is not a comb-shaped one with respect to the individual internal electrodes 2a to 2f formed in the dielectric body 1 but a rectangular plate-shaped common internal that generally opposes the entire individual internal electrodes 2a to 2f. Electrode 3
And the individual internal electrodes 2a to 2f are connected to the individual external electrodes 4a to 4f on the two opposite side surfaces of the dielectric 1, and the common internal electrode 3 is the common external electrode 5a on the other two opposing side surfaces. 5b.

FIG. 5 is a diagram showing a manufacturing process of the capacitor array shown in FIG. 4 by the sheet method for one chip. As shown in FIG. 5A, a required number of dielectric sheets 1a are laminated. Then, as shown in FIG. 5 (B), the dielectric sheet 1b is overlaid with the individual internal electrodes 2a to 2f formed by printing or the like, and the dielectric sheet 1b is covered with a dielectric material as shown in FIG. 5 (C). A sheet having the common internal electrode 3 formed thereon is stacked on the sheet 1c, and then a dielectric sheet 1d having the individual internal electrodes 2a to 2f formed thereon is stacked (FIG. 5 (D)), and a necessary number of dielectrics are further formed thereon. The sheets 1e are overlaid, subjected to steps such as pressurization, cutting and firing, and then the external electrodes 4a to 4
The f, 5a, and 5b are formed by baking, plating, or the like. The capacitor circuit configured as described above is represented as shown in FIG.

[0005]

However, the above-mentioned actual Kaihei 1
In a capacitor array disclosed in Japanese Patent Laid-Open No. 79817/1998, in which a comb-shaped common internal electrode is connected to a common external electrode via an internal conductor pattern, individual electrodes are formed on the internal conductor pattern of the common internal electrode. Current flows in common, and the line width of the inner conductor pattern becomes narrower, so that the loss in the inner conductor pattern increases, so that Q decreases and crosstalk (when a signal comes to one element, the signal There is a problem that a phenomenon that a part of the element leaks and is transmitted to another element that has not come. Also,
In order to prevent such a decrease in Q, it is necessary to form the internal conductor pattern with a large thickness, which leads to an increase in the size of the chip.

On the other hand, the capacitor array shown in FIG.
Since the common internal electrode 3 is formed to have a width that generally opposes all the individual internal electrodes 2a to 2f, the flow passage cross-sectional area of the common internal electrode 3 becomes large, and the problem of the decrease in Q is alleviated. Although thinning can be achieved, crosstalk still occurs, and especially crosstalk at a high frequency of several tens of MHz or more becomes remarkable. Crosstalk like this
On the side where the signal leaks, the unnecessary signal is noise, which is noise. Such noise causes malfunction of the device.

In view of the above problems, it is an object of the present invention to provide a capacitor array capable of reducing crosstalk.

[0008]

In order to achieve the above object, the present invention provides a plurality of individual internal electrodes inside a dielectric,
In a capacitor array in which a common internal electrode is formed via a dielectric layer, the individual internal electrodes are grouped into a plurality of electrodes, and a common internal electrode that is generally opposed to the entire group is provided for each group. While arranging separately
It is characterized in that the divided common internal electrodes are connected at the external electrodes on the side surface of the dielectric.

[0009]

In the present invention, by providing a common internal electrode that is generally opposed to a group of a plurality of individual internal electrodes, it is possible to secure the cross-sectional area of the current of the common internal electrode and to reduce the loss in the common internal electrode. The increase can be prevented. Moreover, since the common internal electrodes are divided for each group, crosstalk between the individual internal electrodes of different groups is reduced.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1A is a perspective view showing an embodiment of a capacitor array according to the present invention, and FIG.
Sectional drawing, (C) is a BB sectional view of (B). This embodiment is different from the conventional example in that the individual internal electrodes 2a to 4c are connected to the individual external electrodes 4a to 4c arranged on one side surface (long side) of the rectangular capacitor array. 2c group and individual external electrodes 4a-4
Individual external electrodes 4d provided on the side surface (long side) opposite to c
The common internal electrodes are divided into groups of individual internal electrodes 2d to 2f which are respectively connected to 4f, and are opposed to each of these groups as a whole (that is, they are not individually opposed to each other in a comb shape). 2 formed into a strip
It is divided into book electrodes 3a and 3b. Then, the common external electrodes 5a and 5b on the short sides of the array are connected in common with both ends of these common internal electrodes 3a and 3b.

FIG. 2 is a diagram showing the manufacturing process drawn corresponding to FIG. 5, and the point that the common internal electrodes 3a and 3b of FIG. 2C are formed on the dielectric sheet 1c. Different from the conventional example.

FIG. 3 is a diagram showing a comparison of the crosstalk between this embodiment and the conventional example. In the capacitor array of the embodiment in which this crosstalk is measured, Pd is used for the electrodes and the barium titanate-based dielectric is used for the dielectric. The vertical and horizontal dimensions are 6.3 mm ×
In a capacitor array having a thickness of 3.2 mm and a thickness of 1.0 mm, the width a of the common internal electrodes 3a and 3b shown in FIG. 1 (B) is 1.2 mm, and the distance b between the common internal electrodes 3a and 3b is 0.2.
mm, individual internal electrodes 2a-2f and common internal electrodes 3a, 3b
The distance c between the and is set to 10 μm. On the other hand, in the conventional capacitor array of FIG. 4, the width d of the common internal electrode 3 is 2.6.
mm, and the others were the same as in this example. In FIG. 3, the crosstalk between the individual internal electrodes 2a and 2f adjacent to each other is drawn corresponding to the frequency.
In contrast to the crosstalk of about -40 dB at MHz, the crosstalk is about -55 dB in this embodiment, and the crosstalk is reduced by about -15 dB. The crosstalk between the individual internal electrodes 2a-2b in this example, that is, between the same groups, was the same as in the conventional example.

Since the common internal electrodes 3a and 3b are provided so as to be generally opposed to each other so as to cover the group of a plurality of individual internal electrodes, crosstalk between different groups is reduced. The loss can be reduced as compared with the conventional example in which a plurality of comb-shaped common internal electrodes are connected to the external electrodes via the internal conductor patterns. Also,
Since the portions without the common internal electrodes 3a and 3b are coupled by the upper and lower dielectrics, the coupling is strengthened, the dielectric sheets are unlikely to be separated from each other, and a chip having high strength can be provided.

In the present invention, the individual internal electrodes 2a to 2f are used.
The number and the number of layers in the same layer are variously selected according to the purpose.

[0015]

According to the present invention, since a plurality of common internal electrodes are divided into groups and the common internal electrodes are divided into groups, it becomes difficult for signals to propagate between the groups, and crosstalk between the groups is prevented. It can be reduced, and overall, crosstalk can be reduced. In addition, since the common internal electrodes are provided so as to face each other in a group-wise manner, the flow passage cross-sectional area is secured, the loss is reduced, and the conventional internal electrodes are formed in a comb shape facing the individual internal electrodes. By comparison, the Q value can be improved. Further, as compared with the structure in which the common internal electrodes are not divided, the common internal electrodes corresponding to the groups are coupled by the dielectric, so that a chip having high strength can be provided.

[Brief description of drawings]

FIG. 1A is a perspective view showing an embodiment of a capacitor array according to the present invention, FIG. 1B is a sectional view taken along the line AA, and FIG.
FIG. 3B is a sectional view taken along line BB of FIG.

FIG. 2 is a diagram showing an example of a manufacturing process of the present embodiment.

FIG. 3 is a diagram showing crosstalk characteristics of the present example and a conventional example in comparison.

4A is a perspective view showing a conventional capacitor array, FIG. 4B is a sectional view taken along line EE of FIG. 4C, and FIG.
F sectional view, (D) is an equivalent circuit diagram.

FIG. 5 is a diagram showing a manufacturing process of a conventional example.

[Explanation of symbols]

1: Dielectric material, 2a-2f: Individual internal electrodes, 3a, 3b:
Common internal electrodes, 4a to 4f: individual external electrodes, 5a, 5
b: Common external electrode

Claims (1)

[Claims] 1. A plurality of individual internal electrodes inside a dielectric,
In a capacitor array in which a common internal electrode is formed via a dielectric layer, the individual internal electrodes are grouped into a plurality of electrodes, and a common internal electrode that is generally opposed to the entire group is provided for each group. While arranging separately
A capacitor array in which common internal electrodes arranged in a divided manner are connected at external electrodes on a side surface of a dielectric.