JPH0812640B2 - Address translation method and apparatus - Google Patents

Description

The present invention relates to a computer system including a virtual storage device, and more particularly to an address conversion method suitable for effectively using a real storage device.

[Conventional technology]

One of the typical conventional address conversion methods, a segment table and a page table, is used to convert a virtual address into a real address. [For example, "HITAC M
Series processor (manufactured by Hitachi Ltd.) M / EA mode ”8080-
2-083 pp.47-53] This method is particularly excellent for efficient use of real memory. For example, for pages that are unlikely to be referred to, turn on the real page fault bit in the page table. This enables real pages to be dynamically deleted from the real storage device, and for segments that are unlikely to be referenced, the segment table bit in the segment table is turned on to dynamically create the page table. It can be deleted from memory.

[Problems to be solved by the invention]

However, in recent years, due to the development of hardware and computer architecture, the capacities of real memory devices and virtual memory devices have increased dramatically, and tend to expand to several GB (Giga Byte) to several hundred GB. On the other hand, since the page size remains the same as the conventional one, the management cost of the storage device such as the memory capacity of the address translation table and the processor time required for the search rapidly increases with the increase of the number of pages. In particular, if the same memory allocation for each page is performed for a job that requires a huge storage area, the memory capacity required for the conversion table becomes enormous.

By increasing the page size, these management costs are reduced. On the other hand, however, memory fragmentation reduces memory utilization efficiency. Furthermore, changing the page size is not easy given the compatibility of existing software, especially operating systems.

An object of the present invention is to improve the multiplicity of jobs and the throughput of the system by maintaining the compatibility with the prior art while reducing the above-mentioned management cost to effectively utilize the storage device.

[Means for solving problems]

In order to achieve the above-mentioned object, in the present invention, for a segment to which a continuous area in a real storage device is allocated,
The real address is generated directly from the segment table and the displacement within the segment, and the page table is omitted.

Further, in such a virtual memory information system, the present invention preferably uses a page table for the segment table entry in order to be able to simultaneously handle both the conventional address translation in units of pages and the above-mentioned address displacement in units of segments. An E bit indicating that the address is not set is provided so that the two address conversion methods can be switched in segment units. That is, at the time of address translation,
If the E bit in the segment table entry corresponding to the virtual address is ON, the real address is generated from the address in the entry and the displacement in the segment. And E
If the bit is off, the page table is used as before to generate the real address.

[Action]

According to the present invention, when allocating a real storage device having continuous segment sizes, the page table is not required, so that the real storage device can be effectively used, and the multiplicity of jobs and the system throughput can be improved. You can

Further, since it is possible to switch between the segment-based address conversion and the conventional page-based address conversion for each segment, it is possible to handle both address conversions simultaneously in one job and maintain compatibility with existing programs.

Example of Invention

The present invention will be described in detail below with reference to the drawings. FIG. 3 shows the positioning in the computer system of the present invention. When executing an instruction, the CPU 10 sets the instruction address or operand address in the logical address register LAR11. This address is a dynamic address translation mechanism DAT2
The real address is converted to a real address by 0, and the obtained real address is sent to the real storage controller SCU30,
Get more corresponding data.

The DAT 20 generally comprises an address translation mechanism 22 for translating a logical address into a real address based on an address translation table, and an associative memory device TLB 21 for the purpose of speeding up the translation. The present invention relates to this DAT.

FIG. 2 shows a virtual storage device VS50, a real storage device MS40, and an address conversion table for associating them with each other. The address translation table includes a segment table origin register STOR12 that points to the segment table of the virtual storage space, a segment table SGT221, and a page table PGT222 that points to the entry of the segment table. The entry of the SGT 221 is provided with an E bit indicating information as to whether or not address conversion in segment units is performed. When the E bit is 0 (off), a real storage device is assigned to the segment corresponding to the entry in page units, and address conversion is performed in page units to index the conventional page table. When the E bit is 1 (ON), the segment corresponding to the entry is assigned a real storage device in segment units and directly maps to the real segment 41 of the MS 40 without using the page table. As a result, the page table of the segment in which the E bit is on can be omitted. Since the conversion table is placed on the MS 40, the present invention can reduce the overhead of the real storage device. Further, since the address conversion table is referenced only once, the processing overhead required for the conversion can be reduced.

Next, an address conversion method using the address conversion table will be described. FIG. 6 shows registers necessary for address conversion, and FIG. 1 shows a flow of conversion. The logical address is set to LAR, but the meaning of the field is different when converting into segment units and when converting into page units. FIG. 6 (a) shows the meaning of the LAR field when the page is used as a conversion unit. L
Segment number S # 111 and page number P # 1 from the top of AR
There are 12 and in-page displacement DP113 fields. On the other hand, the LAR field when the segment is used as a unit is as shown in Fig. 7 (b '), which means that the highest is the segment number and the lower is the intra-segment displacement DS11.
4 The segment table entry has a field as shown in FIG. 9C, and is composed of an address PGTA221-a and an E bit 221-2b. The content of PGTA 221-a is the address of the corresponding page table when the E bit 221-b is 0 (off), and the address of the corresponding real segment when the E bit 221-b is 1 (on). Further, the page table entry (d) in the figure has a real page address RPGA222-a.

Next, FIG. 1 shows the flow of address conversion. When a request for address translation is generated, first, 223-a
At, the start address of the segment table is obtained from STOR12, and the value obtained by multiplying S # 111 by the size of the segment table entry is added to obtain the real address of the corresponding segment table entry. By giving this real address to the SCU 30, the segment table entry is obtained. Next, at 223-b, the E bit of the segment table entry is checked, and if 0 (off), the processing at 223-c is performed. In 223-c, since the address conversion is performed in page units, the real address of the corresponding page table entry is obtained by adding the value obtained by multiplying PGTA 221-a and P # 112 by the page table entry size. By giving this address to the SCU 30, the page table entry is obtained. Then, the actual address is obtained by adding RPGA222-a and DP in 223-d.

On the other hand, if the E bit is 1 (ON) in the process of 223-b, the process of 223-e is performed. 223-e, the segment table entry PGTA221-a and the intra-segment displacement DS1
Calculate the real address by adding 14.

Next, the structure of the TLB for supporting the E-bit will be described. FIG. 4 shows an example of the structure of a TLB that supports E-bit. The TLB 21 outputs the real address RA by inputting STOR12, the segment number S # of the logical address LAR and the page number P #. An E bit is provided for each TLB entry. E at TLB index
If the bit is 0 (off), the logical product circuit 221-b becomes active, the in-page displacement DP becomes an input to the adder 212, and RA which is the output of TLB is added to generate an actual address.

On the other hand, when the E bit is 1 (on), the AND circuit 221-
a becomes active, and the intra-segment displacement having the P # and DP fields of the logical address as the upper part and the lower part, respectively, becomes an input to the adder 212, and is added to RA which is the output of TLB to generate a real address.

If there is no entry corresponding to the TLB, the address translation request 23 by the translation table is turned on, and the address translation by the above translation table is performed. When this conversion is completed, the information of the segment table entry and page table entry is set in the TLB. For the real address field, when the E bit is 0 (off), RPGA22
When 2-a is 1 (on), PGTA221-a is set.

By the way, in the TLB configuration shown in FIG. 4, since entries are in page units, entries are uselessly used even in allocation in segment units. Therefore, this problem is solved by providing two TLBs for each segment and each page. FIG. 5 shows the structure of this TLB. The TLB21-a has entries in page units, and the TLB21-b has entries in segment units. The input of TLB21-a is the segment number S # and page number P # of STOR2 and logical address 11, and the output RA is the real page address. When there is a matched entry with the input, the output RA of the TLB 21-a and the intra-page displacement DP become the input of the adder 212-a, and the real address is generated.

On the other hand, if there is a matched input with the entry of TLB21-b, the output RA of TLB21-b and the P of logical address LAR11.
The intra-segment displacement having the # and DP fields as the upper part and the lower part, respectively, becomes an input to the adder 212-b,
A real address is generated.

When there is a logical address that does not match in any TLB, the AND circuit 231 is turned on and the conversion request 23 by the address conversion table is turned on. The conversion by the address conversion table is as described above. After this conversion is complete, the segment table entry and page table entry information is set in the TLB. However, when the E bit is 1 (on), the AND circuit 241-b is turned on and the information is set only in the TLB 21-b. When the E bit is 0 (off), the AND circuit 241
-A is turned on, and information is set only in TLB21-a. This ensures that the entries in both TLBs are unique.

The effect of deleting the page table will be described below.
If the size of a segment is 1 MB, the size of a page is 4 KB, and the size of a page table entry is 16 B, then a page table of 4 KB is required for each segment. Now, assuming that the virtual memory area of Job is S (MB), the multiplicity of Job is n, and the size of the real memory device is M (MB), paging and swapping are ignored for the sake of simplification. If storage is allocated, (S / 256
+ S) · n = M, that is, S · n = 256/257 · M. If there is no page table, S · n = M, so that the present invention makes it possible to effectively use an actual storage device having a size of M / 257. That is, if M has a size of 257 GB, one job having a virtual storage area of 1 GB can be placed on the real storage device. Since the size M of the real storage device is expected to increase dramatically in the future, the effective use of the real storage device according to the present invention will greatly increase the multiplicity of the job and the throughput of the system.

〔The invention's effect〕

According to the present invention, since the page table is omitted for the segment to which the real storage devices having continuous segment sizes are allocated, the real storage device can be effectively used, and the multiplicity of jobs and the system throughput can be improved. Can be improved.

[Brief description of drawings]

FIG. 1 is a processing flow chart showing an embodiment of a translation system of the present invention, FIG. 2 is a block diagram of an address translation table, FIG. 3 is a block diagram for explaining the positioning of the present invention, FIGS.
FIG. 6 is a block diagram showing a configuration example of a TLB that supports E-bits, and FIG. 6 is an explanatory diagram illustrating the contents of registers required for address translation. 10 ... CPU, 11 ... Logical address register, 12 ... Segment table origin register, 20 ... Dynamic address translation mechanism, 21 ... TLB, 22 ... Translation table address translation, 30 ... Storage controller , 40 …… Real storage device,
50 ... Virtual storage device, 41 ... Real segment, 42 ... Real page, 51 ... Virtual segment, 52 ... Virtual page, 221
…… Segment table, 222 …… Page table.

Claims (7)

[Claims] 1. A segment consisting of a plurality of pages and a virtual storage space consisting of the plurality of segments are configured on a real storage device, and a segment table corresponding to the virtual storage space and a page table corresponding to the segment. In a virtual memory information processing system that performs address translation from a virtual address to a real address using, selecting whether the address translation unit for the segment to which the virtual address belongs is a segment unit or a page unit, and the selection result is a segment unit , Generating a real address from the displacement in the segment of the virtual address and the address specified in the entry corresponding to the segment of the segment table, and if the selection result is in page units, the page table of the segment corresponding to the segment Address the segment table Of the segment corresponding to the segment, the real address is generated from the address designated in the entry corresponding to the page to which the virtual address of the page table belongs and the displacement of the virtual address within the page. Address translation method. 2. The address translation method according to claim 1,
The address conversion method, wherein in the step of selecting the address conversion unit, the address conversion unit is selected based on information stored in the entry of the segment table. 3. The address conversion method according to claim 1,
Before performing the address translation from the virtual address to the real address using the segment table and the page table, the TLB entry corresponding to the virtual address is obtained in the address translation buffer (TLB), and the segment to which the virtual address belongs Is selected as the unit of address translation for segment or page, and when the selection result is the unit of segment, the real address of the virtual address is generated from the displacement of the virtual address in the segment and the real address in the TLB entry. If the selection result is in page units, the real address of the virtual address is generated from the displacement of the virtual address within the page and the real address in the TLB entry. 4. The address translation method according to claim 3, wherein in the step of selecting the address translation unit at the time of address translation using the TLB, the address translation unit is selected based on the information stored in the TLB entry. An address translation method characterized by the above. 5. The address translation method according to claim 1,
The virtual memory information processing system, as an address translation buffer (TLB), places a correspondence between virtual addresses and real addresses for performing the address translation in the segment unit as a first TLB.
And a second TLB in which only the correspondence between the virtual address and the real address for performing the address conversion in the page unit is set, and the address translation from the virtual address to the real address is performed using the segment table and the page table. Before, the TLB entry corresponding to the virtual address of the address translation target is obtained in the first TLB and the second TLB, and when the obtained TLB entry is the entry of the first TLB,
The displacement within the segment of the virtual address and the TLB
If the real address of the virtual address is generated from the real address in the entry and the obtained TLB entry is the entry of the second TLB,
An address translation method, wherein a real address of the virtual address is generated from a displacement of the virtual address within the page and a real address in the TLB entry. 6. The address translation method according to claim 5, wherein when the TLB entry is not found in the step of obtaining the TLB entry, after the address translation is performed using the segment table and the page table, the address According to the result of the step of selecting a translation unit, if the address translation unit for the segment to which the virtual address belongs is a segment unit, the first TLB
An entry corresponding to the segment is registered in, and when the address translation unit for the segment to which the virtual address belongs is page unit, the entry corresponding to the page to which the virtual address belongs is registered in the second TLB. Address translation method. 7. A segment composed of a plurality of pages and a virtual memory space composed of the plurality of segments are configured on a real memory, and a segment table corresponding to the virtual memory space and a segment table entry in the segment table are provided. In a virtual memory information processing system that performs page-based address conversion for generating a real address from a virtual address using a designated page table, a single continuous area in the real memory device is assigned to the segment. Means for designating an address of the continuous area in the corresponding segment table entry, and an address and a virtual address of the continuous area designated in the corresponding entry in the segment table for the segment to which the continuous area is allocated Generate real address from displacement in segment Address converting apparatus characterized by comprising means for performing address translation segment units.