JPH0812920B2 - Lateral conductivity modulation type MOSFET and control method thereof - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a lateral conductivity modulation type MOSFET which supplies a base current of a lateral bipolar transistor by a channel current of the MOSFET and a control method thereof.

[Conventional technology]

Since the conductivity modulation type MOSFET is also called an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor), it is abbreviated as an IGBT hereinafter. IGBTs are known as voltage-driven bipolar devices, and were initially developed as vertical devices, and more recently horizontal IGBTs have been developed. This is because the vertical IGBT has a current flowing between the front and back surfaces of the semiconductor substrate, whereas the horizontal IGBT has
Is formed by using only one side of the semiconductor substrate, so that it can be easily incorporated into the substrate and can be easily connected to an integrated circuit in the same substrate.

FIG. 2 shows a conventional lateral N-channel IGBT, in which a P ^{+ +} layer 3 is formed on the surface of a P well 2 provided on one surface of an N ⁻ substrate 1.
And an N ⁺ source layer 4 in contact therewith, and a source electrode 5 connected to the source terminal S is in contact with both layers. A polycrystalline silicon gate electrode 7 is provided between the source layer 4 and the N ⁻ substrate region 1 via a gate oxide film 6 and connected to the gate terminal G. An N ⁺ buffer layer 9 surrounding the P ⁺ drain layer 8 is arranged at a distance from the P well layer 2, and the drain electrode 10 connected to the drain terminal D is in contact with the P ⁺ layer 8. In this IGBT, a voltage is applied to the gate electrode 7 to invert the surface of the P layer 2 immediately thereunder to form an N channel, and electrons are transferred from the N ⁺ source layer 4 to the N ⁻ layer 1
To be introduced. Accordingly, holes are transferred from the P ⁺ layer 8 on the drain side to the N ⁻ through the N ⁺ buffer layer 9 so as to satisfy the neutral condition.
Introduced in layer 1. In this way, carriers are accumulated in the N ⁻ layer 8 to cause conductivity modulation.

FIG. 3 is a potential barrier diagram, which illustrates a path in which holes 31 are introduced from the drain P ⁺ layer 8 to the N ⁻ layer 1 through the N ⁺ buffer layer 9. Conventionally, the potential barrier of holes from the P ⁺ drain layer 8 to the N ⁺ buffer layer 9 is controlled by changing the specific resistance of the N ⁺ buffer layer 9, that is, the Fermi level. Specifically, increasing the specific resistance of the N ⁺ buffer layer lowers the potential barrier, and decreasing the specific resistance increases the potential barrier.

[Problems to be Solved by the Invention]

In many cases, the IGBT is actually used as a switching element. In this case, it is desired that the conductivity modulation be generated as much as possible in the ON state, that is, the ON resistance be as small as possible. On the other hand, when shifting from the ON state to the OFF state, it is desired to shift to the OFF state as quickly as possible, that is, a fast switching time is required.

In order to meet such requirements, the resistivity and thickness of the N ⁺ buffer layer 9 are taken into consideration, and a lifetime killer is introduced to obtain characteristics. That is, it is the actual situation that the optimum value is determined by adjusting both the degree of conductivity modulation and the method of causing carriers to disappear by the lifetime killer.

Thus, the N ⁺ buffer layer 9 not only functions as a stopper of the depletion layer for holding the breakdown voltage, but also plays a large role in switching the IGBT. But,
The impurity concentration and the thickness of the N ⁺ buffer layer 9 are uniquely determined, and if the lifetime killer is increased under those conditions, the switching time will be faster but the on-resistance will be increased, and if the lifetime killer is reduced. Although the switching time becomes slower, the on resistance becomes smaller, and the switch time and the voltage drop in the on state have a trade-off relationship.

The present invention eliminates this trade-off, causes the conductivity to be modulated in the ON state as much as possible, and the lateral IGBT and the lateral IGBT that realizes the conductivity modulation to be extinguished as quickly as possible when switching to the OFF state. The purpose is to provide a control method.

[Means for solving the problem]

In order to achieve the above object, the present invention provides a first region of the second conductivity type and a second region of the first conductivity type selectively on a surface portion of a substrate of the first conductivity type having a low impurity concentration. The third region of the second conductivity type and the fourth region of the first conductivity type, both of which have a high impurity concentration, are selectively formed on the surface of the first region, and the third region and the The four regions are short-circuited by the source electrode, the gate electrode is provided on the surface of the first region between the fourth region and the substrate region via the oxide film, and the drain electrode is in contact with the surface of the second region. In the lateral IGBT in which the fifth region of the second conductivity type having a high impurity concentration is selectively formed, the extraction electrode is in contact with the second region.
In the ON state, a forward voltage is applied to the PN junction between the second region and the fifth region via the drain electrode and the extraction electrode. In the switching state from on to off, a voltage in the opposite direction is applied to the PN junction between the second region and the fifth region via the drain electrode and the extraction electrode.

[Action]

Since a dedicated extraction electrode is provided in the second region, it is possible to apply a DC voltage between the fifth region, which is the drain layer, and the second region, which is the buffer layer, with an appropriate polarity, and the PN junction between both layers is formed. The potential barrier of can be controlled,
Depending on the ON state, injection of one carrier is facilitated to increase conductivity modulation, and the injection of one carrier and the ejection of the other carrier are controlled according to the switching state from ON to OFF, and conductivity is controlled. It is possible to quickly eliminate the modulation.

〔Example〕

FIG. 1 shows a lateral N-channel IGBT according to an embodiment of the present invention. The layer structure formed in the substrate 1 is the same as that of the conventional example shown in FIG. That is, by diffusion from the surface to the N ⁻ substrate 1 having a specific resistance of 50 to 100 Ω, the P well (first region) 2 having a width of 40 to 50 μm and a surface impurity concentration of 5 × 10 ¹⁶ / cm ³ and a surface impurity concentration of about 10 ¹⁸ / cm ³ N ⁺ buffer layer (second region) 9 is 50 ~
It is formed with a spacing d of 100 μm. P well 2
Is a P ⁺⁺ contact layer (third region) 3 with a depth of 4-5 μm and a surface impurity concentration of 10 ¹⁹ / cm ³ or more due to impurity diffusion from the surface
An N ⁺ source layer (fourth region) 4 having a depth of 1 μm or less and a surface impurity concentration of about 10 ¹⁸ / cm ³ is provided. On the other hand, the N ⁺ buffer layer 9 is also provided with a P ⁺ drain layer (fifth region) 8 having a width of 20 to 30 μm, a depth of 4 to 5 μm, and a surface impurity concentration of about 10 ¹⁹ / cm ³ by diffusion of impurities from the surface. There is. Between the N ⁺ source layer 4 and the N ⁻ substrate 1 exposed on the surface, a gate electrode with a thickness of 1 μm is formed by polycrystalline silicon with an impurity concentration of 10 ¹⁷ / cm ³ through a gate oxide film 6 with a thickness of 1000 Å. It is formed of 7. A drain electrode 10 that further contact with the source electrode 5, P ⁺ drain layer 8 for short-circuiting the both layers in contact with the P ⁺⁺ layer 3 and the N ⁺ source layer 4
In addition to the above, according to the present invention, the extraction electrode 11 which is in contact with the N ⁺ buffer layer is provided. Each electrode is Al or Mo respectively
The source electrode 4 is connected to the source terminal S, the gate electrode 7 is connected to the gate terminal G, and the drain electrode 10 is connected to the drain terminal D. The DC power source 21 is connected between the drain terminal D and the extraction electrode 11. Or 22 is connected.

Next, the control method of this IGBT will be described. For example, in an IGBT to which a voltage of 600 V is applied between the drain and the source, a potential barrier as shown in FIG. 4A is first realized from the viewpoint of causing conductivity modulation in the ON state as much as possible. This is realized by applying a voltage of several to several tens of V from the power source 21 to the PN junction between the N ⁺ buffer layer and the P ⁺ drain in the forward direction. As a result, holes 31 are injected from the P ⁺ drain layer 8 into the N ⁻ layer 1, and N ⁻
Emission of the electrons 32 from the layer 1 to the P ⁺ drain layer 8 becomes easy, and the conductivity modulation can be increased. Therefore, the on-voltage decreases. On the other hand, in the OFF switching state, the potential barrier as shown in FIG. 4B is realized. This is due to the power supply 22 and the N ⁺ buffer layer and P ⁺
It is realized by applying a voltage of several to several tens of V in the reverse direction to the PN junction of the drain. This allows
The injection of the holes 31 from the P ⁺ drain layer 8 to the N ⁻ layer 1 is not only significantly restricted, but also the electrons 32 discharged from the N ⁻ layer 1 to the P ⁺ drain layer 8 are significantly restricted. The switching time can also be made extremely short. For example,
If both DC power supplies 21 and 22 are connected, the IGBTs with the same ON voltage
Switching loss is halved at T. However, it is also possible to connect only one of the DC power supplies 21 and 22 and use only the effect of one.

Although the above-described embodiments have been described with respect to the lateral N-channel IGBT, the same can be applied to a P-channel IGBT in which the conductivity type of each layer is reversed. In this case, the polarity of the DC voltage applied between the drain electrode and the extraction electrode in the ON state and the OFF switching state is opposite to that of the above embodiment.

〔The invention's effect〕

According to the present invention, the extraction electrode is provided in the buffer layer in which the electrode cannot be extracted in the vertical IGBT, and the forward or reverse voltage is applied to the PN junction between the drain layer and the buffer layer between the drain electrodes. Controls the potential barrier and facilitates carrier injection in the ON state,
By limiting the injection of carriers or the discharge of other carriers in the switching state to OFF, it is possible to reduce the ON voltage or the switching time. Moreover, such an effect can be controlled to an arbitrary degree only by the magnitude of the applied voltage, and an IGBT having a desired characteristic can be obtained extremely easily as compared with the adjustment of the specific resistance of the buffer layer or the introduction amount of the lifetime killer. Therefore, the effect is extremely large.

[Brief description of drawings]

Fragmentary cross-sectional view of a lateral IGBT in the embodiment of Figure 1 the present invention, Figure 2 is a fragmentary sectional view of a conventional lateral IGBT, FIG. 3 is a conventional P ⁺
Drain layer-N ⁺ buffer layer-N ^- layer potential barrier diagrams, FIGS. 4 (a) and 4 (b) show a state in which the potential barrier shown in FIG. 3 is changed by voltage application according to an embodiment of the present invention. FIG. 1: N ^- substrate, 2: P well (first region), 3: P ⁺⁺ contact layer (third region), 4: N ⁺ source layer (fourth region), 5: source electrode, 6:
Gate oxide film, 7: gate electrode, 8: P ⁺ drain layer (fifth region), 9: N ⁺ buffer layer (second region), 10: drain electrode, 11: extraction electrode, 21, 22: DC power supply.

Claims (3)

[Claims] 1. A first region of the second conductivity type and a second region of the first conductivity type are selectively located on a surface portion of a substrate of the first conductivity type having a low impurity concentration with a predetermined interval, The third region of the second conductivity type and the fourth region of the first conductivity type are both selectively formed on the surface of the first region, and the third region and the fourth region are short-circuited by the source electrode. A gate electrode is provided on the surface of the first region between the fourth region and the substrate region through an oxide film, and a drain electrode is in contact with the second region. A lateral conductivity modulation type MOSFET characterized in that, when the region is selectively formed, the extraction electrode is in contact with the second region. 2. The horizontal type according to claim 1, wherein in the ON state, a forward voltage is applied to the PN junction between the second region and the fifth region via the drain electrode and the extraction electrode. Control method for conductivity modulation type MOSFET. 3. A voltage reverse to the PN junction between the second region and the fifth region is applied through the drain electrode and the extraction electrode in a switching state from on to off. Item 2. A method for controlling a lateral conductivity modulation type MOSFET according to Item 1.