JPH08129900A - Testing method for semiconductor memory - Google Patents

Abstract

PURPOSE: To prevent a testing time from becoming long in the case of measuring a memory module with a tester having limited data pins. CONSTITUTION: The number of data pins are made to be half number of data pins by wiring data pins divided into banks in the memory module and a dynamic RAM by a CAS signal with a tester fixture 7 and by connecting the fixture to a tester 6. Consequently, the testing time is shortened because reaping testings are made unnecessary by making the CAS signal divided into respective banks 8, 9 operate separately in one timing cycle at the time of a testing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for testing a semiconductor memory, and more particularly to a method for testing a semiconductor integrated circuit having a dynamic random access memory.

[0002]

2. Description of the Related Art The progress in high-density semiconductor integrated circuit technology has been remarkable, and there is momentum that it is not stopped now. Especially, the dynamic random of MOS structure
Currently 16M in the field of access memory (DRAM)
A bit dynamic RAM has been put into practical use, and various products such as a 64M bit dynamic RAM and a 16M synchronous dynamic RAM have already been developed. Along with this, other bit products such as single-in-line-memory-module (SIMM) and dual-in-line-memory-module are increasing, and x8-bit to x36-bit products are put into practical use.
Further, products of x64 bit, x72 bit, etc. have been developed.

With the recent increase in the memory capacity of DRAMs, the test time increases exponentially. like this,
In order to reduce the test time, a multi-address type DRAM having a separate bank selection signal as an address input for selecting a predetermined bank among a plurality of banks is disclosed in Japanese Patent Laid-Open No.
It is described in JP-A 1-113184.

Referring to FIG. 5 which shows a part of the block diagram shown in FIG. 1 of this publication, a DRA having four banked memory cell arrays and row and column decoders is provided.
When a row address strobe (RAS (negative logic)) signal (hereinafter simply referred to as RAS signal) is activated for M (not shown), the row address signal Addr and the bank selection signal BSi are processed by the address buffer 700. Column selection internal signals CAS0, CAS1, CAS2, CA for latching and selectively driving four memory cell arrays based on this information
Control circuit 8 for column address strobe (CAS (negative logic)) signal (hereinafter simply referred to as CAS signal) that generates S3
00 is provided.

As shown in the timing chart of FIG. 6, the operation of this circuit is as follows. First, at the time of falling of RAS signal, that is, transition to activation, row address signal Addr and bank selection signal BSi.
Are simultaneously latched by the address buffer 700. The four row decoders are simultaneously activated by the row strobe signals from the address buffer 700, and select one word line in the four memory cell arrays. afterwards,
The read operation in these memory cell arrays proceeds.
The bank selection signal BSi latched in the address buffer 700 is temporarily taken in by the control circuit 801 as an internal latch incorporated in the clock generator 800. Based on this information, the CAS signal is a series of column selection internal signals CAS that independently drive four memory cell arrays.
0, CAS1, CAS2 and CAS3 are selectively generated from the column strobe signal control circuit 801. For example, when the column selection internal signal CAS0 is selected, the other column selection internal signals CAS1 to CAS3 are not generated, so that the data of only one corresponding memory cell array is output.

Therefore, in such a DRAM, since the memory cell arrays divided into a plurality of banks are completely independent, various test pattern tests of the memory can be independently carried out, and the test time can be shortened. There is.

[0007]

However, in such a configuration, as shown in FIG. 6, the RAS signal is selected during one cycle time (during one active period). The column select internal signal (CAS0, 1, 2, 3) is the only one of them, and therefore only the memory cells in the corresponding bank are selected. That is, since the memory cell array in only one bank is selected during one cycle time, the test time cannot be significantly reduced. With the increase in memory capacity, further reduction in test time is desired.

It is also an important requirement not to increase the number of external leads, that is, the number of pins.

The basic functions of the DRAM are not impaired, the additional circuit dedicated to the test is simple and small, and the wiring in the semiconductor integrated circuit is not changed as much as possible during the inspection and the normal operation. Etc. are important requirements.

In view of the above problems, the present invention has the following problems.

(1) To significantly reduce the test time.

(2) No increase in external leads.

(3) Do not interfere with normal operation.

(4) Minimize the number of circuit elements required for the test.

(5) The circuit required for the test can be incorporated in the semiconductor integrated circuit and can be easily added to the test outside the semiconductor integrated circuit.

(6) The test method should be simple and avoid complicated.

(7) The test data transmission means should be as different as possible from the normal use state.

[0018]

The first structure of the present invention is as follows.
In a semiconductor memory test method for testing a memory of a semiconductor integrated circuit in which a plurality of dynamic random access memories are divided into banks, a plurality of columns are provided during one activation of a row address strobe signal. A method for activating the address strobe selection signal in sequence and writing the data in the tester to the dynamic random access memory in the bank selected by the selection signal is provided.

A second configuration of the present invention is a semiconductor memory test method for testing a memory of a semiconductor integrated circuit, wherein a plurality of dynamic random access memories are divided into banks, with a tester, and a row address strobe signal. A method of sequentially activating a plurality of column address strobe selection signals during one activation of the memory and sequentially reading the written test data from the dynamic random access memory in the bank selected by the selection signals. It is characterized by having.

In particular, in the first and second configurations, a test jig is interposed between the semiconductor integrated circuit and the tester, and the data input / output line of the bank is selected using this test jig. When the semiconductor integrated circuit has only one column address strobe selection signal line, in addition to the signal line, the output of the monostable multivibrator having the signal line as an input is provided in another column. The plurality of column address strobe select signals are configured as the address strobe select signals.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, which shows a circuit diagram of a tester, a test jig, and a memory module prepared by a semiconductor integrated circuit test method according to an embodiment of the present invention, as an inspection target,
A semiconductor integrated circuit including the DRAM memory module 10 is prepared. The memory module 10 is divided into a first bank 8 and a second bank. The first and second banks 8 and 9 are respectively composed of four DRAM memory cell arrays 11, 12, 13, and 14;
4 These arrays are cell arrays of the same configuration, each of which is composed of cells of M rows × N columns, and the input / output lines (I /
The O line) is a common line for input and output, and four lines are provided for each. Therefore, it is written and read every 4 bits.

Further, these cell arrays 11 to 14,
21 to 24 include a column address strobe (CAS (negative logic operation)) selection signal and a row address strobe (RAS).
(Negative logic operation) signal and are activated.
The first row address strobe signal line 1 is connected to the first bank 8
The second row address strobe signal line 2 is commonly connected to the cell arrays 11 to 14 in the second bank 9 and the second row address strobe signal line 2 is commonly connected to the cell arrays 21 to 24 in the second bank 9. The first column address strobe selection signal line 3 is commonly connected to the cell arrays 11 to 14 in the first bank 8, and the second column address strobe selection signal 4 is connected to the cell arrays 21 to 24 in the second bank 9. Commonly connected. The four input / output lines I / O 1, 2, 3, 4, in each cell array are led out from the memory module 10 via pins. First and second row address strobe signal lines 1, 2, 1,
The second column address strobe signal lines 3 and 4 are also pulled out to the outside through the pins. Here, each decoder and the like for selecting row and column addresses are not shown.

The memory module configured as described above is electrically connected to the test jig 7 by pin connection. In this test jig 7, four input / output lines 31 in the cell array 11 and four input / output lines 41 in the cell array 21 are used.
One of them is selected by the signal of the control signal line 60 so that either of them is connected to the test line 51 of the tester 6. For example, one of the I / O2 line in the cell array 11 and the I / O2 line in the cell array 21 is 1 of the test line 51.
It is electrically connected to the book. Cell arrays 12, 13, 14
Similarly, the relationship between the cell arrays 22, 23 and 24 is also selected by the jig 7 in exactly the same manner and electrically connected to the test lines 52 and 53. Further, the first and second column address strobe selection signal lines 3 and 4 are directly connected to the tester 6 without being selected by the test jig 7. The first and second row address strobe signals 1 and 2 are commonly connected in the test jig 7 and connected in the tester 6.

The test jig 7 is prepared as an interface when the total number of test pins of the tester 6 is smaller than the total number of pins of the memory module 10 to be inspected.

The tester 6 includes 16 test lines 51 to 54 which are data input lines and a control line 60 of the test jig 7.
And a row address strobe signal line, and pins for connecting the first and second column address strobe selection signal lines 34, and in addition, the memory module 10 is provided with necessary pins such as an address selection signal line and a control line. Although not shown here. The test pattern set in the test 6 includes various logical and logical programs such as marching, walking and galloping.
It will not be detailed here.

The test jig 7 is composed of a selector including a transfer gate. This selector is necessary for switching between the first bank 8 and the second bank 9.

In order to explain the operation of this embodiment, the state at the time of writing will be described with reference to FIG. 2 showing a timing chart in addition to FIG.

First, the write enable (WE) signal line (not shown) is set from 1 level to 0 level, and the row address strobe signal lines 1 and 2 are also set from 1 level to 0 level to be activated. I do. During the one timing cycle, a plurality of bangs shown below are sequentially selected.

First column address strobe select signal line 3
From the 1 level to the 0 level and first activated, and the memory cell arrays 11, 12, 13, in the first bank 8 are activated.
Select 14. At this time, the test jig 7 electrically connects the cell array in the first bank 8 and the tester 6.
Therefore, the second bank 9 is not connected.

Next, the cells in the cell arrays 11, 12, 13, and 14 are selected by the matrix address signal, and the test data is output from the tester 6, and this data is sequentially output to each memory cell every 4 bits. Write. Continue until all cells in the first bank 8 have been written.

Next, the first column address strobe select signal line 3 is returned from 0 level to 1 level and inactivated,
By immediately activating the second column address strobe select signal line 4, the cell array 2 in the second bank 9 is activated.
Select 1, 22, 23, 24.

Here, the data input / output lines 41, 42, 43 and 44 in the cell arrays 21 to 24 and the test lines 51 to 54 of the tester 6 are connected to each other, respectively.
Control the test jig 7. At this time, it is not connected to the first bank 8 and the cells in this bank 8 hold data.

Next, the cells in the cell arrays 21 to 24 are selected by the row and column address signals, and the test data is output from the tester 6. This test data is sequentially written to the corresponding cells, and continues until all cells are written.

As the control signal of the control signal line 60 to the test jig 7, a signal synchronized with the signals of the first and second column address strobe selection signal lines 3 and 4 can be used.

As described above, the test data write operation of this embodiment is performed once because the two column address strobe select signal lines are sequentially activated while the row address strobe signal line is activated once. Twice the write amount is achieved during the timing cycle of. Therefore, the write time of the test data is about one half.

Further, in this embodiment, since the test jig 7 is used as the interface, there is an advantage that the test can be performed even when the tester has a small number of test pins.

Further, since it is not necessary to increase the number of external leads, and one column address strobe signal line can be selected during one cycle time in normal operation,
In particular, there is an advantage that the structure is simple and the test method is not complicated because it does not affect the normal operation and only requires the provision of the test jig 7 having the transfer gate.

As described above, the read operation of the data written at the timing shown in FIG. 2 in the configuration of FIG. 1 is performed in the same manner as the write operation described above, as shown in FIG. That is, during one timing cycle, the first and second column address strobe selection signal lines are sequentially activated, and data is read using the same input / output lines as those used for writing. The timing operation at the time of reading is limited to that shown in FIG. 3, and redundant description will be omitted.

The data written at the timing shown in FIG. 2 is read at the timing shown in FIG. 3 and compared by the tester 6, and if they match, it is judged as good, and if they do not match, it is judged as defective.

The test time is shortened to about 1/4 by the above writing and reading methods.

Particularly when a semiconductor integrated circuit having a large number of data pins such as a memory module or a multi-bit DRAM is inspected by a tester having a limited number of data pins, it can be performed in a short time without reducing the number of measurements. There is an advantage.

In the above embodiments, the memory module having two column address strobe select signal lines has been described. In addition to this, in the SIMM package having the CAS terminal having only one external lead, that is, FIG. As shown in the block diagram of FIG. 1, the monostable multivibrator 71 is provided between the first and second column address strobe selection signals 3 and 4.
Through the first column address strobe select signal line 3
The vibrator 71 is triggered and the second column address strobe select signal line 4, which is to be activated next, is activated at the time of transition from 0 level to 1 level.

If this vibrator 71 is incorporated in the module 10, the tester and test jig common to the above-mentioned embodiment can be used, and the test can be performed in the same manner.

It should be noted that it is desirable to provide a selector 72 and switch it appropriately by a control signal in preparation for the case where the operation of the vibrator 71 is unnecessary in the case of normal operation.
In FIG. 4, main parts common to those in FIG. 1 are denoted by common reference numerals, and circuits and wirings in the block are omitted.

In the above embodiments, the case where the memory cell array is divided into two banks is shown. However, even when the memory cell array is divided into three or more banks, a suitable number of memory cells can be formed during one cycle time. A column address strobe select signal can be provided and tested.

[0046]

As described above, according to the present invention,
Each of the above problems has been achieved, and a semiconductor tester with a large number of data pins, especially a test jig for inspecting with a tester with a limited number of data pins, has been used to create multiple banks during one timing cycle. The effect is that inspection can be performed in order.

[Brief description of drawings]

FIG. 1 is a block diagram showing a connection relationship between a tester, a test jig, and a semiconductor integrated circuit prepared by a test method according to an embodiment of the present invention.

FIG. 2 is a timing diagram showing a data writing method according to an embodiment of the present invention.

FIG. 3 is a timing diagram showing a data reading method according to an embodiment of the present invention.

FIG. 4 is a block diagram showing a test method when there is only one CAS line.

FIG. 5 is a block diagram showing an address selection method of a conventional DRAM.

FIG. 6 is a timing chart showing the operation of FIG.

[Explanation of symbols]

 1, 2 row address strobe signal line 3 first column address strobe selection signal line 4 second column address strobe selection signal line 6 tester 7 test jig 8 first bank 9 second bank 10, 70 memory module 11 To 14, 21 to 24 DRAM cell array 31 to 34, 41 to 44 data input / output line 51 to 54 test line 60 control line 71 monostable multivibrator 72 selector 700 address buffer 800 clock generator 801 column address strobe signal control circuit

Claims (4)

[Claims] 1. A method of testing a semiconductor integrated circuit in which a plurality of dynamic random access memories are divided into banks, wherein the memory is inspected by a tester, wherein a row address strobe signal is activated once. And a method of activating a plurality of column address strobe selection signals in order and writing the data in the tester to the dynamic random access memory in the bank selected by the selection signals. Test method for semiconductor memory. 2. A method for testing a semiconductor memory, wherein a memory of a semiconductor integrated circuit in which a plurality of dynamic random access memories are divided into banks is tested by a tester, wherein a row address strobe signal is activated once. And a method of sequentially activating a plurality of column address strobe selection signals and sequentially reading the written test data from the dynamic random access memory in the bank selected by the selection signals. Semiconductor memory test method. 3. A semiconductor memory according to claim 1, wherein a test jig is interposed between the semiconductor integrated circuit and the tester, and the data input / output line of the bank is selected by using the test jig. Test method. 4. When the semiconductor integrated circuit has only one column address strobe selection signal line, in addition to the signal line, the output of a monostable multivibrator having the signal line as an input is used for another column address. 3. The semiconductor memory test method according to claim 1, wherein said plurality of column address strobe select signals are formed as strobe select signals.