JPH08130312A - Horizontal semiconductor device and method of using the same - Google Patents

Abstract

(57) Abstract: A turn-off time of an IGBT, a transistor, a thyristor, etc. integrated in a power IC is shortened and a switching loss is reduced. An n epitaxial layer or p on a p-type substrate.
A p-well region is provided in the n-well region formed in the surface layer of the mold substrate to form an n-channel type IGBT therein, and the collector electrode of the IGBT and the n epitaxial layer or n
The anode electrode provided on the surface of the well region is connected to prevent generation of a parasitic pnp transistor. This gives p
Holes are not injected into the mold substrate or p isolation, and the accumulated carriers are reduced, so that the switching time is shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lateral semiconductor device as a power element integrated in a power integrated circuit (hereinafter abbreviated as power IC) for driving a switching power supply, a flat panel display, a motor and the like.

[0002]

2. Description of the Related Art FIG. 24 is a sectional view of a lateral insulated gate bipolar transistor (hereinafter abbreviated as IGBT) as an example of a power element integrated in a conventional power IC. p
An n-buried layer 2402 is formed on a mold substrate 2401, and an n-epitaxial layer 2403 is stacked on the n-buried layer 2402.
From the surface of the n epitaxial layer 2403 to the n buried layer 2
402 sinking n sinker 2404, p-type substrate 2401
Isolation 2 for isolation of device regions reaching
405 is formed. Further, the n epitaxial layer 240
P base region 2407 is formed in the surface layer of
An n emitter region 2415 and ap contact region 2413 are formed in the base region 2407. Further, a p collector region 2414 is formed in the surface layer of the n sinker 2404. A thick oxide film 2410 is provided on the exposed surface of the n epitaxial layer 2403. The gate electrode 2 connected to the G terminal through the gate oxide film 2411 on the surface of the p base region 2407 sandwiched between the exposed surface of the n epitaxial layer 2403 and the n emitter region 2415.
412 is provided. n emitter region 2415 and p
An emitter electrode 2417 connected to the E terminal is provided in common contact with the contact region 2413, and a collector electrode 2418 connected to the C terminal is provided on the surface of the p collector region 2414. Further, an interlayer insulating film, a metal wiring, a passivation film, etc. may be formed on these surfaces.

In this device, by applying a positive voltage equal to or higher than the threshold voltage to the gate electrode 2412 with respect to the emitter electrode 2417, the inversion layer is formed on the surface layer of the p base region 2407 immediately below the gate electrode 2412. Occurs.
Electrons flow from the n emitter region 2415 into the n epitaxial layer 2403 through the inversion layer, and are further injected into the p collector region 2414. As a result, this electron current is transferred to the p collector region 2414 and the n epitaxial layer 240.
3, the base current of the pnp transistor constituted by the p base region 2407, the pnp transistor is turned on, conductivity modulation occurs, and a large current flows between the CE terminals.

FIG. 25 shows a conventional power IC different from that shown in FIG.
A sectional view of a lateral IGBT as a power element integrated in FIG. The n-well region 2 is formed on the surface layer of the p-type substrate 2501.
503 is formed, and the p base region 25 is formed in a part of the surface layer.
07, an n emitter region 2515 and ap contact region 2513 are formed in the p base region 2507. Further, an n buffer region 2509 is formed on the surface layer of the n well region 2503, and the n buffer region 2 is formed.
A p collector region 2514 and an n contact region 2516 are formed in 509. n-well region 2503
There is a thick oxide film 2510 on the exposed surface of the. The exposed surface of the n-well region 2503 and the n-emitter region 25
A gate electrode 2512 connected to the G terminal via the gate oxide film 2511 is provided on the surface of the p base region 2507 sandwiched between the gate electrode 2512 and the gate electrode 2512. n emitter region 251
5 and p contact region 2513 in common,
An emitter electrode 2517 connected to the terminal and a collector electrode 2518 connected to the C terminal are provided on the surface of the p collector region 2514. Further, an interlayer insulating film, a metal wiring, a passivation film, etc. may be formed.

In this device, an inversion layer is formed in the surface layer of the p base region 2507 immediately below the gate electrode 2512 by applying a voltage higher than the threshold voltage to the gate electrode 2512 with respect to the emitter electrode 2517. . Electrons flow from the n-emitter region 2515 into the n-well region 2503 through the inversion layer, and further, the p-collector region 251.
Injected into 4. As a result, this electron current is applied to the p collector region 2514, the n well region 2503, and the p base region 2.
It becomes the base current of the pnp transistor constituted by 507, this transistor turns on, conductivity modulation occurs, and a large current flows between the C and E terminals.

[0006]

However, the device shown in FIG. 24 has the following two drawbacks. p collector region 2414, n sinker 2404, n epitaxial layer 2403 and n buried layer 2402,
There is a parasitic pnp transistor Q1 formed of the p-type substrate 2401, electrons of minority carriers are accumulated in the p-type substrate 2401, and it takes time to extract and eliminate the accumulated electrons when the switch is turned off, resulting in a residual current. Therefore, switching time is prolonged and switching loss is increased. In addition to the parasitic pnp transistor Q1 described above, a parasitic pnp transistor Q2 exists between the p collector region 2414, the n sinker 2404, and the p isolation 2405. When this element is used as a high side switch such as a half bridge, a collector electrode 24 connected to the power source
A parasitic current flows from 18 to the p-type substrate 2401 via the parasitic pnp transistors Q1 and Q2. Therefore, the loss increases.

In the device of FIG. 25, since no epitaxial wafer is used, the cost can be reduced, but n
Since the buried layer cannot be formed, it is used as a low-side switch. This element also has a problem that a parasitic current flows through the parasitic pnp transistor Q3 by the same mechanism as described above. Although the lateral IGBT is taken up and explained as an example, this phenomenon does not occur only in the lateral IGBT, and the same problem occurs in MOSFETs, bipolar transistors, thyristors, or MOS control thyristors having an insulated gate (hereinafter referred to as MCT). .

In view of the above problems, an object of the present invention is to prevent the operation of a parasitic transistor and reduce the accumulation of minority carriers in a semiconductor substrate of the first conductivity type or isolation, thereby shortening the switching time, An object of the present invention is to provide a lateral semiconductor device capable of reducing switching loss and a method of using the lateral semiconductor device.

[0009]

In order to solve the above problems, a lateral semiconductor device according to the present invention has a first semiconductor layer formed on a part of a surface layer of a second conductivity type semiconductor area on a first conductivity type semiconductor area. It is assumed that a semiconductor element having first and second main electrodes and a control electrode is provided in and on the one-conductivity type well region.

It is preferable that the auxiliary electrode is provided on the surface of the second conductivity type semiconductor region or on the surface of the second conductivity type region in contact with the second conductivity type semiconductor region. It is preferable that the electrodes are electrically connected. The second conductive type semiconductor region and the second conductive type region in contact with the second conductive type semiconductor region are covered with an insulating film on the surface exposed portion,
The auxiliary electrode may not be provided on it.

Semiconductor elements are IGBTs, MOSFETs,
It can be either a transistor, a thyristor, or an MCT. For example, as an IGBT, a second conductivity type semiconductor region formed on the first conductivity type semiconductor layer, a first conductivity type well region formed in a part of a surface layer of the second conductivity type semiconductor region, and a second conductivity type well region A first conductivity type base region formed on a part of a surface layer of the one conductivity type well region; a second conductivity type emitter region formed on a part of a surface layer of the first conductivity type base region; A second conductivity type base region formed in a portion of the surface layer of the conductivity type well region where the first conductivity type base region is not formed, and a second conductivity type base region formed in a part of the surface layer of the second conductivity type base region. A gate made of polycrystalline silicon formed on the surface of a first conductivity type base region sandwiched between a first conductivity type collector region, a second conductivity type base region and a second conductivity type emitter region via a gate insulating film. Electrodes,
It has an emitter electrode provided in common contact on the surfaces of the second conductivity type emitter and the first conductivity type base region, and a collector electrode provided on the surface of the first conductivity type collector region. .

Further, the second conductivity type base region may be expanded to form an IGBT in which the first conductivity type base region is formed in a part of the surface layer thereof. Conversely, the first conductivity type base region may be widened to form the IGBT in which the second conductivity type base region is formed in a part of the surface layer thereof.
Further, the first conductivity type base region may be expanded so that the second conductivity type base region is included in a part of the surface layer of the first conductivity type base region so that the first conductivity type base region is omitted.

Further, the first conductivity type base region may be an IGBT in which the second conductivity type base region is formed in a part of the surface layer and the second conductivity type emitter region is not included. For example, as a lateral MOSFET, a second conductivity type base region formed in a part of the surface layer of the first conductivity type well region and a first conductivity type formed in a part of the surface layer of the second conductivity type base region. A source region, a first conductivity type drain region formed in a portion of the surface layer of the second conductivity type base region where the first conductivity type source region is not formed, the first conductivity type source region and the first conductivity type A gate electrode formed via a gate insulating film on the surface of the second conductivity type base region sandwiched between the drain region and the surface of the first conductivity type source region and the first conductivity type base region in common. It is assumed to have a source electrode which is a second main electrode provided in contact with each other and a drain electrode which is a first main electrode provided on the surface of the first conductivity type drain region.

Further, a lateral MOSFET in which the second-conductivity-type base region is widened and the first-conductivity-type source region is formed in a part of the surface layer thereof can be used. The second conductivity type drain region is formed on a part of the surface layer of the first conductivity type well region and the part of the surface layer of the first conductivity type well region where the second conductivity type drain region is not formed A second conductivity type source region, a gate electrode formed via a gate insulating film on the surface of the first conductivity type well region sandwiched between the second conductivity type source region and the second conductivity type drain region, A source electrode, which is a second main electrode provided in common on the surfaces of the second-conductivity-type source region and the first-conductivity-type base region, and a first electrode provided on the surface of the second-conductivity-type drain region. Lateral MO having one main electrode and drain electrode
It can also be an SFET.

For example, as a lateral bipolar transistor, a second conductivity type base region is formed on a part of the surface layer of the first conductivity type well region, and a part of the surface layer of the second conductivity type base region is formed. A first conductivity type emitter region,
A first conductivity type collector region formed in a portion of the surface layer of the first conductivity type well region where the second conductivity type base region is not formed; and a gate electrode formed on the surface of the second conductivity type base region. An emitter electrode that is a first main electrode provided on the surface of the first conductivity type emitter region, and a collector electrode that is a second main electrode provided on the surface of the first conductivity type collector region. To do.

Further, it is also possible to form a lateral bipolar transistor in which the base region of the second conductivity type is widened and the collector region of the first conductivity type is formed in a part of the surface layer thereof.
As a reverse polarity lateral bipolar transistor, a first conductivity type base region formed on a part of the surface layer of the first conductivity type well region and a first conductivity type base region formed on a part of the surface layer of the first conductivity type base region. A second conductivity type collector region and a second conductivity type emitter region formed in a portion of the surface layer of the first conductivity type base region where the second conductivity type collector region is not formed,
A base electrode formed on the surface of the first conductivity type base region, an emitter electrode that is a second main electrode provided on the surface of the second conductivity type emitter region, and a surface of the second conductivity type collector region. And a collector electrode which is the first main electrode provided.

Further, it is possible to form a lateral bipolar transistor in which the second conductivity type base region is expanded and the first conductivity type collector region is formed in a part of the surface layer thereof.
Further, the first conductivity type well region also serves as the first conductivity type base region, and a lateral bipolar transistor in which the first conductivity type base region is omitted may be used.

Further, the first-conductivity-type base region may be a lateral bipolar transistor in which the first-conductivity-type collector region is formed in a part of the surface layer and the first-conductivity-type emitter region is not included. . For example, as a thyristor, a first conductivity type base region formed in a part of the surface layer of the first conductivity type well region, and a second conductivity type cathode formed in a part of the surface layer of the first conductivity type base region. Area and
A second conductivity type base region formed apart from the first conductivity type base region in a part of the surface layer of the first conductivity type well region,
Provided on the surface of the second conductivity type base region, the first conductivity type anode region, the gate electrode formed on the surface of the first conductivity type base region, and the surface of the second conductivity type cathode region. The second main electrode is a cathode electrode and the anode electrode is a first main electrode provided on the surface of the first conductivity type anode region.

A lateral thyristor in which the second-conductivity-type base region is widened and the first-conductivity-type base region is formed in a part of the surface layer of the thyristor can be used. On the contrary, a lateral thyristor in which the first conductivity type base region is widened and the second conductivity type base region is formed in a part of the surface layer thereof can be used. Further, the first conductivity type well region also serves as the first conductivity type base region, and a lateral thyristor in which the first conductivity type base region is omitted may be used.

Further, the first conductivity type base region may be a lateral thyristor in which the second conductivity type base region is formed in a part of the surface layer and the second conductivity type emitter region is not included. For example, as a lateral MOS gate thyristor, a first conductivity type base region formed in a part of the surface layer of the first conductivity type well region and a second conductivity type formed in a part of the surface layer of the first conductivity type base region. A conductivity type cathode region, a first conductivity type cathode region formed in a part of a surface layer of the second conductivity type cathode region, and a second conductivity type base region formed apart from the first conductivity type base region. A first conductivity type anode region formed in the surface layer of the second conductivity type base region, and a second conductivity type cathode region sandwiched between the second conductivity type base region and the first conductivity type cathode region, The gate electrode formed on the surfaces of the conductivity type base region and the first conductivity type well region via the gate insulating film and the surface of the first conductivity type cathode region and the second conductivity type cathode region are in common contact with each other. Second Lord It shall have the cathode electrode is extremely, the anode electrode is a first main electrode provided on a surface of the first conductivity type anode region.

Further, a lateral MOS gate thyristor in which the second conductivity type base region is widened and the first conductivity type base region is formed in a part of the surface layer thereof can be used. On the contrary, a lateral MOS in which the first conductivity type base region is widened and the second conductivity type base region is formed in a part of the surface layer thereof.
It can also be a gate thyristor. Further, since the well region of the first conductivity type also serves as the base region of the first conductivity type, a lateral MOS in which the base region of the first conductivity type is omitted
It can also be a gate thyristor.

Further, the first conductivity type base region may be a lateral MOS gate thyristor in which the second conductivity type base region is formed in a part of the surface layer and the second conductivity type emitter region is not included. it can. The second conductivity type semiconductor region includes not only the second conductivity type semiconductor layer formed on the first conductivity type semiconductor device substrate but also the second conductivity type semiconductor region formed on a part of the surface layer of the first conductivity type semiconductor substrate. It may be composed of a two-conductivity type semiconductor region.

Further, a second conductivity type buried layer having an impurity concentration higher than that of the second conductivity type semiconductor layer formed in a part of the interface between the first conductivity type semiconductor substrate and the second conductivity type semiconductor layer, and an auxiliary electrode. It is also possible to have a second conductivity type sinker having a higher impurity concentration than the second conductivity type semiconductor layer reaching the second conductivity type buried layer from the surface of the second conductivity type semiconductor layer below. A buffer region having an impurity concentration higher than that of the opposite conductivity type semiconductor region may be provided between the semiconductor region in contact with the electrode and the opposite conductivity type semiconductor region therebelow.

Furthermore, first and second wells formed in and on the first conductivity type well region formed in a part of the surface layer of the second conductivity type semiconductor region on the first conductivity type semiconductor layer. As a method of using a lateral semiconductor device having a main electrode and a control electrode and having an auxiliary electrode on the surface of the second conductivity type semiconductor region or a second conductivity type region in contact with the second conductivity type semiconductor region, , A potential higher than that of the first and second main electrodes is applied.

The action when the above measures are taken is
Will be described as an example. If a p-well region is formed in the n-type semiconductor region on the p-type substrate and an IGBT is formed in the p-well region, the p-well region is sandwiched between the p-collector region and the p-type substrate, and thus parasitic. Since the pnp transistor does not operate and carriers are not accumulated in the p-type substrate, the switching time can be shortened. If an auxiliary electrode is provided on the surface of the n-type semiconductor region or an n-type region in contact with the n-type semiconductor region and the auxiliary electrode and the collector electrode of the IGBT are connected to have the same potential, the p-collector region and the p-type substrate are formed. The isolation effect between the two is further enhanced, the carriers injected from the collector electrode are blocked, and the base current of the parasitic transistor is significantly reduced or completely blocked, so that the operation of the parasitic transistor is suppressed, and It is possible to prevent injection and accumulation of minority carriers into the conductive type semiconductor substrate.

The same applies to an IGBT in which the second-conductivity-type base region is expanded and the first-conductivity-type base region is formed in a part of the surface layer, and the first-conductivity-type base region is expanded. The same applies to the IGBT in which the second conductivity type base region is formed in a part of the surface layer. Furthermore,
If the first conductivity type base region is sufficiently widened so that the surface layer includes the second conductivity type base region, the first conductivity type well region can be omitted because it overlaps with the first conductivity type well region, and The operation of the parasitic transistor is suppressed, and the injection and accumulation of minority carriers in the first conductivity type semiconductor substrate can be prevented.

The semiconductor element formed in the first-conductivity-type well region is not limited to the IGBT, and not only the second-conductivity-type semiconductor layer on the first-conductivity-type semiconductor substrate but also the surface layer of the first-conductivity-type semiconductor substrate. Regarding the IGBT formed in the second-conductivity-type well region formed in a part of the same, the auxiliary electrode on the surface of the second-conductivity-type well region and the collector electrode of the IGBT are connected to have the same potential. Thereby, it is possible to prevent the carriers injected from the collector electrode from being accumulated in the first conductivity type semiconductor substrate.

Further, a second conductivity type buried layer having an impurity concentration higher than that of the second conductivity type semiconductor layer formed in a part of an interface between the first conductivity type semiconductor substrate and the second conductivity type semiconductor layer, and an auxiliary electrode. If there is a second-conductivity-type sinker having a higher impurity concentration than the second-conductivity-type semiconductor layer that reaches the second-conductivity-type buried layer from the surface of the second-conductivity-type semiconductor layer, punch-through due to the spread of the depletion layer can be prevented. .

Further, the contact region of the second conductivity type having a higher impurity concentration than the second conductivity type semiconductor layer under the auxiliary electrode lowers the contact resistance of the electrode. If the second conductivity type buffer region having a higher impurity concentration than the second conductivity type base region is provided outside the first conductivity type collector region, it serves to suppress the spread of the depletion layer in the high breakdown voltage element.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION As an embodiment of the present invention, first and second main electrodes and a control electrode are provided directly in a second conductivity type semiconductor region on a first conductivity type semiconductor layer and on the upper part thereof. A first conductivity type well region formed in a surface layer of a second conductivity type semiconductor region on a first conductivity type semiconductor layer without forming a semiconductor element, and first and second main electrodes and control electrodes on the well region. To form a semiconductor element having

[0031]

Embodiments of the present invention will be described below with reference to the drawings. In the following, substrates, layers with p and n on the head,
A region means a substrate, a layer, or a region containing an acceptor and a donor-forming impurity, respectively. FIG. 1 shows a cross-sectional view of a lateral IGBT as a power element integrated in a power IC according to the first embodiment of the present invention. An n-buried layer 102 is formed in the element formation portion on the p-type substrate 101, and an n-epitaxial layer 103 is laminated thereon. An n sinker 104 reaching the n buried layer 102 from the surface of the n epitaxial layer 103, and a p isolation 105 for separating an element region are formed. Further, a p well region 106 is formed on the surface layer of the n epitaxial layer 103,
A p base region 107 is formed in the p well region 106, and an n emitter region 11 is formed in the p base region 107.
5, p contact region 113 is formed. Also,
An n base region 108 is formed in a portion of the surface layer of the p well region 106 other than the portion where the p base region 107 is formed.
An n buffer region 109 having an impurity concentration higher than that of the n base region 108 is formed in the base region 108, and a p collector region 114 is formed in a part of the surface layer thereof. An n contact region 116 is formed on the surface layer in the n sinker 104. A thick oxide film 110 is provided on the exposed surface of the n base region 108. The p base region 1 sandwiched between the exposed surface of the n base region 108 and the n emitter region 115.
A gate electrode 112 made of polycrystalline silicon is provided on the surfaces of the 07 and p well regions 106 and is connected to the G terminal through the gate oxide film 111. In the figure, p
Although the base region 107 includes the p-contact region 113 therein, a structure in which the p-contact region 113 is half included may be used. An emitter electrode 117 connected in common to the n emitter region 115 and the p contact region 113 and connected to the E terminal, and a collector electrode 118 connected to the C terminal on the surface of the p collector region 114, respectively. It is provided. An auxiliary electrode 119 is provided on the surface of the n contact region 116, and
8 is connected. Further, an interlayer insulating film, a metal wiring, a passivation film, etc. may be formed on the surface.

In this device, by applying a voltage equal to or higher than the threshold voltage to the gate electrode 112 with respect to the emitter electrode 117, the surface layers of the p base region 107 and the p well region 106 immediately below the gate electrode 112. An inversion layer is generated at. N emitter region 115 through the inversion layer
Electrons flow into the n base region 108 and are further injected into the p collector region 114. As a result, this electron current is transmitted to the p collector region 114, the n buffer region 109, and the n buffer region 109.
P composed of the base region 108 and the p base region 107
It becomes the base current of the np transistor, the transistor is turned on, conductivity modulation occurs, and a large current flows between the CE terminals. Incidentally, the n-buried layer 102 and the n-sinker 1
Reference numeral 04 denotes a p-type base region 107, a p-type substrate 101, and a p-type base region 107, p
This is to prevent punch-through from occurring due to the depletion layer spreading between the isolation 105 and the isolation 105. Also, n
The buffer region 109 is also for preventing punch-through of the n base region 108, and can be omitted depending on the case. p contact region 113, n contact region 116
For reducing the contact resistance with the emitter electrode 117 and the auxiliary electrode 119, respectively.

Here, the n sinker 10 surrounding the IGBT
4, the same potential as that of the p collector region 114 is applied to the n buried layer 102, so that the p type substrate 101 or
Parasitic pnp with p-isolation 105 as collector
The transistor does not turn on. Therefore, the problems in the conventional device are avoided. As a result, the carriers accumulated on the substrate were significantly reduced, the turn-off time was shortened, and the switching loss was reduced to 1/10 or less of the conventional value.

FIG. 2 is a modification of FIG. 1 and shows a sectional view of a lateral IGBT according to a second embodiment of the present invention. In this example, the structure is almost the same as in the first embodiment of FIG.
The auxiliary electrode 21 provided on the contact region 216
9 is present, but is not connected to the collector electrode 218.
By keeping the auxiliary electrode 219 at a higher potential than the collector electrode 218 by another power source, the n epitaxial layer 203, the n buried layer 202 and the n sinker 2 are formed.
The potential of 04 is also increased, and carriers are p-type substrate 201 and p
It is not injected into the isolation 205, and the parasitic pnp transistor whose collector is the p-type substrate 201 does not turn on. Therefore, the above problems are avoided. As a result, as in the first embodiment, the switching loss can be greatly reduced. This element can be turned on / off by the voltage applied to the gate electrode 212, which is the same as the IGBT of the first embodiment shown in FIG.

FIG. 3 is another modification of FIG. 1 and shows a cross-sectional view of a lateral IGBT according to a third embodiment of the present invention. In this example, the structure is almost the same as in the first embodiment of FIG.
There is no n-contact region, and there is no auxiliary electrode provided thereon. Therefore, the n epitaxial layer 303 on the p-type substrate 301 is not connected to the collector electrode 318, and its potential is floating.

This element can be turned on / off by the voltage applied to the gate electrode 312, like the IGBT of the first embodiment shown in FIG. In the off state, when the depletion layer spreads from the pn junction between the n base region 308 and the p well region 306 and reaches the n epitaxial layer 303, depending on the potential of the collector electrode 318, the n epitaxial layer 303 and the n buried layer 302. And n sinker 3
The potential of 04 also rises. Therefore, the device breakdown voltage is determined by the junction between the n-buried layer 302 and the p-type substrate 301.

In the on-state, the n-buried layer 302 is not entirely depleted, so that carriers are not injected into the p-type substrate 301, and the parasitic pnp transistor having the p-type substrate 301 as a collector does not turn on. Therefore, the above problems are avoided. As a result, as in the first embodiment, the switching loss can be greatly reduced. FIG. 4 shows a cross-sectional view of a lateral IGBT as a power element integrated in a power IC according to the fourth embodiment of the present invention. p
An n well region 403 is formed in the surface layer of the mold substrate 401 by introducing and diffusing impurities from the surface. The p well region 4 is formed in a part of the surface layer of the n well region 403.
06 is formed. Further, an n base region 408 is formed in a part of the surface layer of the p well region 406, a p base region 407 is formed at an end of the surface layer of the n base region 408, and a surface layer of the p base region 407 is formed. A p-contact region 413 is formed at an end of the surface layer of the n-emitter region 415 and the p-base region 407. Further, an n buffer region 409 having an impurity concentration higher than that of the n base region 408, and the n buffer region 4 are provided in a portion of the surface layer of the n base region 408 other than the portion where the p base region 407 is formed.
A p collector region 414 is formed in 09. An n contact region 416 is formed on the surface layer of the exposed surface of the n well region 403. There is a thick oxide film 410 on the exposed surface of the n base region 408. The gate oxide film 41 is formed on the surface of the p base region 407 sandwiched between the exposed surface of the n base region 408 and the n emitter region 415.
A gate electrode 412 connected to the G terminal through 1 is provided. An emitter electrode 417 connected in common to the n emitter region 415 and the p contact region 413 and connected to the E terminal, and a collector electrode 418 connected to the C terminal on the surface of the p collector region 414, respectively. It is provided. An auxiliary electrode 419 is provided on the surface of the n contact region 416. Further, an interlayer insulating film, a metal wiring, a passivation film, etc. may be formed.

The operation of this element is the same as that of the first embodiment of FIG. 1, and the current between the collector electrode 418 and the emitter electrode 417 is turned on / off by the signal voltage to the gate electrode 412. The n well region 403 in the p type substrate 401 is electrically connected to the p collector region 414 via the n contact region 416. Therefore, the parasitic pnp transistor whose collector is the p-type substrate 401 does not turn on. Therefore, the above problems are avoided. As a result, as in the first embodiment, the switching loss can be greatly reduced.

The embodiment of FIG. 4 differs from that of FIG. 1 in that
In this example, the well region 403 is formed not by an epitaxial layer but by diffusion of impurities. As shown in FIG.
It can also be formed in the region. In addition, the n base region 4
08 extends halfway below the p base region 407, but sometimes includes the entire p base region 407. Alternatively, the p base region 407 is the p contact region 4
It may include all 13. IGBT in such cases
And the advantages of the present invention are fully obtained. Also in the device having the structure of FIG. 4, the auxiliary electrode 419 is replaced by the collector electrode 41 as in the second and third embodiments.
Alternatively, the n-well region 403 can be set to a floating potential without being connected to No.

For the sake of simplicity also in the following embodiments, the semiconductor element is formed in the n-well region formed by the diffusion of impurities in the surface layer of the p-type substrate. However, as shown in FIG. Can also be formed in regions separated by p-isolation. Of course, conversely, instead of the n epitaxial layer 103 of FIG. 1, an n well region formed by impurity diffusion can be used.

In the IGBT of the embodiment shown in FIG. 1, the n emitter region 115 and the like are symmetrically arranged with the p collector region 114 as the center. When dealing with a particularly large current, such a structure is often used in view of current and thermal balance. For the sake of simplicity, the embodiments of FIG. 4 and subsequent figures show an asymmetrical structure as a basic structure. FIG. 5 shows a sectional view of a lateral IGBT according to a fifth embodiment of the present invention. An n-well region 503 is formed on the surface layer of the p-type substrate 501, and a lateral IGBT is formed on the surface layer of the p-well region 506 formed on a part of the surface layer of the n-well region 503. The difference from the embodiment of FIG. 1 is that an n base region 508 is formed in the surface layer of the p base region 507.
In this case, the n base region 508 and the n emitter region 5
Since the p well region 506 is not sandwiched between the gate electrode 512 and the gate electrode 15, the gate electrode 512 is on the surface of the p base region 507. The operation of this device is the same as that of the above-mentioned embodiment,
Similar effects can be obtained, and switching loss can be significantly reduced.

FIG. 6 shows a horizontal IG according to a sixth embodiment of the present invention.
A sectional view of BT is shown. An n-well region 603 is formed on the surface layer of the p-type substrate 601, and a surface layer of the p-well region 606 formed on a part of the surface layer of the n-well region 603 is similar to that of the fifth embodiment of FIG. A lateral IGBT is formed. The difference from the embodiment of FIG. 5 is that the p base region is omitted. Alternatively, it can be considered that the p base region is formed large enough to completely include the n base region 608 and overlaps with the p well region 606. Gate electrode 612 is on the surface of p-well region 606.

FIG. 7 is a lateral IG according to a seventh embodiment of the present invention.
A sectional view of BT is shown. An n-well region 703 is formed on the surface layer of the p-type substrate 701, and a surface layer of the p-well region 706 formed on a part of the surface layer of the n-well region 703 is similar to that of the sixth embodiment of FIG. A lateral IGBT is formed. The difference from the embodiment of FIG. 6 is that the p base region 707 is formed not to include the n emitter region 715 but to include the n base region 708. Gate electrode 712
Are on the surfaces of p base region 707 and p well region 706.

The operation of these elements is the same as that of the above-mentioned embodiment, the same effect is obtained, and the switching loss can be greatly reduced. Of course, FIG. 5, FIG. 6 and FIG.
N-well region 50 formed by diffusion of impurities
Instead of 3, 603 and 703, an n-epitaxial layer formed by epitaxial growth may be used. Also in the devices having these structures, unlike the second and third embodiments, the auxiliary electrode is not connected to the collector electrode to maintain a higher potential, or the auxiliary electrode is not provided and the n-well region is floated. It can also be at a potential.

Although all of the above-mentioned embodiments show the n-channel type IGBT, the structure of the present invention is not limited to the n-channel type IGBT, and the p-channel type IGBT by the symmetrical conduction type semiconductor region. Needless to say, can also be applied to. The example of the IGBT has been described above, but the present invention is also applied to semiconductor devices other than the IGBT.

FIG. 8 shows the power I of the eighth embodiment of the present invention.
Lateral MOSFET as a power device integrated in C
FIG. An n well region 803 is formed in the surface layer of the p-type substrate 801 by introducing and diffusing impurities from the surface. A p well region 806 is formed in a part of the surface layer of the n well region 803. Further, an n base region 808 is formed in a part of the surface layer of the p well region 806, and p is formed in a part of the surface layer of the n base region 808.
A source region 821 is formed, an n buffer region 809 is formed in a portion of the surface layer of the n base region 808 different from the portion where the p source region 821 is formed, and a p drain region 822 is formed in the n buffer region 809. . Further, an n contact region 816 is formed on the surface layer of the exposed surface of the n well region 803. The gate oxide film 81 is formed on the surfaces of the n base region 808 and the n buffer region 809 sandwiched between the p source region 821 and the p drain region 822.
A gate electrode 812 connected to the G terminal through 1 is provided. The source electrode 823 connected to the S terminal is formed on the surface of the p source region 821, and the p drain region 82 is also formed.
On the surface of 2, the drain electrode 82 connected to the D terminal
4 are provided respectively. n contact region 816
An auxiliary electrode 819 is provided on the surface of the. Further, an interlayer insulating film, a metal wiring, a passivation film, etc. may be formed.

In this element, by applying a negative voltage equal to or higher than the threshold voltage to the gate electrode 812 with respect to the source electrode 823, the inversion layer is formed on the surface layer of the n base region 808 immediately below the gate electrode 812. Occurs. The source electrode 823 and the drain electrode 824 are electrically connected through the inversion layer. The hole current flows in the inversion layer, and there is a parasitic diode composed of the p drain region 922, the n buffer region 909, and the n base region 908. Conventionally, holes leaked to the n-base region are accumulated in the p-type substrate,
It was a cause of increasing the switching loss.

In this example, the n well region 803 in the p type substrate 801 is electrically connected to the p drain region 822 via the n contact region 816. For this reason,
The parasitic pnp transistor whose collector is the p-type substrate 801 does not turn on. Therefore, the above problems are avoided. As a result, it is possible to significantly reduce the switching loss as in the case of the IGBT described above.

FIG. 9 is a horizontal MO of the ninth embodiment of the present invention.
The sectional view of SFET is shown. n on the surface layer of the p-type substrate 901
A well region 903 is formed and its n well region 906 is formed.
A lateral MOSFET similar to that of the eighth embodiment of FIG. 8 is formed on the surface layer of the p-well region 906 formed on the surface layer of FIG. The difference from the embodiment of FIG. 8 is that the p well region 906 is
The point is that the p source region 921 is formed in the surface layer of. In this case, the gate electrode 912 is provided on the surfaces of the n base region 908 and the n buffer region 909 sandwiched between the p well region 906 and the p drain region 922 with the gate oxide film 911 interposed therebetween.

The operation of this element is the same as that of the eighth embodiment of FIG. 8, the same effect is obtained, and the switching loss can be greatly reduced. The embodiment of FIGS. 8 and 9 is similar to the above-described IGBT example, in which the n-well regions 803 and 90 are formed.
It goes without saying that 3 may be an epitaxial layer. Further, auxiliary electrodes 819 and 919 are provided on the surfaces of the n contact regions 816 and 916, and drain electrodes 824 and
It is also possible to maintain a higher potential without connecting to 924, or to omit the auxiliary electrodes 819 and 919. Even in such a case, the operation of the MOSFET does not change, and the advantages of the present invention can be sufficiently obtained.

FIG. 10 is a lateral MOSFE as a power element integrated in the power IC of the tenth embodiment of the present invention.
A sectional view of T is shown. By introducing and diffusing impurities from the surface into the surface layer of the p-type substrate 1001, the n well region 10 is formed.
03 is formed. A p well region 1006 is formed in a part of the surface layer of the n well region 1003. Further, a p base region 1007 is formed in a part of the surface layer of the p well region 1006, and an n drain region 1026 is formed in the surface layer of the p base region. A p buffer region 1032 is formed in a portion of the surface layer of the p base region 1007 other than the portion where the n drain region 1026 is formed, and an n source region 1025 is formed in the p buffer region 1032. Further, an n contact region 1016 is formed on the surface layer of the exposed surface of the n well region 1003. G is formed on the surface of the p base region 1007 and the p buffer region 1032 sandwiched between the n source region 1025 and the n drain region 1026 via the gate oxide film 1011.
A gate electrode 1012 connected to the terminal is provided. A source electrode 1023 connected to the S terminal is formed on the surface of the n source region 1025, and an n drain region 1026 is formed.
On the surface of the drain electrode 102 connected to the D terminal
4 are provided respectively. n contact region 101
An auxiliary electrode 1019 is provided on the surface of 6. Further, an interlayer insulating film, a metal wiring, a passivation film, etc. may be formed.

In this element, by applying a voltage equal to or higher than the threshold voltage to the source electrode 1023 to the gate electrode 1012, p just below the gate electrode 1012 is applied.
Inversion layers occur in the surface layers of the base region 1007 and the p buffer region 1032. N source region 1 through the inversion layer
Electrons flow into the n-drain 1026 from 025, and the source electrode 1023 and the drain electrode 1024 are electrically connected.

In this example, since it is an n-channel MOSFET, carriers that contribute to conduction are electrons and not holes, but it is excluded when an inversion layer is formed by applying a voltage to the gate electrode 1012. There are holes. The holes may flow to the p-type substrate 1001 which is the collector of the parasitic pnp transistor. However, the n-well region 1
003 is electrically connected to the n drain region 1026 via the n contact region 1016. Therefore, the holes are not injected into the p-type substrate 1001 by the parasitic pnp transistor. Therefore, the above problem is avoided. As a result, switching loss can be significantly reduced.

The p base region 1007 need not include the n drain region 1026. In addition, the p-well region 10
If the impurity concentration of 03 is carefully examined, p base region 1
In some cases, 007 can be omitted. Also in this case, the n well region 1003 may be made of an epitaxial layer. Even in such a case, the operation of the MOSFET does not change, and the advantages of the present invention can be sufficiently obtained.

FIG. 11 is a sectional view of a lateral bipolar transistor as a power element integrated in a power IC according to an eleventh embodiment of the present invention. An n well region 1103 is formed in the surface layer of the p-type substrate 1101 by introducing and diffusing impurities from the surface. A p well region 1106 is formed on a part of the surface layer of the n well region 1103. Further, an n base region 1108 is formed in a part of the surface layer of the p well region 1106, a p collector region 1114 is formed in a part of the surface layer of the n base region 1108, and a surface layer of the n base region 1108 is formed. An n buffer region 1109 is formed in a portion different from the portion where the p collector region 1114 is formed, and ap emitter region 1127 is formed in the n buffer region 1109. Further, the n contact region 1 is formed on the surface layer of the exposed surface of the n well region 1103.
116 is formed. A base electrode 1129 connected to the B terminal is provided on the surface of the n base region 1108. An emitter electrode 1117 connected to the E terminal is provided on the surface of the p emitter region 1127, and a collector electrode 1118 connected to the C terminal is provided on the surface of the p collector region 1114. An auxiliary electrode 1119 is provided on the surface of the n contact region 1116. Further, an interlayer insulating film, a metal wiring, a passivation film, etc. may be formed.

In this element, the emitter electrode 1117
By passing a base current from the base electrode 1129 to the base electrode 1129, a large amount of holes are injected from the p emitter region 1127 into the n base region 1106, and the emitter electrode 1117 and the collector electrode 1118 are electrically connected. In this example,
The n-well region 1103 in the p-type substrate 1101 has the p-emitter region 1127 via the n-contact region 1116.
Is electrically connected to. Therefore, the p-type substrate 110
The parasitic pnp transistor whose collector is 1 will not turn on. Therefore, the above problems are avoided.
As a result, it is possible to significantly reduce the switching loss as in the case of the above example of the element.

FIG. 12 is a sectional view of a lateral bipolar transistor according to the 12th embodiment of the present invention. p-type substrate 12
N well region 1203 is formed in the surface layer of
A lateral bipolar transistor similar to that of the eleventh embodiment of FIG. 11 is formed on the surface layer of the p-well region 1206 formed on the surface layer of the well region 1203. The difference from the embodiment of FIG. 11 is that the surface layer of the p well region 1206 has p
That is, the collector region 1214 is formed. Also in this case, the operation is the same as that of the above-described embodiment, the same effect is obtained, and the switching loss can be greatly reduced.

Also in the device having the structure shown in FIGS. 11 and 12, auxiliary electrodes 1119 and 1219 are provided as in the second and third embodiments.
Can be held at a higher potential without being connected to the emitter electrodes 1117 and 1217, or the n-well regions 1103 and 1203 can be set to a floating potential without providing an auxiliary electrode. FIG. 13 is a sectional view of a lateral bipolar transistor as a power device integrated in a power IC according to the 13th embodiment of the present invention. By introducing and diffusing impurities from the surface into the surface layer of the p-type substrate 1301,
A well region 1303 is formed. A p well region 1306 is formed on a part of the surface layer of the n well region 1303. Further, a p base region 1307 is formed on a part of the surface layer of the p well region 1306, and an n collector region 1331 is formed on a part of the surface layer of the p base region 1307.
Is formed, a p buffer region 1332 is formed in a portion of the surface layer of the p base region 1307 other than the portion where the n collector region 1331 is formed, and an n emitter region 1315 is formed in the p buffer region 1332. Further, an n contact region 1316 is formed in the surface layer of the exposed surface of the n well region 1303. A base electrode 1329 connected to the B terminal is provided on the surface of the p base region 1307. An emitter electrode 1317 connected to the E terminal is provided on the surface of the n emitter region 1315, and a collector electrode 1318 connected to the C terminal is provided on the surface of the n collector region 1331. An auxiliary electrode 1319 is provided on the surface of the n contact region 1316. Further, an interlayer insulating film, a metal wiring, a passivation film, etc. may be formed.

In this element, a large amount of electrons are injected from the n-emitter region 1315 into the p-base region 1307 by flowing a base current from the base electrode 1329 to the emitter electrode 1317, so that a space between the emitter electrode 1317 and the collector electrode 1318 is generated. Conduct. Then, the p-type substrate 13
The n-well region 1303 in 01 is the n-contact region 1
It is electrically connected to the n collector region 1331 via 316. Therefore, holes, which are the majority carriers in the p base region 1307, are not injected into the p-type substrate 1301 by the parasitic pnp transistor, and the switching loss can be significantly reduced as in the above example of the element. become.

The p base region 1307 may not include the n collector region 1331 or may include only the n collector region 1331. In addition, the p-well region 130
If the impurity concentration of 3 is carefully examined, the p base region 13
In some cases, 07 can be omitted. p buffer area 1332
Is not absolutely necessary. Even in such cases, MOS
The operation of the FET is the same, and the advantages of the present invention can be sufficiently obtained.

14 to 18 are sectional views of a horizontal thyristor as a power element integrated in the power IC of the fourteenth to eighteenth embodiments of the present invention. First, in FIG. 14, an n well region 1403 is formed in the surface layer of the p-type substrate 1401 by introducing and diffusing impurities from the surface. A p well region 1406 is formed on a part of the surface layer of the n well region 1403. Further, the p base region 140 is formed on a part of the surface layer of the p well region 1406.
7 is formed, an n cathode region 1433 is formed in a part of the surface layer of the p base region 1407, and an n base region is formed in a part of the surface layer of the p well region 1406 different from the part where the p base region 1407 is formed. 1408, its surface layer n
The buffer area 1409, and further the n buffer area 140
A p-anode region 1434 is formed in the inner part 9. Further, an n contact region 1416 is formed on the surface layer of the exposed surface of the n well region 1403. p contact region 141 formed in the surface layer of p base region 1407
On the surface of the gate electrode 1412 connected to the G terminal
Is provided. A cathode electrode 1435 connected to the E terminal is provided on the surface of the n cathode region 1433, and an anode electrode 1436 connected to the A terminal is provided on the surface of the p anode region 1434. An auxiliary electrode 1419 is provided on the surface of the n contact region 1416. Further, an interlayer insulating film, a metal wiring, a passivation film, etc. may be formed.

FIG. 15 shows a case where the n base region 1508 of the surface layer of the p well region 1506 is large enough to include the p base region 1507. FIG. 16 shows the p base region 160.
An n base region 1608 is formed in a part of the surface layer of No. 7. In FIG. 17, the p base region is the n base region 1708.
The point is that it is formed so large that it completely includes. In this case, since the p well region 1706 and the p base region overlap, the p base region can be omitted. Gate electrode 1712
Are on the surface of p contact region 1713 formed in p well region 1706.

In FIG. 18, the p base region 1807 is formed so as not to include the n cathode region 1833 but to include the n base region 1808. Gate electrode 1812 is on the surface of p base region 1807. The operation of these elements will be explained with reference to the example of the horizontal thyristor of the fifteenth embodiment, from the gate electrode 1512 to the cathode electrode 1535.
By passing a gate current, the n cathode region 1533
A large amount of electrons are injected into the p base region 1507 and the n base region 1508 from the above, and a large amount of holes are injected from the p anode region 1534. As a result, this thyristor is turned on to cause conductivity modulation, and a large current flows between the A and K terminals. Then, the n-well region 1503 is
P anode region 15 via contact region 1516
It is electrically connected to 34. Therefore, the p-type substrate 1
The parasitic pnp transistor whose collector is 501 does not turn on. Therefore, the problems described above are avoided. As a result, as in the first embodiment, the switching loss can be greatly reduced.

Similar effects can be obtained for other lateral thyristors, and the switching loss can be greatly reduced. As we have repeated many times in these examples, n
The well region may be made of an epitaxial layer. Further, as in the example of the IGBT described above, for example, the auxiliary electrode 1519 on the surface of the n contact region 1516 may not be connected to the anode electrode 1536, and may be kept at a higher potential, or the auxiliary electrode 1519 may not be provided. it can. Even in such a case, the operation as a thyristor is not changed, and the advantages of the present invention can be sufficiently obtained.

19 to 23 are sectional views of a lateral MCT as a power device integrated in the power IC of the nineteenth to twenty-third embodiments of the present invention. First, in FIG. 19, the n-well region 19 is formed in the surface layer on the p-type substrate 1901.
03 is formed, and p is formed on the surface layer of the n well region 1903.
A well region 1906 is formed and its p well region 19 is formed.
A p base region 1907 is formed in the semiconductor layer 06, an n cathode region 1933 is formed in the p base region 1907, and a p cathode region 1937 is formed in the n cathode region 1933. In addition, p of the surface layer of the p well region 1906 is
An n base region 1908 is provided in a portion other than the portion where the base region 1907 is formed, an n buffer region 1909 having an impurity concentration higher than that of the n base region 1908 in the n base region 1908, and a p anode region in a part of the surface layer thereof. 19
34 is formed. A thick oxide film 1910 is provided on the exposed surface of the n base region 1908. An n contact region 1916 is formed on the exposed surface of the n well region 1903. A gate electrode 1912 made of polycrystalline silicon is provided on the surfaces of the n cathode region 1933, the p base region 1907, and the p well region 1906, which are sandwiched between the p cathode region 1937 and the n base region 1908, with a gate oxide film 1911 interposed therebetween. And is connected to the G terminal. n cathode region 1933 and p cathode region 19
A cathode electrode 1935 connected in common with 37 and connected to the K terminal is provided, and an anode electrode 1936 connected to the A terminal is provided on the surface of the p anode region 1934. An auxiliary electrode 1919 is provided on the surface of the n contact region 1916 and is connected to the anode electrode 1936. Further, an interlayer insulating film, a metal wiring, a passivation film, etc. may be formed on the surface.

FIG. 20 shows a case where the n base region 2008 of the surface layer of the p well region 2006 is large enough to include the p base region 2007. The n base region 2008 extends partway below the p base region 2007.
It may include the entire base region 2007. Figure 21
The n base region 2108 is formed in a part of the surface layer of the p base region 2107. In this case, since the p well region 2106 is not sandwiched between the n base region 2108 and the p cathode region 2137, the gate electrode 21
12 is an n cathode region 2133 and a p base region 210.
7 on the surface.

In FIG. 22, the p base region is omitted. Alternatively, it can be considered that the n-type base region 2208 is formed to be large enough to completely include it and overlaps with the p-well region 2206. Of course, the gate electrode 2212 is on the surface of the n cathode region 2233 and the p well region 2206. In FIG. 23, the p base region 2307 is formed so as not to include the n cathode region 2333 but to include the n base region 2308. The gate electrode 2312 is composed of the n cathode region 2333, the p well region 2306 and the p base region 2.
307 on the surface.

The operation of these elements will be described with reference to the example of the lateral MCT of the nineteenth embodiment. By applying a positive voltage higher than the threshold voltage to the gate electrode 1912 and the cathode electrode 1935. Inversion layers are formed in the surface layers of the p base region 1907 and the p well region 1906 just below the gate electrode 1912. Through the inversion layer, electrons flow from the n cathode region 1933 into the n base region 1908 and further into the p anode region 1934. As a result, this electron current becomes a base current of a pnp transistor composed of the p anode region 1934, the n buffer region 1909, the n base region 1908, and the p base region 1907, and this transistor is turned on to cause conductivity modulation. A large current flows between the AK terminals. Conversely, when a negative voltage equal to or higher than the threshold voltage is applied to the gate electrode 1912 with respect to the cathode electrode 1935, an inversion layer is generated in the surface layer of the n cathode region 1933 immediately below the gate electrode 1912. Since the p cathode region 1937 and the p base region 1907 are connected through the inversion layer and the n cathode region 1933 is separated, the n base region 190 is separated.
The electrons cannot be supplied to the transistor 8, the transistor is turned off, and the current between the A and K terminals stops. The n buffer area 1909 is for preventing punch through of the n base area 1908, and can be omitted in some cases.
The n contact region 1916 is for reducing the contact resistance with the auxiliary electrode 1919.

Then, the n well region 1903 is connected to the p contact region 1934 via the n contact region 1916.
Is electrically connected to. Therefore, the p-type substrate 190
The parasitic pnp transistor whose collector is 1 will not turn on. Therefore, the above problems are avoided.
As a result, as in the first embodiment, the switching loss can be greatly reduced.

Similar effects can be obtained for other lateral MCTs, and the switching loss can be greatly reduced.
Also in these examples, the n well region may be formed of an epitaxial layer. Further, for example, the auxiliary electrode 1919 on the surface of the n contact region 1916 is replaced with the anode electrode 1
It is also possible to maintain a higher potential as in the second embodiment of the IGBT described above without connecting to the 936, or to dispose the auxiliary electrode 1919 and not in the outside of the p-well region as in the third embodiment. It is also possible to make the potential of the n-type semiconductor region floating. Even in such a case, the operation as the MCT remains unchanged, and the advantages of the present invention can be sufficiently obtained. Although all of the above-mentioned embodiments show the n-channel type MCT, the structure of the present invention is not limited to the n-channel type MCT, and is also applied to the p-channel type MCT by the symmetrical conduction type semiconductor region. It goes without saying that you can do it.

[0071]

INDUSTRIAL APPLICABILITY Including the n-channel type IGBT, MOSF
In ET, bipolar transistor, thyristor, etc., the element periphery is surrounded by an n-type semiconductor region, or in a p-channel type element, the element periphery is surrounded by a p-type region, and the enclosed semiconductor region is at the same potential as the first main electrode. The connection suppresses the operation of the parasitic transistor and prevents the accumulation of carriers in the substrate and the isolation region. As a result, for example, the switching speed of the IGBT is improved and the current capacity is significantly increased as shown in the embodiments. did. In other semiconductor devices as described above, the switching time can be shortened and the switching loss can be greatly reduced. The enclosed semiconductor region may be kept at a potential higher than that of the first main electrode, or may be a floating potential without providing an electrode.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a lateral IGBT integrated in a power IC according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a lateral IGBT integrated in a power IC according to a second embodiment of the present invention.

FIG. 3 is a sectional view of a lateral IGBT integrated in a power IC according to a third embodiment of the present invention.

FIG. 4 is a sectional view of a lateral IGBT integrated in a power IC according to a fourth embodiment of the present invention.

FIG. 5 is a sectional view of a lateral IGBT integrated in a power IC of a fifth embodiment of the present invention.

FIG. 6 is a sectional view of a lateral IGBT integrated in a power IC according to a sixth embodiment of the present invention.

FIG. 7 is a sectional view of a lateral IGBT integrated in a power IC according to a seventh embodiment of the present invention.

FIG. 8 is a sectional view of a lateral MOSFET integrated in a power IC according to an eighth embodiment of the present invention.

FIG. 9 is a sectional view of a lateral MOSFET integrated in a power IC according to a ninth embodiment of the present invention.

FIG. 10 is a sectional view of a lateral MOSFET integrated in a power IC according to a tenth embodiment of the present invention.

FIG. 11 is a sectional view of a lateral bipolar transistor integrated in a power IC according to an eleventh embodiment of the present invention.

FIG. 12 is a sectional view of a lateral bipolar transistor integrated in a power IC according to a twelfth embodiment of the present invention.

FIG. 13 is a sectional view of a lateral bipolar transistor integrated in a power IC according to a thirteenth embodiment of the present invention.

FIG. 14 is a sectional view of a horizontal thyristor integrated in a power IC according to a fourteenth embodiment of the present invention.

FIG. 15 is a sectional view of a horizontal thyristor integrated in a power IC according to a fifteenth embodiment of the present invention.

FIG. 16 is a sectional view of a horizontal thyristor integrated in a power IC according to a sixteenth embodiment of the present invention.

FIG. 17 is a sectional view of a horizontal thyristor integrated in a power IC according to a seventeenth embodiment of the present invention.

FIG. 18 is a sectional view of a horizontal thyristor integrated in a power IC according to an eighteenth embodiment of the present invention.

FIG. 19 is a sectional view of a lateral MOS control thyristor integrated in a power IC according to a nineteenth embodiment of the present invention.

FIG. 20 is a sectional view of a lateral MOS control thyristor integrated in a power IC according to a twentieth embodiment of the present invention.

FIG. 21 is a sectional view of a lateral MOS control thyristor integrated in a power IC according to a twenty-first embodiment of the present invention.

FIG. 22 is a sectional view of a lateral MOS control thyristor integrated in a power IC according to a twenty second embodiment of the present invention.

FIG. 23 is a sectional view of a lateral MOS control thyristor integrated in a power IC according to a twenty third embodiment of the present invention.

FIG. 24 is a lateral IGBT integrated in a conventional power IC.
Cross section of

FIG. 25 is another lateral IG integrated in a conventional power IC
BT cross section

[Explanation of symbols]

The last two digits are the names of the following parts, and the one or two digits above them are the numbers of the examples. 01 p-type substrate 02 n buried layer 03 n epitaxial layer or n
Well region 04 n sinker 05 p isolation 06 p well region 07 p base region 08 n base region 09 n buffer region 10 thick oxide film 11 gate oxide film 12 gate electrode 13 p contact region 14 p collector region 15 n emitter region 16 n Contact region 17 Emitter electrode 18 Collector electrode 19 Auxiliary electrode 21 p Source region 22 p Drain region 23 Source electrode 24 Drain electrode 25 n Source region 26 n Drain region 27 p Emitter region 29 Base electrode 31 n Collector region 32 p Buffer region 33 n Cathode region 34 p Anode region 35 Cathode electrode 36 Anode electrode 37 p Cathode region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical indication location H01L 29/74 N 29/78 301 W 9055-4M 655 Z

Claims (33)

[Claims] 1. A first and a second main electrode are formed in and on a first conductivity type well region formed in a part of a surface layer of a second conductivity type semiconductor region on a first conductivity type semiconductor layer. A lateral semiconductor device having a semiconductor element having a control electrode. 2. The lateral semiconductor device according to claim 1, wherein an auxiliary electrode is provided on the surface of the second conductivity type semiconductor region. 3. The lateral semiconductor device according to claim 1, wherein an auxiliary electrode is provided on the surface of the second conductivity type region in contact with the second conductivity type semiconductor region. 4. The lateral semiconductor device according to claim 2, wherein the first main electrode and the auxiliary electrode are electrically connected. 5. The lateral semiconductor device according to claim 1, wherein the exposed surface portion of the second conductivity type semiconductor region and the second conductivity type region in contact with the second conductivity type semiconductor region is covered with an insulating film. . 6. The lateral semiconductor device according to claim 1, wherein the semiconductor element is any one of a transistor, a thyristor, a MOSFET, an insulated gate bipolar transistor, and a MOS control thyristor. 7. A semiconductor element is formed on a first conductivity type base region formed on a part of a surface layer of a first conductivity type well region and on a part of a surface layer of the first conductivity type base region. A second conductivity type emitter region, a second conductivity type base region formed apart from the first conductivity type base region, and a first conductivity type collector region formed in a surface layer of the second conductivity type base region, A gate electrode formed via a gate insulating film on the surface of the first conductivity type region sandwiched between the second conductivity type base region and the second conductivity type emitter region, the second conductivity type emitter and the first conductivity type. It has an emitter electrode which is a second main electrode provided in common contact with the surface of the mold base region, and a collector electrode which is a first main electrode provided on the surface of the first conductivity type collector region. Must be a lateral insulated gate bipolar transistor The semiconductor device according to claim 6, wherein. 8. A semiconductor element is formed on a second conductivity type base region formed on a part of the surface layer of the first conductivity type well region and on a part of the surface layer of the second conductivity type base region. The first conductivity type base region, the second conductivity type emitter region formed in a part of the surface layer of the first conductivity type base region, and the first conductivity type base region of the surface layer of the second conductivity type base region are A gate insulating film is provided on the surface of the first-conductivity-type base region that is sandwiched between the first-conductivity-type collector region and the second-conductivity-type base region that is formed in the portion that is not formed. Of the first conductivity type collector region, the emitter electrode that is a second main electrode provided in common contact on the surfaces of the second conductivity type emitter and the first conductivity type base region, and Collector electrode which is the first main electrode provided on the surface and The semiconductor device according to claim 6, characterized in that the lateral insulated gate bipolar transistor having. 9. A semiconductor element is formed on a first conductivity type base region formed on a part of a surface layer of a first conductivity type well region and on a part of a surface layer of the first conductivity type base region. A second conductivity type emitter region, a second conductivity type base region formed in a portion of the surface layer of the first conductivity type base region where the second conductivity type emitter region is not formed, and a second conductivity type base region A gate insulating film is provided on the surface of the first conductivity type collector region formed in a part of the surface layer and the first conductivity type base region sandwiched between the second conductivity type base region and the second conductivity type emitter region. Of the gate electrode formed as a second main electrode, the emitter electrode which is a second main electrode provided in common contact on the surfaces of the second conductivity type emitter and the first conductivity type base region, and the first conductivity type collector region. Collector electrode which is the first main electrode provided on the surface The semiconductor device according to claim 6, characterized in that the lateral insulated gate bipolar transistor having a. 10. A semiconductor element comprising a second conductivity type emitter region formed in a part of a surface layer of a first conductivity type well region,
The second conductivity type base region is formed in a portion of the surface layer of the first conductivity type well region where the second conductivity type emitter region is not formed, and is formed in a part of the surface layer of the second conductivity type base region. A first conductivity type collector region, a gate electrode formed via a gate insulating film on the surface of a first conductivity type well region sandwiched between a second conductivity type base region and a second conductivity type emitter region, An emitter electrode, which is a second main electrode provided in common on the surfaces of the second conductivity type emitter and the first conductivity type well region, and a first electrode provided on the surface of the first conductivity type collector region. The semiconductor device according to claim 6, which is a lateral insulated gate bipolar transistor having a collector electrode which is a main electrode. 11. A semiconductor element, a second conductivity type emitter region formed in a part of a surface layer of a first conductivity type well region,
The first conductivity type base region is formed on a portion of the surface layer of the first conductivity type well region where the second conductivity type emitter region is not formed, and is formed on a part of the surface layer of the first conductivity type base region. A second conductivity type base region, a first conductivity type collector region formed in a part of a surface layer of the second conductivity type base region, a second conductivity type base region and a second conductivity type emitter region. And a gate electrode formed on the surface of the first conductivity type base region via a gate insulating film, and provided in common contact on the surfaces of the second conductivity type emitter and the first conductivity type base region. 7. A lateral insulated gate bipolar transistor having an emitter electrode which is a second main electrode and a collector electrode which is a first main electrode provided on the surface of the first conductivity type collector region. The semiconductor device described. 12. A semiconductor element is formed on a second conductivity type base region formed on a part of the surface layer of a first conductivity type well region and on a part of a surface layer of the second conductivity type base region. A first conductivity type drain region; a first conductivity type source region formed in a portion of the surface layer of the first conductivity type well region where the second conductivity type base region is not formed; On the surface of the second conductivity type base region sandwiched between the first conductivity type drain region and the gate electrode formed via the gate insulating film, and on the surface of the first conductivity type source region and the second conductivity type base region. Is a lateral MOSFET having a source electrode which is a second main electrode provided in common contact with each other and a drain electrode which is a first main electrode provided on the surface of the first conductivity type drain region. The semiconductor device according to claim 6. 13. A semiconductor element is formed on a second conductivity type base region formed on a part of the surface layer of the first conductivity type well region and on a part of the surface layer of the second conductivity type base region. A first conductivity type source region, a first conductivity type drain region formed in a portion of the surface layer of the second conductivity type base region where the first conductivity type source region is not formed, and the first conductivity type source region; A gate electrode formed via a gate insulating film on the surface of the second conductivity type base region sandwiched by the first conductivity type drain region, and the surfaces of the first conductivity type source region and the first conductivity type base region. A lateral MOSFET having a source electrode, which is a second main electrode provided in common above, and a drain electrode, which is a first main electrode, provided on the surface of the first conductivity type drain region. Claim 6 characterized by the above-mentioned.
The semiconductor device according to. 14. A semiconductor element, and a second conductivity type drain region formed in a part of a surface layer of the first conductivity type well region,
A second conductivity type source region formed in a portion of the surface layer of the first conductivity type well region where the second conductivity type drain region is not formed, and the second conductivity type source region and the second conductivity type drain region. A gate electrode formed on the surface of the sandwiched first conductivity type well region via a gate insulating film, a source electrode that is a second main electrode provided on the surface of the second conductivity type source region, A lateral M having a drain electrode which is a first main electrode provided on the surface of the two-conductivity type drain region.
The semiconductor device according to claim 6, which is an OSFET. 15. A semiconductor element is formed on a second conductivity type base region formed on a part of the surface layer of the first conductivity type well region and on a part of the surface layer of the second conductivity type base region. The first conductivity type emitter region, the first conductivity type collector region formed in a portion of the surface layer of the first conductivity type well region where the second conductivity type base region is not formed, and the surface of the second conductivity type base region. The gate electrode formed on the above, the emitter electrode that is the first main electrode provided on the surface of the first conductivity type emitter region, and the second main electrode provided on the surface of the first conductivity type collector region. 7. The semiconductor device according to claim 6, which is a lateral bipolar transistor having a collector electrode. 16. A semiconductor element is formed on a second conductivity type base region formed on a part of the surface layer of the first conductivity type well region and on a part of the surface layer of the second conductivity type base region. The first conductivity type emitter region, the first conductivity type collector region formed in a portion of the surface layer of the first conductivity type well region where the second conductivity type base region is not formed, and the surface of the second conductivity type base region. A gate electrode provided above, an emitter electrode that is a first main electrode provided on the surface of the first conductivity type emitter region, and a second main electrode provided on the surface of the first conductivity type collector region. 7. The semiconductor device according to claim 6, which is a lateral bipolar transistor having a collector electrode. 17. A semiconductor element comprising a second conductivity type emitter region formed in a part of a surface layer of a first conductivity type well region,
A second conductivity type collector region formed in a portion of the surface layer of the first conductivity type well region where the second conductivity type emitter region is not formed, and a surface of the first conductivity type region in the first conductivity type well region. A base electrode formed on the upper surface, an emitter electrode that is a second main electrode provided on the surface of the second conductivity type emitter region, and a first main electrode provided on the surface of the second conductivity type collector region. 7. The semiconductor device according to claim 6, which is a lateral bipolar transistor having a collector electrode. 18. A semiconductor element is formed on a first conductivity type base region formed on a part of a surface layer of a first conductivity type well region and on a part of a surface layer of the first conductivity type base region. Second conductivity type cathode region, second conductivity type base region formed in a part of the surface layer of the first conductivity type well region away from the first conductivity type base region, and surface of the second conductivity type base region A first conductivity type anode region formed in the layer, a gate electrode formed on the surface of the first conductivity type base region, and a cathode serving as a second main electrode provided on the surface of the second conductivity type cathode region. 7. The semiconductor device according to claim 6, wherein the semiconductor device is a horizontal thyristor having an electrode and an anode electrode which is a first main electrode provided on the surface of the first conductivity type anode region. 19. A semiconductor element is formed on a second conductivity type base region formed on a part of the surface layer of the first conductivity type well region and on a part of the surface layer of the second conductivity type base region. The first conductivity type base region, the second conductivity type cathode region formed in a part of the surface layer of the first conductivity type base region, and the first conductivity type base region of the surface layer of the second conductivity type base region A first conductivity type anode region formed in a portion not formed, a gate electrode formed on the surface of the first conductivity type base region, and a second main electrode provided on the surface of the second conductivity type cathode region. 7. The semiconductor device according to claim 6, wherein the semiconductor device is a horizontal thyristor having a cathode electrode which is an electrode and an anode electrode which is a first main electrode provided on the surface of the first conductivity type anode region. 20. A semiconductor element is formed on a first conductivity type base region formed on a part of a surface layer of a first conductivity type well region and on a part of a surface layer of the first conductivity type base region. A second conductivity type cathode region, a second conductivity type base region formed in a portion of the surface layer of the first conductivity type base region where the second conductivity type cathode region is not formed, and a second conductivity type base region of the second conductivity type base region. A first conductivity type anode region formed on a part of the surface layer, a gate electrode formed on the surface of the first conductivity type base region, and a second main electrode provided on the surface of the second conductivity type cathode region. 7. The semiconductor device according to claim 6, wherein the semiconductor device is a horizontal thyristor having a cathode electrode which is an electrode and an anode electrode which is a first main electrode provided on the surface of the first conductivity type anode region. 21. A semiconductor device, comprising: a second conductivity type cathode region formed in a part of a surface layer of a first conductivity type well region;
The second conductivity type base region is formed in a portion of the surface layer of the first conductivity type well region where the second conductivity type cathode region is not formed, and is formed in a part of the surface layer of the second conductivity type base region. A first conductivity type anode region, a gate electrode formed on the surface of the first conductivity type well region, a cathode electrode that is a second main electrode provided on the surface of the second conductivity type cathode region, The semiconductor device according to claim 6, wherein the semiconductor device is a lateral thyristor having an anode electrode that is a first main electrode provided on the surface of the one conductivity type anode region. 22. A semiconductor element, comprising a second conductivity type cathode region formed in a part of a surface layer of the first conductivity type well region,
The first conductivity type base region is formed in a portion of the surface layer of the first conductivity type well region where the second conductivity type cathode region is not formed, and is formed in a part of the surface layer of the first conductivity type base region. A second conductivity type base region, a first conductivity type anode region formed in a part of the surface layer of the second conductivity type base region, and a gate electrode formed on the surface of the first conductivity type base region. A horizontal thyristor having a cathode electrode which is a second main electrode provided on the surface of the second conductivity type cathode region and an anode electrode which is a first main electrode provided on the surface of the first conductivity type anode region 7. The semiconductor device according to claim 6, wherein 23. A semiconductor element is formed on a first conductivity type base region formed on a part of a surface layer of a first conductivity type well region and on a part of a surface layer of the first conductivity type base region. A second conductivity type cathode region, a first conductivity type cathode region formed in a part of the surface layer of the second conductivity type cathode region, and a second conductivity type base formed apart from the first conductivity type base region. A region, a first conductivity type anode region formed in the surface layer of the second conductivity type base region, a second conductivity type cathode region sandwiched between the second conductivity type base region and the first conductivity type cathode region, A gate electrode formed on the surfaces of the first-conductivity-type base region and the first-conductivity-type well region via a gate insulating film, and commonly on the surfaces of the first-conductivity-type cathode region and the second-conductivity-type cathode region. The second main electrode provided in contact And over cathode electrode, the semiconductor device according to claim 6, characterized in that the lateral MOS gate thyristor having an anode electrode as a first main electrode provided on a surface of the first conductivity type anode region. 24. A semiconductor element is formed on a second conductivity type base region formed on a part of the surface layer of the first conductivity type well region and on a part of the surface layer of the second conductivity type base region. A first conductivity type base region, a second conductivity type cathode region formed on a part of the surface layer of the first conductivity type base region, and a part of a surface layer of the second conductivity type cathode region A first conductivity type cathode region, a first conductivity type anode region formed in a part of a surface layer of the second conductivity type base region away from the first conductivity type base region, a second conductivity type base region, and A gate electrode formed on the surfaces of the second conductivity type cathode region and the first conductivity type base region sandwiched by the conductivity type cathode region via a gate insulating film, the first conductivity type cathode region and the second conductivity type. Provided in common contact on the surface with the cathode region A cathode electrode which is a second main electrode,
7. The semiconductor device according to claim 6, wherein the semiconductor device is a lateral MOS gate thyristor having an anode electrode which is a first main electrode provided on the surface of the first conductivity type anode region. 25. A semiconductor element is formed on a first conductivity type base region formed on a part of a surface layer of a first conductivity type well region and on a part of a surface layer of the first conductivity type base region. A second conductivity type cathode region, a first conductivity type cathode region formed on a part of the surface layer of the second conductivity type cathode region, and a second conductivity type on a part of the surface layer of the first conductivity type base region. A second conductivity type base region formed apart from the cathode region, a first conductivity type anode region formed in a part of a surface layer of the second conductivity type base region, a second conductivity type base region and a first conductivity type base region. A gate electrode formed on the surfaces of the second conductivity type cathode region and the first conductivity type base region sandwiched by the conductivity type cathode region via a gate insulating film, the first conductivity type cathode region and the second conductivity type. Provided in common contact on the surface with the cathode region 7. A lateral MOS gate thyristor having a cathode electrode which is a second main electrode and an anode electrode which is a first main electrode provided on the surface of the first conductivity type anode region. The semiconductor device described. 26. A second conductivity type cathode region, wherein the semiconductor element is formed in a part of a surface layer of the first conductivity type well region,
The first conductivity type cathode region formed on a part of the surface layer of the second conductivity type cathode region and the part of the surface layer of the first conductivity type well region formed apart from the second conductivity type cathode region The second conductivity type base region, the first conductivity type anode region formed in a part of the surface layer of the second conductivity type base region, and the second conductivity type base region and the first conductivity type cathode region. Common to the gate electrode formed on the surfaces of the second conductivity type cathode region and the first conductivity type well region via the gate insulating film, and the surface of the first conductivity type cathode region and the second conductivity type cathode region A lateral MOS gate thyristor having a cathode electrode which is a second main electrode provided in contact with the anode and an anode electrode which is a first main electrode provided on the surface of the first conductivity type anode region. And claim 6 Mounting semiconductor device. 27. A semiconductor element, and a second conductivity type cathode region formed in a part of a surface layer of the first conductivity type well region,
The first conductivity type cathode region formed on a part of the surface layer of the second conductivity type cathode region and the part of the surface layer of the first conductivity type well region formed apart from the second conductivity type cathode region A first conductivity type base region, a second conductivity type base region formed on a part of the surface layer of the first conductivity type base region, and a part of a surface layer of the second conductivity type base region On the surface of the first conductivity type anode region, the second conductivity type cathode region sandwiched between the second conductivity type base region and the first conductivity type cathode region, the first conductivity type well region and the first conductivity type base region. A gate electrode formed via a gate insulating film, a cathode electrode which is a second main electrode provided in common contact on the surfaces of the first conductivity type cathode region and the second conductivity type cathode region, and Provided on the surface of one conductivity type anode region The semiconductor device according to claim 6, characterized in that the lateral MOS gate thyristor having an anode electrode which is one main electrode. 28. The lateral semiconductor device according to claim 1, wherein the second conductivity type semiconductor region is formed on the first conductivity type semiconductor substrate. 29. The lateral type according to claim 1, wherein the second conductivity type semiconductor region is formed in a part of a surface layer of the first conductivity type semiconductor substrate. Semiconductor device. 30. A second-conductivity-type buried layer having an impurity concentration higher than that of the second-conductivity-type semiconductor layer formed at a part of an interface between the first-conductivity-type semiconductor substrate and the second-conductivity-type semiconductor layer, and an anode electrode. 29. The horizontal type according to claim 28, further comprising a second conductivity type sinker having a higher impurity concentration than the second conductivity type semiconductor layer reaching from the surface of the second conductivity type semiconductor layer to the second conductivity type buried layer. Semiconductor device. 31. A buffer region having an impurity concentration higher than that of the semiconductor region of the opposite conductivity type is provided between the semiconductor region in contact with the first main electrode and the semiconductor region of the opposite conductivity type below the semiconductor region. The lateral semiconductor device according to any one of 1 to 13, 15, 16, and 18 to 30. 32. The first and second wells formed in and on the first conductivity type well region formed in a part of the surface layer of the second conductivity type semiconductor region on the first conductivity type semiconductor layer. In a method of using a lateral semiconductor device having a main electrode and a control electrode and having an auxiliary electrode on the surface of the second conductivity type semiconductor region, applying a higher potential to the auxiliary electrode than the first and second main electrodes. A method of using a lateral semiconductor device, comprising: 33. First and second wells formed in and on a first conductivity type well region formed in a part of the surface layer of the second conductivity type semiconductor region on the first conductivity type semiconductor layer. In a method for using a lateral semiconductor device having a main electrode and a control electrode, and having an auxiliary electrode on the surface of a second conductivity type region in contact with the second conductivity type semiconductor region, the auxiliary electrode includes a first electrode and a second electrode. A method of using a lateral semiconductor device, which is characterized by applying a higher potential than that of a main electrode.