JPH08148573A - Semiconductor device - Google Patents

Abstract

(57) [Summary] (Correction) [Purpose] To increase the product yield of large-scale integrated circuit devices LSI and the like in which a plurality of microprocessors that can operate independently logically are mounted on the same chip. In a large-scale integrated circuit device LSI or the like having a plurality of microprocessors MPU1 to MPU8 which are coupled to a common system bus SBUS and can operate logically independently, a microprocessor corresponding to each microprocessor Is provided with a bus interface circuit BI that selectively and logically connects the microprocessor and the system bus SBUS when each of the microprocessors can operate normally, and each microprocessor is connected to the power supply wiring formed of the uppermost metal wiring layer. To supply operating power,
By selectively disconnecting the power supply wiring with a focused ion beam or the like, the microprocessor having an unavoidable failure inside is disconnected from the bus and brought into a non-operating state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and is used, for example, for high-performance large-scale integrated circuit devices having a plurality of microprocessors mounted on one chip (semiconductor substrate) and for improving the product yield thereof. And particularly effective technology.

[0002]

2. Description of the Related Art There is a microprocessor in which a central processing unit which is the central portion of the chip and a random access memory which is a cache memory are mounted on one chip.
Further, as one means for increasing the processing capability of such a microprocessor or the like, a plurality of processing units capable of operating in parallel are provided in a central processing unit and a plurality of instructions are simultaneously executed so that a CPI (Cycle) of the microprocessor or the like is executed.
There is a so-called superscalar system that can reduce the Per Instruction.

For microprocessors adopting the superscalar system, see, for example, "1994 I.S.
SCC (ISSCC: Internet)
nal Solid State Circuits
(Conference) Digest of Technical Papers (Digest Of Technic)
al Papers), pp. 212-213.

[0004]

In recent years, the performance of microprocessors and the like has been remarkably improved, and there is a great need for higher performance. In such a situation, in the conventional microprocessor in which one central processing unit is mounted on one chip, as means for meeting this need, (1) the cycle time of the microprocessor itself is accelerated (2) The above The superscalar system is adopted and the number of instructions that can be executed simultaneously is increased by adding the processing unit in the central processing unit. (3) Multiple microprocessors formed on individual chips are logically connected and parallelized by these microprocessors. There is no choice but to adopt a method such as processing. However, the method (1) cannot be expected to have a dramatic effect in view of the current situation that the miniaturization and high integration technology of integrated circuits is approaching its limit, and (3)
In the method (1), the effect is limited because the transmission delay time of the signal between chips becomes large. In the method (2), the control logic for allocating instructions to each processing unit becomes complicated as the number of processing units is increased, so that the chip size of the microprocessor increases and its operating frequency decreases, and at the same time, Since there are few types of instructions that can be executed, the expected effect cannot be obtained.

For these reasons, a plurality of microprocessors involved in parallel processing will be formed on the same chip in the future, and the transmission delay time of signals between the microprocessors will be shortened to construct a high-performance large-scale integrated circuit device. However, there is a limit to miniaturization and high integration technology, and an increase in chip size cannot be denied. Further, as the number of microprocessors formed on the same chip increases, the number of elements of the large scale integrated circuit device increases, and the failure occurrence rate increases. For this reason, in the current state of the digital integrated circuit field in which a reliable relief technique is not established other than the separate shipment by the operable clock frequency, the product yield of the large-scale integrated circuit device is reduced, which prevents the cost reduction. The problem arises.

An object of the present invention is to increase the product yield of a large-scale integrated circuit device or the like in which a plurality of modules such as microprocessors which can operate independently logically are mounted on the same chip, and to reduce the cost. It is to plan.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, in a large-scale integrated circuit device in which a plurality of modules such as a microprocessor, which are coupled to a common bus and can operate independently logically, are mounted on the same chip, each module has a corresponding module. A bus enable circuit for selectively setting its output signal to a valid level when it can operate at any time, and a bus interface circuit for selectively logically connecting a corresponding module and a bus in accordance with the output signal of the bus enable circuit. At the same time, operating power is supplied to each module through the power supply wiring consisting of the uppermost metal wiring layer, and this power supply wiring is selectively cut off by a focused ion beam, etc. No Disconnect the failed module from the bus and put it in a non-operational state. In addition, a large-scale integrated circuit device including such a non-operating module is shipped as a partial product having relatively low processing capability.

[0009]

According to the above-mentioned means, even when a plurality of modules mounted on a large scale integrated circuit device or the like includes a module having an unavoidable fault, it is separated from the bus, that is, other modules and shipped as a partial product. Therefore, the product yield of large-scale integrated circuit devices and the like can be increased and the cost thereof can be reduced.

[0010]

1 is a system configuration diagram of an embodiment of a large scale integrated circuit device LSI (semiconductor device) to which the present invention is applied. Further, FIG. 2 shows a microprocessor MP mounted on the large-scale integrated circuit device LSI of FIG.
A block diagram of one embodiment of U1 is shown. further,
3 shows a circuit diagram of an embodiment of the bus enable circuit BE and the bus interface circuit BI included in the microprocessor MPU1 of FIG. 2, and FIG. 4 shows a power supply of the large scale integrated circuit device LSI of FIG. A partial cross-sectional structural diagram of one embodiment of the supply wiring is shown. Based on these drawings, the configuration and operation of the large-scale integrated circuit device LSI, the microprocessors MPU1 to MPU8, the bus enable circuit BE and the bus interface circuit BI, and the features thereof will be described with reference to these drawings. The circuit elements shown in FIG. 3 and the circuit elements constituting the blocks shown in FIGS. 1 and 2 are manufactured by a known semiconductor integrated circuit manufacturing technique.
It is formed on one semiconductor substrate such as single crystal silicon. Further, a detailed description of the microprocessors MPU1 to MPU8 will be described with reference to the microprocessor MPU of FIG.
1 is taken as an example, but other microprocessor M
Since the PU2 to MPU8 have the same configuration, please infer them.

In FIG. 1, a large-scale integrated circuit device LSI of this embodiment has eight modules which can operate independently logically, that is, microprocessors MPU1 to MPU1.
The MPU 8 is provided, and one bus controller BUSC commonly provided to these microprocessors is provided.
Each of the microprocessors MPU1 to MPU8 includes a bus interface circuit BI, is coupled to the system bus SBUS via the bus interface circuit, and is further coupled to the bus controller BUSC. The bus controller BUSC is a power-on reset circuit PORS.
, And is coupled below to the external bus EBUS. A storage device, an input / output device, and the like (not shown) are coupled to the external bus EBUS. Further, the large-scale integrated circuit device LSI is supplied with a power supply voltage VCC of + 5V (volt) and a ground potential V of 0V from an external power supply device (not shown).
SS is supplied as an operating power supply. Of these, the power supply voltage VCC is the power supply wiring, that is, the power supply voltage supply wiring SLV.
It is supplied to the microprocessors MPU1 to MPU8 and the bus controller BUSC via C, and the ground potential V
SS is supplied to each device through the ground potential supply wiring SLVS.

The bus controller BUSC includes microprocessors MPU1 to MPU for the system bus SBUS.
The access of U8 is managed and controlled, and the bus access right is selectively given to the microprocessor having the bus access request in a predetermined priority order. Further, the microprocessor having the bus access right and the external bus EBUS are selectively logically coupled, and data exchange is performed between the microprocessor and the storage device or the input / output device coupled to the external bus. Mediate.

In this embodiment, each of the microprocessors MPU1 to MPU8 is selectively disconnected from the system bus SBUS by disconnecting the fuse F1 of the corresponding bus enable circuit BE, as described later, and its power supply voltage is increased. The supply wiring SLVC is selectively brought into a non-operating state by being cut at, for example, the portion marked with X in FIG. Also, the microprocessor MPU1
~ The MPU 8 has a function of exchanging a previously given identification code with the bus controller BUSC when it can operate normally, and the power-on reset circuit PORS of the bus controller BUSC has an identification code when the power is turned on. Of microprocessors MPU1 to MPU
8 has a function of identifying the operating state and selectively constructing a digital processing device having a different processing capacity according to the number of microprocessors that can operate normally. As a result, the large-scale integrated circuit device LSI of this embodiment can be shipped as a partial product while including a microprocessor having some unavoidable obstacle therein, thereby increasing the product yield and reducing the cost. Is planned.

By the way, in the large-scale integrated circuit device LSI of this embodiment, as shown in FIG. 4, three aluminum wiring layers (metal wiring layers) are prepared for use in forming the wiring paths in the chip. To be done. Of these, the semiconductor substrate S
The lowermost layer closest to the UB, that is, the first aluminum wiring layer AL1 is mainly used as an inter-element signal wiring SLID for coupling elements such as MOSFETs formed on the surface of the substrate. The second aluminum wiring layer AL2 is mainly connected to the microprocessors MPU1 to MPU8 with the ground potential V.
It is used as a ground potential supply wiring SLVS for supplying SS, and is the uppermost layer, that is, the third layer aluminum wiring layer A.
L3 mainly supplies the power supply voltage V to these microprocessors.
It is used as a power supply voltage supply wiring SLVC for supplying CC. That is, in the large-scale integrated circuit device LSI of this embodiment, the power supply voltage supply line SLVC that is selectively disconnected to bring the microprocessor in which an unavoidable failure has occurred into a non-operating state is a focused ion beam. It is composed of the uppermost aluminum wiring layer AL3 that can be easily cut by the FIB, so that the cutting work of the power supply voltage supply wiring SLVC becomes efficient.

Next, the microprocessors MPU1-MP
U8 has, as a representative of the microprocessor MPU1 of FIG. 2, a central processing unit CPU of a stored program system as its basic constituent element. Central processing unit CP
As described above, U is supplied with the power supply voltage VCC and the ground potential VSS, which are operation power supplies, through the power supply voltage supply wiring SLVC and the ground potential supply wiring SLVS, and a predetermined clock signal CLK is supplied from a clock generation circuit (not shown). Supplied. In addition, the central processing unit CPU has an internal bus I
The random access memory RAM, the special function unit SFU, and the bus interface circuit BI are coupled via the BUS, and the bus enable circuit BE is coupled to the bus interface circuit BI.

The random access memory RAM functions as a so-called cache memory, and the central processing unit CPU
Temporarily holds programs and operation data necessary for controlling the operation of the. Further, the central processing unit CPU operates synchronously in accordance with the clock signal CLK and performs step operation in accordance with a program held in the random access memory RAM to perform a predetermined logical operation processing, and controls / controls each unit of the microprocessor MPU1. . On the other hand, the special function unit SFU substitutes a part of the arithmetic function of the central processing unit CPU, and the bus interface circuit BI has the internal bus IBUS of the corresponding microprocessor MPU1 according to the bus enable signal BEN supplied from the bus enable circuit BE. And system bus SB
Selectively logically connect with US. Further, the bus enable circuit BE includes a fuse F1 that is selectively cut off when some unavoidable failure occurs in the microprocessor MPU1, and when the fuse is not in the cut state, in other words, the microprocessor MPU1 is normal. Output signal, that is, the bus enable signal BEN, is selectively set to a valid level, that is, a high level.

Here, the bus enable circuit BE is shown in FIG.
, A fuse F1 provided between the power supply voltage VCC and the input terminal of the inverter V1 and an N-channel MOSFET (metal oxide semiconductor type electric field provided between the input terminal of the inverter V1 and the ground potential VSS). In this specification, a MOSFET is referred to as an insulated gate field effect transistor generically) N1
And The output signal of the inverter V1 is MOSFET
The signal is supplied to the gate of N1, inverted by the inverter V2, and then supplied to the bus interface circuit BI as an output signal of the bus enable circuit BE, that is, a bus enable signal BEN.

When the microprocessor MPU1 operates normally and the fuse F1 is not cut off, in the bus enable circuit BE, the input terminal of the inverter V1 is coupled to the power supply voltage VCC via the fuse F1 and the output signal thereof is grounded. It is set to a low level like VSS. Therefore, the MOSFET N1 is turned off, and the output signal of the bus enable circuit BE, that is, the bus enable signal BEN is set to the effective level, that is, the high level such as the power supply voltage VCC.

On the other hand, when some unavoidable failure occurs in the microprocessor MPU1 and the fuse F1 is in the cut state, the bus enable circuit BE turns on the MOSFET N1 in response to power-on, whereby the inverter V1 is turned on. The output signal is at a high level like the power supply voltage VCC. Further, when the output signal of the inverter V1 is at the high level, the MOSFET N1 is kept in the ON state to be latched with the inverter V1, and the output signal of the bus enable circuit BE, that is, the bus enable signal BEN is at the low level like the ground potential VSS. It is said that
In this way, the output signal of the bus enable circuit BE, that is, the bus enable signal BEN, is output from the microprocessor MP.
When U1 is in a normal operation state and fuse F1 is not in a cut state, it is selectively set to an effective level, that is, a high level.

Next, the bus interface circuit BI is provided in correspondence with the bits BA1 to BAi of the system bus SBUS, each of i bus receivers BR and bus drivers BD, and j provided in correspondence with the bits BB1 to BBj. Bus receivers BR and bits BC1 to B
It includes k bus drivers BD provided corresponding to Ck. Among them, the bus receiver BR is composed of a so-called AND type receiver, and one input terminal thereof has corresponding bits BA1 to B of the system bus SBUS.
It is bound to Ai and BB1 to BBj, respectively. Further, the bus enable circuit BE is connected to the other input terminal.
To the bus enable signal BEN in common, and its output signal is output to the corresponding bits of the internal bus IBUS as the bus input signals IBA1 to IBAi and IBB1 to IBBj.

As a result, each of the bus receivers BR is selectively brought into the transmission state by the high level of the bus enable signal BEN, and the corresponding bits BA1 to BAi and BB1 to BBj of the system bus SBUS are selectively transmitted.
The input signals supplied via the bus input signals IBA1 to IBAi and IBB1 to IBB.
It is transmitted to the corresponding bit of the internal bus IBUS as j.

On the other hand, each bus driver BD of the bus interface circuit BI comprises a tri-state output type driver, and its input terminals receive the bus output signals OBA1 to OBAi and OBC1 to OBCk from the corresponding bits of the internal bus IBUS. Each is supplied. The bus enable signal BEN is commonly supplied to the non-inversion control terminal, and the AND gate AG is connected to the inversion control terminal.
1 output signal, that is, the output enable signal OE, is an inverted signal by the inverter V3, that is, an inverted output enable signal O.
B is commonly supplied. The output terminals of each bus driver BD have corresponding bits BA1 to B of the system bus SBUS.
It is bound to Ai and BC1 to BCk, respectively. The bus enable signal BE is supplied from the bus enable circuit BE to one input terminal of the AND gate AG1.
An output control signal OC is supplied to the other input terminal from a control circuit (not shown).

From these facts, the output signal of the AND gate AG1, that is, the output enable signal OE, causes the microprocessor MPU1 to operate normally when the bus enable signal BEN and the output control signal OC are both set to the high level. When it is in a ready state and has an access right to the system bus SBUS, it is selectively set to the high level, and the inverted output enable signal OB is selectively set to the high level on the condition complementary thereto. Further, each bus driver BD is selectively brought into a transmission state by setting the output enable signal OE to the high level and the inverted output enable signal OB to the low level, and is supplied through the corresponding bit of the internal bus IBUS. The bus output signals OBA1 to OBAi and OBC1 to OBCk are output to the corresponding bits of the system bus SBUS. When the output enable signal OE is low level and the inverted output enable signal OB is high level, the output of each bus driver BD is in a high impedance state.

As a result of the above, the bus interface circuit BI
Is an effective level, that is, a high level of the output signal of the bus enable circuit BE, that is, the bus enable signal BEN, so that the corresponding microprocessor MPU1 and the system bus SBUS are selectively logically coupled, in other words, the bus. When the enable signal BEN is set to the low level, the corresponding microprocessor MPU1 is set to the system bus SBUS, that is, another microprocessor M.
It will be selectively separated from the PU2 to MPU8. At this time, as described above, the power supply voltage supply wiring SLVC of the microprocessor MPU1 is selectively brought into a non-operating state by cutting off the corresponding power supply voltage supply wiring SLVC of the uppermost layer, and the large-scale integrated circuit device LSI. Is shipped as a partial product having a low processing capability, including the microprocessor MPU1 in the non-operating state. As a result, the substantial product yield of the large-scale integrated circuit device LSI can be increased and the cost thereof can be reduced.

The operation and effect obtained from the above embodiments are as follows. That is, (1) Corresponding to each module in a large-scale integrated circuit device or the like in which a plurality of modules such as a microprocessor that are coupled to a common bus and can operate independently logically are mounted on the same chip. A bus enable circuit for selectively setting its output signal to a valid level when the module can operate normally, and a bus interface circuit for selectively logically connecting the corresponding module and bus according to the output signal of the bus enable circuit. With the provision of, and operating power is supplied to each module through the power supply wiring composed of the uppermost metal wiring layer, and the power supply wiring is selectively cut by a focused ion beam or the like. Selectively disconnects an internally unavoidable faulty module from the bus, and thus from other modules It is possible to obtain the effect that it can be in a non-operating state. (2) According to the above item (1), even if a plurality of modules mounted on a large-scale integrated circuit device or the like includes a module having an unavoidable fault, the large-scale integrated circuit device or the like can be shipped as a partial product. The effect is obtained. (3) According to the above items (1) and (2), it is possible to obtain an effect that the product yield of a large scale integrated circuit device or the like can be increased and the cost thereof can be reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the number of modules, that is, microprocessors, mounted on the large-scale integrated circuit device LSI can be set arbitrarily. When the power is turned on, the bus controller B
The operation state of the microprocessors MPU1 to MPU8 can be identified by the power-on reset circuit PORS of the USC, for example, based on the logic level of the bus enable signal BEN of each microprocessor.
The large-scale integrated circuit device LSI can include a storage device, an input / output control device, and the like therein, and the system configuration, the polarity and absolute value of the power supply voltage, and the like can adopt various embodiments.

In FIG. 2, the microprocessor MPU
1 to MPU 8 can include a read-only memory and some peripheral devices, and it is not essential to include the special function unit SFU. Also,
The bus enable circuit BE is a bus interface circuit B.
It may be included in I, and the block configuration of the microprocessors MPU1 to MPU8 is not restricted by this embodiment. In FIG. 3, the bus enable signal BEN can be set to a valid level at a low level provided that the logical conditions of the bus interface circuit BI are matched. The fuse F1 may be replaced with, for example, an uppermost aluminum wiring layer that is selectively cut, and the bus enable circuit BE and the bus interface circuit BI may have various specific configurations. In FIG. 4, the uses of the first to third aluminum wiring layers AL1 to AL3 are not restricted by this embodiment. In addition, the large-scale integrated circuit device LSI has two
It is possible to provide a metal wiring layer of no more than four layers or four or more layers, and the cutting method thereof is arbitrary.

In the above description, the case where the invention made by the present inventor is mainly applied to a large-scale integrated circuit device having a plurality of microprocessors, which is a field of application of the background, has been described, but the invention is not limited thereto. However, the present invention can be widely applied to a semiconductor device including a plurality of modules that can operate at least logically independently and a system including such a semiconductor device.

[0029]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a large-scale integrated circuit device in which a plurality of modules such as a microprocessor, which are coupled to a common bus and can operate independently logically, are mounted on the same chip, each module has a corresponding module. And a bus interface circuit for selectively logically coupling the corresponding module and the bus according to the output signal of the bus enable circuit. , The operating power is supplied to each module through the power supply wiring consisting of the uppermost metal wiring layer, and this power supply wiring cannot be avoided inside by selectively disconnecting it with a focused ion beam or the like. Disconnect the faulty module from the bus and put it in a non-operational state. In addition, a large-scale integrated circuit device including such a non-operating module is shipped as a partial product having relatively low processing capability. As a result, even if a plurality of modules mounted on a large-scale integrated circuit device include a module having an unavoidable fault, it can be separated from the bus, that is, other modules, and shipped as a partial product. The product yield of circuit devices and the like can be improved, and the cost thereof can be reduced.

[Brief description of drawings]

FIG. 1 is a system configuration diagram showing an embodiment of a large scale integrated circuit device to which the present invention is applied.

2 is a block diagram showing an embodiment of a microprocessor included in the large-scale integrated circuit device of FIG.

3 is a circuit diagram showing an embodiment of a bus enable circuit and a bus interface circuit included in the microprocessor of FIG.

4 is a partial cross-sectional structural view showing an example of a power supply wiring of the large-scale integrated circuit device of FIG.

[Explanation of symbols]

LSI: Large-scale integrated circuit device, MPU1 to MPU8
... Microprocessor, BI ... Bus interface circuit, SBUS ... System bus, BUSC ...
-Bus controller, PORS ... power-on reset circuit, EBUS ... external bus, VCC ... power supply voltage, VSS ... ground potential, SLVC ... power supply voltage supply wiring, SLVS ... ground potential supply wiring. CPU ...
・ Central processing unit, IBUS ... Internal bus, SFU ...
Special function unit, RAM ... Random access memory, BE ... Bus enable circuit, CLK ... Clock signal. F1 ... Fuse,
N1 ... N-channel MOSFET, V1 to V3 ...
・ Inverter, AG1 ... AND gate,
BR ... AND type bus receiver, BD ... Bus driver, BA1 to BAi, BB1 to BBj, BC1 to BC
k ... Each bit of the system bus, IBA1 to IBA
i, IBB1 to IBBj ... Bus input signal, OBA1
~ OBAI, OBC1 ~ OBCk ... Bus output signal,
BEN ... Bus enable signal, OC ... Output control signal, OE ... Output enable signal, OB ... Inverted output enable signal. SUB: Semiconductor substrate, AL1
... first layer aluminum wiring layer, AL2 ... second layer aluminum wiring layer, AL3 ... third layer aluminum wiring layer, SLID ... inter-element signal wiring, FIB ...
Focused ion beam.

Claims (5)

[Claims] 1. A plurality of modules each of which operates logically independently of each other and is selectively disconnected from the other to be inoperative when an unavoidable failure occurs therein. Semiconductor device. 2. The semiconductor device according to claim 1, wherein the semiconductor device is shipped as a partial product while including a module in a non-operating state. 3. The semiconductor device includes a plurality of metal wiring layers, each of the modules being supplied with operating power through a power supply wiring formed of an uppermost metal wiring layer, 3. The semiconductor device according to claim 1, wherein the module having an unavoidable failure therein is selectively made inactive by disconnecting the power supply wiring. 4. The plurality of modules are coupled to each other via a bus, and each of the modules selectively outputs its output signal to a valid level when the corresponding module can operate normally. 3. A bus enable circuit for controlling the bus enable circuit, and a bus interface circuit for selectively logically connecting a corresponding module and the bus according to an output signal of the bus enable circuit. The semiconductor device according to claim 2 or claim 3. 5. The module is a microprocessor, and the semiconductor device is configured as a digital processing device having different processing capabilities selectively according to the number of microprocessors that are coupled to the bus and can operate normally. 5. The semiconductor device according to claim 4, further comprising a bus controller that operates.