JPH08148657A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [Structure] The insulating layer provided on the outermost surface of the semiconductor substrate 30.
An opening 41 is formed in the opening 31, and the dielectric film 24 deposited on the opening and the insulating layer 31, the first electrode 40 provided under the dielectric film, and the dielectric film 24 on the dielectric film 24. Second electrode provided
28 and on-chip capacitors CAP1 and CAP2
Dynamic RAM that is configured. [Effect] Even when a dielectric film having a large dielectric constant such as a high dielectric constant film is used for a capacitor, it is possible to provide a dynamic RAM which can maintain a good function of the dielectric film without deteriorating the performance of the device. it can.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device (for example,
The present invention relates to a dynamic RAM (Random access memory) and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor integrated circuit device, for example, a dynamic RAM, a memory cell M-cel having a structure as shown in FIG. 20 is known.

That is, a trench-shaped groove 3 having a predetermined depth is provided in the P-type well 2, and the groove 3 is filled with an N ⁺ -type polysilicon layer (field plate) 8 via an insulating film 4. There is. Although a P ⁻ type silicon substrate exists below the well 2, it is omitted in the drawing.

Then, the N ⁺ -type diffusion region 5 formed by diffusion over the entire surface outside the groove 3 (the side in contact with the well 2) is used as an electrode (storage node), and the polysilicon layer 8 is used as a counter electrode and an insulating film 4. Cap with a dielectric film
Is configured.

Further, an N ⁺ type source region 6 and an N ⁺ type drain region 7 are formed by diffusion in a predetermined pattern on the surface inside the P type well 2 on the side of the groove 3 (on the left side in the drawing). A gate electrode 9 as a word line (WL) is provided between these via a gate oxide film 14, and a lateral N-channel MOS transistor (transfer gate) Tr is provided.
Is configured. In this transistor, the above-mentioned capacitor Cap is connected to the source region 6.

In the reference numerals shown in FIG. 20, 10 is a field oxide film, 11 is an outermost SiO ₂ layer, 12 is a contact hole, and 13 is a bit line (BL).

On the other hand, the memory cell M-ce as shown in FIG.
1 is known (however, common parts are assigned to the parts corresponding to those shown in FIG. 20).

In this memory cell, the capacitor Cap is formed in a stack type, and N ^{+ of the} transfer gate Tr is formed ^.
Fin type stack cell capacitor Ca in the type source region 6
The polysilicon layer 5 of the p lower electrode is connected, the dielectric film 4 is deposited on this polysilicon layer, and the polysilicon layer 8 (field plate) is further provided.

In FIG. 21, reference numeral 15 is an insulating film for sidewalls, 16 is an insulating layer for passivation, 17 is an intermediate insulating layer, and 18 is a contact hole.

In both the memory cells shown in FIGS. 20 and 21, the silicon oxide film (having a dielectric constant of 4.0) or the silicon nitride film has been used as the dielectric film 4 of the capacitor. However, in the near future, various materials, structures, manufacturing methods and the like are being researched and developed in order to use a high dielectric constant film having a dielectric constant of several hundreds for the purpose of increasing the capacity.

Such a high dielectric constant film, for example, SrTiO 3
It was found that the following defects occur in the conventional capacitor when the _three films are used as the dielectric film.

The capacitor Cap shown in FIGS. 20 and 21 is
After forming the dielectric film 4, a polysilicon layer 8 is formed on the dielectric film 4.
Since the insulating layers 17 and 11 are deposited, heating is always required when these are deposited, which adversely affects the memory function of the memory cell itself and the physical properties of the dielectric film. It may cause deterioration.

That is, when the polysilicon layer 8 is formed by CVD (Chemical Vapor Deposition), heating at about 800 ° C. is required, and when the insulating layers 17 and 11 are formed, for example, insulation is performed. Layer 11 is made of boron- and phosphorus-doped silicate glass (BP
Since the reflow temperature at the time of forming with SG) is about 850 ° C., the following problems (1) and (2) mainly occur.

(1) Although a localized level due to Sr or Ti exists in a high dielectric constant film, for example, a SrTiO ₃ film,
This localized level causes generation of electrons and the like and recombination center: GR
There is a possibility that the memory data will be erased by becoming a (Generation-Recombination) center, and the electric charge at the time of memory is trapped and erased by this GR center. Such a phenomenon of the GR center is likely to occur due to the above heating.

(2) In the high dielectric constant film, oxygen atoms as a component thereof are liberated and eliminated by the above-mentioned excessive heating, or Sr, Ba and the like (further, Pt and the like of the second electrode) are constituted. Since the metal atoms easily diffuse, the physical properties (particularly the dielectric constant) of the metal atoms fluctuate, and the transistor performance of the memory cell is adversely affected.

[0016]

SUMMARY OF THE INVENTION It is an object of the present invention to prevent the performance of a semiconductor device from being deteriorated even when a dielectric film having a large dielectric constant such as the above-mentioned high dielectric constant film is used for a capacitor. It is an object of the present invention to provide a semiconductor device in which the function of a film can be favorably maintained and a manufacturing method thereof.

[0017]

That is, according to the present invention, an opening is formed in an insulating layer provided on the outermost surface of a semiconductor substrate, and a dielectric layer deposited on the insulating layer through the opening. And a first electrode provided under the dielectric layer and a second electrode provided on the dielectric layer, a semiconductor device having a capacitive element.

According to the semiconductor device of the present invention, since the capacitive element composed of the first electrode-dielectric layer-second electrode is formed via the insulating layer provided on the outermost surface of the semiconductor substrate,
Since the dielectric layer of the capacitive element can be formed at the final stage of the manufacturing process of the semiconductor device, it can be easily and easily formed without being affected by heating when forming the insulating layer and the like. Since such a capacitive element is formed on the outermost surface of the semiconductor substrate, the on-chip capacitor (On Chip Capacitor)
Capacitor).

Therefore, even if the above-mentioned high dielectric constant film is used as the dielectric layer, it is not subjected to excessive heating,
The GR center is not generated in the film (or the generation thereof is significantly reduced), the variation of the dielectric constant due to the composition change is not generated (or the variation is drastically reduced), and Sr or the like is not generated. Since diffusion of constituent metal atoms is also unlikely to occur, for example, memory performance as a semiconductor device can be favorably maintained.

In the semiconductor device of the present invention, specifically, a semiconductor element and a capacitance element connected to the semiconductor element are provided on a semiconductor substrate, and the capacitance element is (a).
An opening formed in an insulating layer provided on the outermost surface of the semiconductor substrate and a dielectric layer deposited on the insulating layer;
(B) Under this dielectric layer, it is composed of a first electrode provided so as to be connected to the semiconductor element, and (c) a second electrode provided on the dielectric layer. .

In this case, the semiconductor element is a semiconductor memory element composed of an insulated gate field effect transistor, and one diffusion region of the semiconductor memory element is a bit provided under the outermost insulating layer on the semiconductor substrate. The diffusion region may be connected to the line and the other diffusion region may be connected to the first electrode of the capacitive element, and the first electrode may be formed in the same step as the bit line.

With such a structure, a sufficient distance can be secured between the capacitive element (capacitor) and the transistor in the semiconductor memory element, so that even if Sr, Ba, Pt, etc., which are the capacitor constituents, are diffused, this is the transistor. Never reach the diffusion area (or decrease sharply),
It does not adversely affect the memory function of the memory element.

In the semiconductor device of the present invention, the first wiring and the second wiring are provided under the outermost insulating layer on the semiconductor substrate, and at least one of these wirings is the first of the capacitive element. A capacitive element is formed by also serving as an electrode, and a dielectric layer and a second electrode are provided on the first electrode, and the first wiring and the second wiring are formed via the second electrode. The capacitive element may be connected between and.

In this case, the first wiring and the second wiring are power supply lines (for example, the first wiring is the V _CC line,
The second wiring may be a V _SS (ground) line). Since the capacitive element having the above structure is built in and connected between these wirings, the power supply is stabilized, and the inductance of the wiring is extremely small compared to the case where such capacitive element is externally attached by another wiring. Therefore, the cutting characteristic of high frequency noise can be improved.

According to the semiconductor device of the present invention, the capacitance element is formed via the outermost insulating layer on the semiconductor substrate, and the first electrode of the capacitance element serves as the terminal electrode of the semiconductor device. It is desirable to be formed in the same process as the bonding pad.

In the semiconductor device of the present invention, the step of forming the first electrode of the capacitor on the semiconductor substrate, and the first step
Forming an outermost surface insulating layer on the semiconductor substrate on the electrode, forming an opening in the insulating layer on the first electrode, and forming the capacitor on the opening and the insulating layer. It is desirable to manufacture by a manufacturing method including a step of forming a dielectric layer of an element and a step of forming a second electrode of the capacitive element on the dielectric layer.

According to this manufacturing method, the above capacitive element can be manufactured with good reproducibility without excessive heating at the final stage of the manufacturing process of the semiconductor device.

In this case, the first electrode of the capacitive element is preferably formed on the intermediate insulating layer on the semiconductor substrate. Bonding pads, bit lines, and the like can also be formed on the intermediate insulating layer. An outermost insulating layer is formed on the intermediate insulating layer, an opening is formed on the first electrode in the insulating layer, and a dielectric layer is formed on the opening and the outermost insulating layer. Furthermore, a second electrode can be formed to form a capacitor. This second electrode can be formed by vacuum evaporation or the like, but the heat received by the dielectric film at that time does not affect its physical properties (even if it receives heat,
No problem if it is below ℃).

Thus, after the bonding pad is formed, 2
Since the capacitor can be produced only by adding the steps (formation of the dielectric layer and formation of the second electrode), the production thereof is easy and simple.

[0030]

Embodiments of the present invention will be described below.

1 to 16 show the dynamic RA of the present invention.
9 shows an embodiment applied to M.

First, the structure of the main part of the dynamic RAM according to the present embodiment will be described with reference to FIGS.

On one main surface of the P ^-- type silicon substrate 30, a memory cell portion M-CEL partitioned by the field oxide film 10,
And each element region of the inverter circuit unit INV which is a part of the peripheral circuit unit including the input / output unit IN. In the drawings, only a part of the semiconductor element forming each of these parts is shown. FIG. 1 shows a section without the decoder circuit portion DEC appearing in FIG. 4 and FIG.

In the memory cell section M-CEL, two transfer gates TR1 and T each composed of a MOS transistor are provided.
A memory cell including R2 and on-chip type capacitors CAP1 and CAP2 connected to them is provided.

In the transfer gates TR1 and TR2, an N ⁺ type source region 26 and an N ⁺ type drain region 27 common to each transistor are formed in a P type well 22 provided on one main surface of a P ⁻ type silicon substrate 30. Are formed by impurity diffusion.

A wiring 40 such as TiN is provided in each source region 26 through a contact hole 38 provided in an intermediate insulating layer 37 such as boron and phosphorus-doped silicate glass (BPSG).
A dielectric film 24 such as SrTiO ₃ having a thickness of about 2000 Å is formed on the wiring by depositing a thickness of about 2000 Å and opening 41 provided in the outermost insulating layer 31 such as SiO ₂ formed on the wiring. It is formed to a thickness, and a conductor layer such as Pt is further formed on this dielectric film.
28 is formed with a thickness of about 1000Å.

Therefore, the wiring 40 connected to the source region 26
As a first electrode (storage node), the conductor layer 28 as a second electrode (plate electrode), and a dielectric film between these two electrodes.
On-chip type cell capacitor C having a structure provided with 24
AP1 and CAP2 are formed on the outermost surface side of the semiconductor substrate 30.

A polysilicon word line 29 (WL, WL ') is provided between the source region 26 and the drain region 27 via a gate oxide film 34, and the drain region 27 is made of SiO _2. The bit line 33 (BL) is connected through the contact hole 32 provided in the insulating layer 37. A side wall insulating film 35 is formed on the side of the word line 29.

On the other hand, in the inverter circuit section INV which is a part of the peripheral circuit section of this dynamic RAM, N ⁺ type diffusion regions 46 and 47 are formed in the P type well 22, and the gate oxidation is performed between these two regions. A gate electrode 44 of polysilicon is provided via the film 34, and for example, a MOS transistor T1 for an inverter is formed.

In the diffusion region 46 of this MOS transistor, TiN is formed through the contact hole 48 of the intermediate insulating layer 37.
A conductive layer 43 such as the above is deposited and guided onto the intermediate insulating layer 37, and its end portion is exposed in a through hole 59 provided in the insulating layer 28 to form a bonding pad PAD. In FIG. 1, a power supply unit pad PAD, which is an example thereof, is shown.

Although various semiconductor elements are provided between the input / output section IN and the memory cell section M-CEL, the inverter circuit section INV is shown in FIG.
In this inverter circuit unit INV, P is provided in the N-type well 50.
^{The +} type diffusion regions 51 and 52 are formed, and a polysilicon gate electrode 53 is provided between these regions via a gate oxide film 34 to form a MOS transistor T2.

The diffusion region 51 of this MOS transistor T2
Is connected to the diffusion region 47 of the MOS transistor T1 by a wiring 56 such as TiN deposited in the contact holes 54 and 55 of the intermediate insulating layer 37 to form an inverter circuit unit INV. In addition, the diffusion region 52 of the transistor T2
Is T deposited on the contact hole 57 of the intermediate insulating layer 37.
It may be connected to a power supply by a wiring 58 such as iN.
Memory cell unit M-CEL and peripheral circuit unit (IN and IN
V) is connected by conductor layers 33, 40, 43, 56, 58 and the like such as TiN.

The bit line 33 (BL) and the wirings 40, 43, 56 and 58 may be formed of the same material such as TiN in the same process, which will be described in detail in the manufacturing process described later. explain.

FIG. 3 is an equivalent circuit diagram of a memory cell of the memory cell section M-CEL, and FIG. 4 is a dynamic RAM.
3 is an equivalent circuit diagram of the main part of FIG.

In FIG. 4, input pads PAD-BL and PAD-WL for bit lines and word lines are provided.
Are decoder units DEC-BL and DEC-WL, respectively.
Through each bit line B of the memory cell unit M-CEL
It is connected to L, BL 'and each word line WL, WL'. In this case, the signal from each input pad is output as "1" and its complement by the inverter Inv, and these outputs are input to each NAND gate of the decoder section.
This output is input to the memory cell.

Next, the dynamic RAM according to this embodiment
An example of the manufacturing process will be described with reference to FIGS.

First, as shown in FIG. 5, a photoresist mask (not shown) is formed on one main surface of the P ^-- type silicon substrate 30.
N-type impurities (for example, phosphorus) and P-type impurities (for example, boron) are sequentially ion-implanted by using, and an N-type well 50 and a P-type well 22 are formed by annealing.

Then, after growing a thin thermal oxide film (not shown) on the surface of each well, a field oxide film 10 for element region isolation of about 5000 Å is formed by the LOCOS method of masking silicon nitride (not shown). Selectively grow to the thickness of.

Then, after removing the silicon nitride mask and the thermal oxide film, the surface is washed and, as shown in FIG. 6, the gate oxide film 34 is grown to a thickness of about 150Å by thermal oxidation.

Next, as shown in FIG. 7, polysilicon is deposited on the entire surface by a CVD method to a thickness of about 2500 Å and patterned to form a polysilicon gate electrode 29 (WL, W).
L '), 44 and 53 are respectively formed, a silicon oxide film is further deposited on the entire surface by a CVD method, and the entire surface is etched to form a side wall 35 of silicon oxide on a side portion of each gate electrode.
Are selectively formed.

Then, as shown in FIG. 8, an N-type impurity (for example, phosphorus) 60 and a P-type impurity (for example, boron) 61 are sequentially ion-implanted using a photoresist mask (not shown) to form a gate electrode 29, Impurities are selectively implanted into the P-type well 22 and the N-type well 50 by the 44 and 53 and the sidewall 35, and the N ⁺ -type diffusion regions 26 and 27 are annealed by annealing.
46 and 47 and P ⁺ type diffusion regions 51 and 52 are formed in a self-aligned manner.

Next, as shown in FIG. 9, a BPSG layer 37 as an intermediate insulating layer is deposited on the entire surface by a CVD method to a thickness of about 8000Å and reflowed at a temperature of about 850 ° C. to flatten the surface, and thereafter, The BPSG layer 37 is patterned by photolithography, and contact holes 32, 38, 48, 54, 55 and 57 are formed at predetermined positions in a size of 1 μm × 1 μm.

Next, as shown in FIG. 10, TiN is deposited on the entire surface to a thickness of about 2000 Å by a sputtering method, and this is patterned by photolithography to form each wiring 33.
(BL), 40, 43, 56 and 58 are formed respectively.

Then, as shown in FIG. 11, a silicon oxide film (SiO ₂ layer) 31 as an outermost insulating layer is deposited by plasma CVD to a thickness of about 4000 Å, and this is patterned by photolithography. The openings 41 and 59 are formed, respectively.

Then, as shown in FIG. 12, openings O are formed in the regions of the memory cell portion M-CEL and the inverter circuit portion INV.
A metal shadow mask M having a PN is arranged so as to cover the input / output portion IN, and SrTiO ₃ which is a high dielectric constant material is arranged.
24 is a sputtering method (however, the temperature of the semiconductor substrate 30 is 5
The temperature should be around 00 ° C. ) Is deposited to a thickness of about 1000Å and the high dielectric constant film 24 made of SrTiO ₃ is formed in contact with the wiring 40 as the first electrode of the capacitor.

Then, as shown in FIG. 13, using the same shadow mask, Pt (platinum) 28 was heated to a thickness of about 1000Å by a vacuum evaporation method by electron beam heating (however, the temperature of the semiconductor substrate 30 was room temperature). The Pt layer 28 serving as the second electrode of the capacitor is formed by depositing the dielectric constant film 24 in substantially the same pattern. The shadow mask used here may be different from that shown in FIG.

In this way, the dynamic RAM having the on-chip capacitors CAP1 and CAP2 shown in FIGS. 1 and 2 in the memory cell can be manufactured.
According to this dynamic RAM, the first electrode 40 connected to the MOS transistors TR1 and TR2 through the insulating layer 31 provided on the outermost surface of the semiconductor substrate 30-the dielectric layer 24.
-Capacitors CAP1, CAP2 consisting of the second electrode 28
The following advantages (A) to (D) are obtained.

(A) Since the dielectric layer 24 of the capacitors CAP1 and CAP2 can be formed at the final stage of the manufacturing process of the dynamic RAM, it is easy and simple without being affected by heating due to reflow when forming the insulating layer. Can be formed.

(B) Therefore, SrTiO 3 is used as the dielectric layer.
_{3 Even if the} high dielectric constant film 24 (dielectric constant is 200) is not subjected to excessive heating, it does not generate GR centers in the film (or significantly reduces the occurrence thereof). In addition, since the variation of the dielectric constant due to the composition change does not occur (or the variation is drastically reduced), the charge storage function (memory function) becomes good. The high dielectric constant film 24 significantly increases the capacitance of the capacitor, and even if the capacitor area is reduced by that amount, a sufficient memory capacitance can be obtained, and further higher integration and improved memory performance can be expected.

(C) In addition, Sr (B
In the case of the aTiO ₃ film, diffusion of Ba) and Pt in the electrode 28 is unlikely to occur, so that the performance of the active regions of the transistors TR1 and TR2 sensitive to such impurities can be maintained. That is,
Since the capacitors CAP1 and CAP2 are provided on the outermost surface, a sufficient distance can be secured between these capacitors and the transistors, and Sr, Ba, P which are the capacitor constituent materials.
Even if diffusion such as t occurs, it does not reach (or drastically decreases) the diffusion region of the transistor, and does not adversely affect the memory function.

(D) In addition, capacitors CAP1 and CAP
In order to form No. 2, it is only necessary to add two steps (formation of the dielectric layer 24 and formation of the second electrode 28) after the formation of the bonding pad PAD, so that the production of the capacitor is easy and simple.

Next, the dynamic RAM according to this embodiment
Was incorporated into a prototype chip shown in FIGS. 14 and 15 and subjected to a test.

FIG. 14 shows a layout (for example, a length of about 100) between the memory cell section M-CEL-decoder circuit section DEC-inverter circuit section INV-bonding pad PAD.
00 μm, width 1600 μm) is schematically shown.

Here, the memory cell section M-CEL may be composed of a cell array of 4096 bits in 128 rows and 32 columns, for example. The area surrounded by the imaginary line is the area of the capacitor CAP described above (specifically, the area where the electrode 28 and the dielectric film 24 are formed or the area of the mask used when forming these).

In FIG. 15, two kinds of dynamic RAMs of the layout shown in FIG. 14, DRAM1 and DRAM2, are arranged on a common substrate, and test elements (for example,
A chip TC provided with a MOS transistor, a capacitor, a 1-bit dynamic RAM cell, or the like) EL as a single element is shown.

Each of the DRAM1 and DRAM2 has bonding pads PAD-BL1, PAD-WL1 and P, respectively.
AD-BL2, PAD-WL2, decoder unit DEC-B
L1, DEC-WL1, DEC-BL2, DEC-WL
2, inverter circuit section INV, memory cell section M-CEL
1 and M-CEL2.

These memory cells differ in the size of the capacitors, for example, in the M-CEL1, 6 × 6 μm,
For M-CEL2, it may be 2 × 2 μm. Further, the test element EL also has each bonding pad PAD ′ and an element portion T ′ such as a transistor. The virtual line OPN indicates the opening of the mask M used when forming the above-mentioned capacitor CAP, and SrTi is passed through this opening.
O ₃ and Pt can be selectively attached.

FIG. 16 shows a test chip T shown in FIG.
It shows a state in which a large number of four Cs are cut out from a semiconductor wafer of, for example, 6 inches, and a metal shadow mask M is aligned with one unit.

In the chip shown in FIGS. 14 and 15, after the operation of applying the probe electrode to the upper electrode 28 (see FIG. 1) of the capacitor of the memory cell and storing the charge in the storage node via the transistor TR. When the leak current was measured, it was 1 × 10 ⁻⁸ A / cm ^2, which was extremely small, and it was confirmed that the memory performance of the device of this example was good. In addition, it was possible to form a dielectric film having a high relative dielectric constant of 20 times that of a silicon oxide film.

17 to 19 show an embodiment in which the present invention is applied to a power supply stabilizing circuit.

According to this embodiment, a semiconductor integrated circuit IC
Power supply pads PAD-V _CC (for V _CC power supply) and PAD-GND on the insulating layer 75 such as SiO ₂
Between the power lines 70 and 71 (for grounding), SiO ₂
A capacitor CAP including a power supply line 70-SrTiO ₃ high dielectric constant film 74-Pt layer 78 is connected via through holes 73 and 76 provided in the insulating layer 72. The capacitor CAP is for stabilizing the power supply.

Thus, the pads PAD-V _CC and PAD
-High capacity capacitor CAP between each wiring 70-71 of GND
Is connected and is built in the chip (Fig. 19 (A) shows the outline).
The inductance of the wiring becomes extremely smaller than that in the case where the wiring is externally attached by another wiring 80 as shown in FIG. This allows high frequency noise 81 to easily escape to the ground level,
The cutting characteristics can be improved, the operating frequency can be lowered, and the power supply and the operation can be stabilized.

The above-mentioned capacitor CAP can be manufactured by the same sputtering method, vapor deposition method, or photolithography as the above-mentioned process, but the high dielectric constant film 74 is used.
The conductor layer 78 and the conductor layer 78 must be formed using different shadow masks. Alternatively, they may be formed by ordinary photolithography.

Although the embodiments of the present invention have been described above, the above-mentioned embodiments can be further modified based on the technical idea of the present invention.

For example, the above-mentioned capacitors CAP1 and C
The cross-sectional structure of AP2 and CAP, the plane pattern (including the grounding structure with the lower layer), the constituent material thereof, and the like may be variously changed. As the constituent material of the dielectric film, the above-mentioned SrTiO _{3 is used.}
Besides, BaTiO ₃ , (Ba, Sr) TiO ₃ , T
Other high dielectric constant films such as a ₂ O ₅ can also be used, and
The electrode or wiring material is also a conductor film material other than TiN and Pt,
For example, it may be RuO ₂ , Al or the like.

If a ferroelectric film such as Pb (Zr, Ti) O ₃ is used as the dielectric film instead of the high dielectric constant film, FRAM (Ferroelectric RA) is used.
A non-volatile RAM called M) can be made.

Further, the above-mentioned insulating layers may be laminated in a large number, and various materials such as BPSG and SiO ₂ can be used as the material.

Regarding the film forming method, in the above-described example, the shadow mask is used to prevent the high dielectric constant film and the upper electrode from being formed in the bonding pad region, but other patterning methods such as the lift-off method may be used. It is also possible to form a peeling layer in the bonding pad region, form a dielectric film and an upper electrode on the peeling layer, and remove only the bonding pad region together with the peeling layer. Of course, other methods may be adopted.

The present invention may be applied to a semiconductor memory such as a dynamic RAM other than the type described above, for example, a static RAM (SRAM). In addition, the conductivity type of the above-mentioned semiconductor region can be changed, or the present invention can be applied to other parts of the semiconductor memory or other devices. The contents shown in FIG. 17 and FIG. 18 can be applied not only to power supply stabilization but also to a place where a capacitor is required in a semiconductor circuit inside a chip.

[0080]

As described above, according to the present invention, since the capacitive element including the first electrode, the dielectric layer and the second electrode is formed via the insulating layer provided on the outermost surface of the semiconductor substrate,
Since the dielectric layer of the capacitive element can be formed at the final stage of the manufacturing process of the semiconductor device, it can be easily and easily formed without being affected by heating when forming the insulating layer and the like.

Therefore, even if a high dielectric constant film is used as the dielectric layer, it is not subjected to excessive heating, so that no GR center is generated in the film (or the occurrence thereof is significantly increased). In addition, since the dielectric constant does not fluctuate (or drastically decreases) due to the composition change, and the diffusion of constituent metal atoms such as Sr does not easily occur, for example, good memory performance as a semiconductor device is maintained. can do.

[Brief description of drawings]

FIG. 1 is a sectional view of a main part of a dynamic RAM having an on-chip capacitor according to a first embodiment of the present invention.

FIG. 2 is an enlarged cross-sectional view of a part of a memory cell in the dynamic RAM.

FIG. 3 is an equivalent circuit diagram of a part of the same memory cell.

FIG. 4 is an equivalent circuit diagram of a main part of the dynamic RAM.

FIG. 5 is a cross-sectional view of a step of the method for manufacturing the same dynamic RAM.

FIG. 6 is a cross-sectional view of another process step in the method for manufacturing the dynamic RAM.

FIG. 7 is a cross-sectional view of another process step in the method for manufacturing the dynamic RAM.

FIG. 8 is a cross-sectional view of another process step in the method for manufacturing the dynamic RAM.

FIG. 9 is a cross-sectional view of another process step in the method for manufacturing the dynamic RAM.

FIG. 10 is a cross-sectional view of another step in the method for manufacturing the dynamic RAM.

FIG. 11 is a cross-sectional view of another process step in the method of manufacturing the dynamic RAM.

FIG. 12 is a cross-sectional view of another process step in the method of manufacturing the dynamic RAM.

FIG. 13 is a sectional view of still another process step in the method for manufacturing the dynamic RAM.

FIG. 14 is a layout diagram of a main part of the same dynamic RAM.

FIG. 15 is a layout diagram of a prototype chip incorporating a dynamic RAM having the same layout.

FIG. 16 is a pattern diagram showing a positional relationship of a shadow mask with respect to four prototype chips cut out from a semiconductor wafer.

FIG. 17 is a schematic plan view of a main part of a semiconductor IC chip according to another embodiment of the present invention.

18 is a sectional view taken along line XVIII-XVIII in FIG.

FIG. 19 is a schematic diagram showing a power supply stabilizing circuit of the semiconductor IC chip.

FIG. 20 is a cross-sectional view of a part of a memory cell in a conventional dynamic RAM.

FIG. 21 is a cross-sectional view of a part of a memory cell in another conventional dynamic RAM.

[Explanation of symbols]

 22, 50 ... Well 24 ... Dielectric film 26, 27, 46, 47, 51, 52 ... Diffusion region 28 ... Conductor layer (second electrode: upper electrode) 29 (WL, WL ') ・ ・ ・ Word line 30 ・ ・ ・ Semiconductor substrate 31 ・ ・ ・ Outermost surface insulating layer 32, 38, 48, 54, 55, 57 ・ ・ ・ Contact hole 33 (BL) ・ ・ ・ Bit line 37 ・ ・-Intermediate insulating layer 40 ... Wiring (first electrode: lower electrode) 41, 59 ... Openings 43, 56, 57 ... Wiring M-CEL ... Memory cell DEC ... Decoder circuit section IN ... Input / output section INV ... Inverter circuit section CAP1, CAP2, CAP ... Capacitors TR1, TR2 ... Transfer gate PAD ... Bonding pad

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 21/822 7735-4M H01L 27/10 621 B (72) Inventor Katsuhiro Aoki Miura, Inashiki-gun, Ibaraki Murakihara 2355 Japan Incorporated by Texas Instruments Incorporated (72) Inventor Ken Numata 2355 Mihara, Miura, Inashiki-gun, Ibaraki Pref. Incorporated by Texas Instruments Incorporated

Claims (8)

[Claims] 1. An opening is formed in an insulating layer provided on the outermost surface of a semiconductor substrate, a dielectric layer deposited on the insulating layer through the opening, and a dielectric layer provided below the dielectric layer. A semiconductor device in which a capacitive element is constituted by a first electrode and a second electrode provided on the dielectric layer. 2. A semiconductor element and a capacitive element connected to the semiconductor element are provided on a semiconductor substrate, and the capacitive element is formed in (a) an insulating layer provided on the outermost surface of the semiconductor substrate. A dielectric layer deposited on the opening and the insulating layer; (b) a first electrode provided below the dielectric layer so as to be connected to the semiconductor element; The semiconductor device according to claim 1, wherein the semiconductor device is configured by a second electrode provided on the dielectric layer. 3. The semiconductor element is a semiconductor memory element composed of an insulated gate field effect transistor, and one diffusion region of the semiconductor memory element is connected to a bit line provided under an insulating layer on the outermost surface of a semiconductor substrate. The semiconductor device according to claim 2, wherein the other diffusion region is connected to the first electrode of the capacitive element, and the first electrode is formed in the same step as the bit line. 4. A first substrate under the outermost insulating layer on the semiconductor substrate.
Wiring and a second wiring are provided, at least one of these wirings is also used as the first electrode of the capacitive element, and the dielectric layer and the second electrode are provided on the first electrode. The semiconductor device according to claim 1, wherein a capacitive element is formed, and the capacitive element is connected between the first wiring and the second wiring via the second electrode. 5. The semiconductor device according to claim 4, wherein each of the first wiring and the second wiring is a power supply line. 6. The semiconductor device according to claim 1, wherein the first electrode of the capacitive element is formed in the same step as the bonding pad. 7. A step of forming a first electrode of a capacitive element on a semiconductor substrate, a step of forming an outermost insulating layer on the semiconductor substrate on the first electrode, and the first electrode. A step of forming an opening in the insulating layer above, a step of forming a dielectric layer of the capacitive element on the opening and the insulating layer, and a second electrode of the capacitive element on the dielectric layer The method for manufacturing a semiconductor device according to claim 1, further comprising: 8. The manufacturing method according to claim 7, wherein the first electrode of the capacitive element is formed on the intermediate insulating layer on the semiconductor substrate.