JPH08148998A - PLL circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] Two VCOs are provided and switched so that a discontinuous area of the clock frequency due to the combination of the VCO frequency variable range and the operation of the clock generator does not occur. The phase comparator 2 compares the phases of the horizontal synchronizing signal from the terminal 1 and the comparison signal from the frequency divider 8, outputs a phase difference voltage signal, and an unnecessary frequency component is filtered by the LPF 3,
It is applied to O4a and VCO4b to oscillate a clock. CPU10
Is switched to VCO4a or VCO4b by the selector 5 and input to the clock generator 6, converted to a required frequency based on the data from the CPU 10 and output from the terminal 7. The CPU 10 selects a parameter from the LUT 11 based on the data representing the lock state from the lock detector 9 based on the differential voltage signal from the phase comparator, controls the clock generator, and sets the parameter in the discontinuous area of the output frequency. If it is close, output a signal to the selector to output VCO4b
Switch to.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (phase locked loop) circuit for converting a clock from a VCO (voltage controlled oscillator) into a required frequency by a clock generator, and to a control method of a clock generator.

[0002]

2. Description of the Related Art Some PLL circuits used for digital processing of video signals are constructed as shown in FIG. This circuit applies a reference signal from the terminal 1, for example, a horizontal synchronizing signal to the phase comparator 2 and outputs the frequency divider 8
The comparison signal is compared with the phase to output a difference signal voltage corresponding to the phase difference, and the difference signal voltage is input to the LPF (low pass filter) 3 to filter unnecessary frequency components and applied to the VCO 4a. The oscillation frequency is controlled, the output of the VCO 4a is input to the clock generator 6, the required frequency is converted based on the signal from the CPU 21 to generate the system clock, which is output from the terminal 7, and at the same time this clock is divided by a frequency divider. 8
To the frequency of the reference signal from the terminal 1 and is fed back to the phase comparator 2 to form a PLL.

The CPU 21 receives data indicating the lock state from the lock detector 9 (for example, lock state: "0,0",
The clock generator 6 is controlled so that the lock release due to the phase lead: "1,1" and the lock release due to the phase delay: "0,1") are always locked. That is, C
The PU 21 reads the parameter table shown in FIG. 2 stored in the lookup table 11 and locks the lock detection unit 9
The parameter P corresponding to the signal is selected and the data is sent to the clock generator 6.
Is 0 to 130, the parameter Q is 0 to 129, P and Q are combined for each table value, and the clock from the VCO 4a is 2
The output frequency of the clock generator 6 is changed in steps of approximately 0.1% by multiplying it, multiplying it by the parameter P, and dividing by the parameter Q. This is to make the output frequency continuously change from the step of the output frequency of the clock generator 6 and the variable frequency range of the VCO 4a. As described above, the maximum value of the parameter P is 130.
, Q is 129, so table values T = 129 and T = 130
There is a part that is not in 0.1% increments such as between. On the other hand, the frequency variable range of the VCO 4a is set to, for example, ± 0.2% from the stability of the frequency, so when the center frequency of the VCO 4a is 14.3185MHz, the center frequency of T = 128: 28.412 (MHz) Upper limit frequency: 28.4688 (MHz) Center frequency of T = 129: 28.414 (MHz) Lower limit frequency: 28.3571 (MHz), and at T = 128 and T = 129, as shown in Fig. 3 (a), the variable range of frequency is discontinuous area. Does not occur, but T
Between = 129 and T = 130, the upper limit frequency of T = 129: 28.4708 (MHz), the center frequency of T = 130: 28.636 (MHz), the lower limit frequency: 28.5787 (MHz), and a discontinuous area occurs. .

[0004]

SUMMARY OF THE INVENTION In view of the above, the present invention provides two VCOs having different center frequencies and appropriately switches the VCOs so that the VCO frequency variable range and the frequency converted by the clock generator can be changed. The purpose is to eliminate the discontinuous area of the clock frequency caused by the combination with.

[0005]

In order to solve the above-mentioned problems, the present invention provides a phase comparator for comparing the phases of a reference signal from the outside and an internal comparison signal and outputting a phase difference signal,
A lock detection unit that detects the locked state of the PLL based on the phase difference signal from the phase comparator, a low-pass filter that inputs the signal from the phase comparator and filters unnecessary frequency components, and a plurality of low-pass filters are provided. Voltage control oscillation circuit that oscillates a clock with a frequency corresponding to the voltage of the signal from the bandpass filter, a selector that switches the signal from the voltage control oscillation circuit, and a clock generator that converts the clock from the selector to the required frequency and outputs it. And a frequency divider that divides a clock from a clock generator to generate a comparison signal and feeds it back to the phase comparator, and a CPU that controls the selector, the clock generator, etc., based on the signal from the lock detector. And a PLL circuit for controlling a clock generator and a selector.

[0006]

With the above construction, the PL according to the present invention
In the L circuit, the CPU selects the table value based on the signal indicating the lock state from the lock detection unit, sends the parameter of the table value to the clock generator, and controls the output frequency. When the table value of the parameter is close to the discontinuous area, a signal is sent to the selector to switch the VCO to prevent the output frequency from entering the discontinuous area.

[0007]

Embodiments of the PLL circuit according to the present invention will be described in detail below. FIG. 1 is a block diagram of essential parts of an embodiment of a PLL circuit according to the present invention. In the figure, reference numeral 1 is an input terminal for inputting a horizontal synchronizing signal or the like. Reference numeral 2 is a phase comparator which compares the phases of the horizontal synchronizing signal from the input terminal 1 and the comparison signal from the frequency divider 8 and outputs a difference voltage signal according to the phase difference. An LPF 3 filters an unnecessary frequency component of the difference voltage signal from the phase comparator 2. 4a and 4b are VCOs. For example, VCO 4a is 14.3185M when a center voltage is applied.
The Hz and VCO 4b each oscillate a clock of 12.5875 MHz. Reference numeral 5 is a selector, which receives a VCO 4a signal from the CPU 10.
Alternatively, the output is switched to VCO4a. A clock generator 6 converts the VCO 4a or the clock from the VCO 4a input through the selector 5 into a desired frequency based on the data from the CPU 10 and outputs the frequency from a terminal 7. 8
Is a frequency divider, which divides the clock from the clock generator 6 into the frequency of the horizontal synchronizing signal input from the terminal 1 to obtain a comparison signal, which is fed back to the phase comparator 2. Reference numeral 9 denotes a lock detector, which detects P based on the phase difference signal from the phase comparator 2.
The lock state of LL is detected. The CPU 10 selects a parameter corresponding to the lock state detected by the lock detector 9 from the parameter table read from the lookup table 11 and sends it to the clock generator 6.

Next, the operation of the PLL circuit according to the present invention will be described. The phase comparator 2 compares the phases of the horizontal synchronizing signal from the terminal 1 and the comparison signal from the frequency divider 8 and outputs a difference signal voltage corresponding to the phase difference. This difference signal voltage is input to the LPF 3 to filter an unnecessary frequency component to obtain a control voltage, and VC
Applied to O4a and VCO4b, VCO4a and VCO4b
Oscillates a clock having a frequency corresponding to each applied voltage. Clock from VCO4a and VCO4b
The clock is switched by the selector 5, input to the clock generator 6, converted to a required frequency based on the data from the CPU 10, and output from the terminal 7. The lookup table 11 stores a parameter table as shown in FIG. 2, the CPU 10 reads the parameter table, and the data indicating the lock state from the lock detection unit 9, for example, the lock state: “0, 0”, Select an appropriate table value based on unlocking due to phase lead: "1,1" and unlocking due to phase delay: "0,1",
The data is sent to the clock generator 6.

Thus, for example, when the clock from the VCO 4a is input to the clock generator 6 through the selector 5 and the table value T = 128 is selected by the CPU 10, the data of T = 128: 127/128 = 0.99218. Is sent to the clock generator 6, the clock from the VCO 4a is calculated based on this data, and 14.3185 MHz × 2 × 0.
Outputs 99218 ≈ 28.412MHz. Then, the CPU 10
When the data from the lock detector 9 is continuously monitored and the data indicates the phase delay of the comparison signal, the next table value T = 129 for the VCO 4a is between the next table value T = 130. Since it has a discontinuous area, a signal is sent to the selector 5 to switch from VCO 4a to VCO 4b. At the same time, the CPU 10 causes the VCO 4b
A table value T = 56 or the like for calculating a clock of 2 to be close to 28.5 MHz is selected and sent to the clock generator 6.

[0010]

As described above, P according to the present invention
According to the LL circuit, when the table value of the parameter for controlling the clock generator becomes close to the discontinuous area, the VCO is switched to the other VCO, so that the frequency of the output clock does not become discontinuous.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part of an embodiment of a PLL circuit according to the present invention.

FIG. 2 is an example of a parameter table stored in a lookup table.

FIG. 3 is a diagram for explaining generation of a discontinuous region due to a VCO frequency variable range and parameters.

FIG. 4 is a main part block diagram of an example of a conventional PLL circuit.

[Explanation of symbols]

 1 Input Terminal 2 Phase Comparator 3 LPF 4 VCO 5 Selector 6 Clock Generator 7 Output Terminal 8 Frequency Divider 9 Lock Detector 10 CPU 11 Lookup Table

Claims (5)

[Claims] 1. A phase comparator for comparing the phases of an external reference signal and an internal comparison signal and outputting a phase difference signal, and a lock state of the PLL is detected based on the phase difference signal from the phase comparator. Lock detecting section, a low-pass filter for inputting a signal from the phase comparator and filtering unnecessary frequency components, and a plurality of voltages for respectively oscillating clocks having a frequency corresponding to the voltage of the signal from the low-pass filter. Control oscillator circuit, selector for switching the signal from the voltage control oscillator circuit, clock generator for converting the clock from the selector to the required frequency and outputting it, and dividing the clock from the clock generator to make the comparison signal the phase comparison A frequency divider for returning to the clock and a CPU for controlling the selector, the clock generator and the like. A PLL circuit configured to control a clock generator and a selector based on a signal. 2. A lookup table for storing parameters for converting the output frequency of the clock generator is provided, the CPU reads the parameter table from the lookup table, and selects a parameter corresponding to a signal from the lock detector. The PLL circuit according to claim 1, configured to do so. 3. The CPU switches the selector when the frequency range converted by the clock generator by the selected parameter is not continuous with the frequency range by the parameter of the next table value.
The described PLL circuit. 4. The PLL circuit according to claim 1, wherein the plurality of voltage controlled oscillation circuits oscillate clocks of different frequencies with the same control voltage. 5. The plurality of voltage controlled oscillator circuits oscillate clocks of different frequencies with the same control voltage, and the frequency range is discontinuous by a clock generator based on the clock from one of the voltage controlled oscillator circuits. 4. The PLL circuit according to claim 1, wherein the area and the discontinuous area of the frequency range by the clock generator based on the clock from the other voltage-controlled oscillation circuit do not overlap.