JPH08149274A - Control signal generator for optical beam scanning - Google Patents

Abstract

PURPOSE: To attain high speed image scanning by generating a clock signal of a prescribed period synchronously with an optical beam detection signal so as to increase the frequency of the control block without increasing a position deviation of dots between lines. CONSTITUTION: A reference signal generating section 20 generates a sawtooth wave signal S22 based on an original oscillation clock CKO and outputs the same fixed clock CK2 as the CK0. A hold section 30 detects an instantaneous value of a signal S22 and stores it in response to an optical beam detection signal S10 from a photodetector 10 at that point of time. An original dot clock generating section 40 generates an original dot clock CK1 of the same period as the signal S22 and synchronously with the signal S10. When the instantaneous value of the hold section 30 is within a set range, the clock CK1 whose timing is coincident completely with the signal S10 is fed to a shape section 54 and when the instantaneous value is at the outside of the setting range, the clock CK2 is fed to the shaping section 54 through a changeover section 50. As a result, a dot clock SYNCK to modulate a light beam for each picture element is obtained synchronously with the deflection of the light beam as a result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control signal generating device for scanning a light beam of a line-sequential system, which is used for image formation in digital copying machines, page printers, facsimile machines and the like.

[0002]

2. Description of the Related Art Generally, in an image forming apparatus that deflects a laser beam to perform line-sequential scanning, a photodetector is arranged at a proper position in the optical path of the laser beam in order to align the heads of images on the lines. The scanning is started based on the timing when the beam passes through the photodetector. Then, during scanning, the laser beam is modulated in accordance with the dot-unit image data transferred in accordance with the pixel clock (dot clock).

In the reproduced image, if the positional deviation of dots is not more than 1/4 of the dot diameter, it is not so conspicuous, but if it exceeds 1/4, the deterioration of image quality becomes remarkable. Therefore, the output of the above-mentioned photodetector (SOS: Start o
It is necessary to suppress the delay of the dot clock with respect to f Scan) to at least ¼ cycle of the dot clock or less. That is, ideally, a perfect synchronization state in which there is no phase difference between the dot clock and the SOS is desirable.

Conventionally, the following two methods have been known as methods for generating a dot clock synchronized with SOS. One of them is n (= 4 ~
8) A method of dividing the original oscillation clock in response to the input of the SOS by using the original oscillation clock having a frequency about twice (JP-A-51-46141). The other one is to delay the dot clock by 1 / n cycle by an n-stage signal delay circuit and select the dot clock of the delay stage having the smallest phase difference from SOS in response to the input of SOS. Method (JP-A-62-269410).

[0005]

In the conventional method of dividing the frequency of the original oscillation clock, when the frequency of the dot clock is increased to speed up the image formation or increase the resolution, the original oscillation clock with an extremely high frequency is generated. Will be needed.

However, when a crystal oscillator is used to obtain an original oscillation clock with a stable frequency, the practical upper limit of the oscillation frequency is about 100 MHz, and a desired frequency division ratio is secured as the dot clock frequency increases. However, there is a problem in that it becomes impossible to make the positional deviation of dots inconspicuous.

Further, in the method of delaying the dot clock, the circuit configuration is more complicated than that of the frequency division, and in order to shorten the delay time of each stage in order to increase the frequency of the dot clock, an ECL element or the like is used. Expensive I for high speed processing
There was a problem that C had to be used. Further, since n dot clocks (high-frequency pulse signals) having a phase shift are generated, there is a problem that high-frequency noise is likely to occur.

The present invention has been made in view of such a problem, and increases the frequency of a control clock that defines the modulation period of a light beam without increasing the positional deviation of dots between lines, thereby performing image scanning. The purpose is to enable speeding up.

[0009]

According to a first aspect of the present invention, there is provided a control signal generating device comprising a photodetector for detecting a light beam for scanning an original image line-sequentially, and a ramp waveform having a constant amplitude and period. Signal generating means for outputting a signal, signal holding means for storing an instantaneous value of the ramp waveform signal at that time in response to the input of the light beam detection signal from the photodetector, the ramp waveform signal and the Clock signal generating means for generating a clock signal of a constant cycle in synchronization with the light beam detection signal by comparing the magnitude with the instantaneous value stored in the signal holding means.

A control signal generating device according to a second aspect of the present invention stores second clock signal generating means for generating a second clock signal of a constant cycle in synchronization with the ramp waveform signal, and the signal holding means. When the instantaneous value is a value within a setting range from a lower limit value greater than the minimum value of the ramp waveform signal to an upper limit value less than the maximum value, the clock signal is selected, and the instantaneous value is a value outside the setting range. And a clock switching means for selecting the second clock signal and selectively outputting the selected clock signal or the second clock signal.

The ramp waveform means a signal waveform whose instantaneous value monotonously changes (increases or decreases) between two values, and is not limited to a linearly changing triangular wave (including a sawtooth wave).

[0012]

The light beam is incident on the photodetector every scanning of one line, and the photodetector outputs the light beam detection signal.

In response to the light beam detection signal, the signal holding means stores the instantaneous value of the ramp waveform signal having a constant amplitude and cycle. That is, the instantaneous value of the ramp waveform signal is held as information indicating at which point in one cycle of the ramp waveform signal the time when the light beam enters the photodetector.

The clock signal generating means synchronizes with the light beam detection signal by comparing the momentarily changing ramp waveform signal with the stored instantaneous value, that is, by binarizing the stored instantaneous value as a threshold value. In addition, a clock signal having the same period as the ramp waveform signal is generated.

On the other hand, the second clock signal generating means generates a binary second clock signal synchronized with the ramp waveform signal. When the instantaneous value stored in the signal holding means is a value near the minimum value or the maximum value of the ramp waveform signal, the second clock signal is supplied to the clock signal generation means instead of the clock signal. Is output to. In other cases, the clock signal is output to the supply destination. That is, a signal (clock signal or second clock signal) having an appropriate duty ratio is always sent to the supply destination, thereby preventing malfunction at the supply destination.

[0016]

1 is a perspective view showing the outline of a scanning optical system 100 according to the present invention. The scanning optical system 100 is used as an exposure unit of an electrophotographic process in a state of being incorporated in, for example, a page printer.

The light source in the scanning optical system 100 is a semiconductor laser 121. The semiconductor laser 21 is controlled according to image data in pixel units sent from a data processing system (not shown) and outputs a binary-modulated light beam. The light beam is collimated by the collimating lens 122 and is deflected by the rotating polygon mirror 123.
The deflected light beam forms a spot of a predetermined size on the photosensitive drum 3 by an imaging lens 124 called an fθ lens, and performs light beam scanning in the H direction (main scanning direction).

The photosensitive drum 3 is rotating at a constant speed, and its surface is uniformly charged to a predetermined potential by a charging charger (not shown). Two-dimensional scanning is performed line-sequentially by the deflection of the light beam and the rotation of the photosensitive drum 3, and the surface charges of the photosensitive drum 3 are partially eliminated to form an electrostatic latent image. The electrostatic latent image is transferred onto the paper after development.

In such line-sequential scanning of the light beam, the light beam traveling toward the starting end position of the scanning line is reflected by, for example, the mirror 125 and guided to the photodetector 10.
The arrangement position of the photodetector 10 can be appropriately selected, and the deflected light beam can be guided to the photodetector 10 without being reflected.

The light beam detection signal (SOS) S10 output from the photodetector 26 is used as a main scanning synchronization signal for each line. That is, scanning of each line (writing of an image of one line) is started with reference to the output timing of the light beam detection signal S10.

FIG. 2 is a block diagram of the control signal generator 1 of the present invention, FIG. 3 is a waveform diagram of the output signal of each part in the control signal generator 1, and FIG. 4 is a pulse of the light beam detection signal S10 and the original dot clock CK0. FIG. 5 is a diagram showing the relationship with the width, and FIG. 5 is a time chart showing the operation of the clock switching unit 50 of FIG.

The control signal generator 1 is the photodetector 1 described above.
0, a reference signal generation unit 20, a hold unit 30, an original dot clock generation unit 40, and a clock switching unit 50, and a synchronization signal for modulating the light beam for each pixel in synchronization with the deflection of the light beam. Dot clock SY
Output NCK.

The reference signal generator 20 includes a crystal oscillator circuit 2
1. Sawtooth wave generator 22 and fixed clock generator 2
Consists of three. The crystal oscillator circuit 21 outputs the original oscillation clock CK0 having a stable frequency. Original oscillation clock CK0
Is the dot clock SYN that should be finally generated.
Same as CK. The sawtooth wave generation unit 22 generates a sawtooth wave signal S22 based on the original oscillation clock CK0. The sawtooth wave signal S22 is a periodic signal whose instantaneous value gradually increases linearly with the passage of time, reaches its maximum value, and then rapidly returns to its minimum value, and its amplitude and cycle are constant. Further, the fixed clock generation unit 23 outputs a fixed clock CK2 having the same frequency as the original oscillation clock CK0 (that is, the same as the sawtooth wave signal S22). The duty ratio of the fixed clock CK2 is, for example, 50%.

As shown in FIG. 3, the hold unit 30 responds to the input of the light beam detection signal S10 from the photodetector 10 and in response to the instantaneous value V of the sawtooth wave signal S22 at that time.
x is detected and stored, and the state in which the instantaneous value Vx is stored is held until the scanning of one line is completed.

The instantaneous value Vx is information indicating which time point in one cycle of the sawtooth wave signal S22 the light beam enters the photodetector 10, ie, the light beam detection signal S.
It is information indicating the phase difference between the sawtooth wave signal S22 and the sawtooth wave signal S22.

The original dot clock generating section 40 has the instantaneous value Vx held by the holding section 30 and the sawtooth wave signal S22 inputted from the sawtooth wave generating section 22.
When the sawtooth wave signal S22 is less than or equal to the instantaneous value Vx, the binary original dot clock CK1 is output at "L" level, and when it exceeds the instantaneous value Vx, it is at "H" level. That is, the original dot clock generator 4
By 0, the original dot clock CK1 is generated in synchronization with the light beam detection signal S10 and having the same cycle as the sawtooth wave signal S22 having a stable frequency.

By the way, the duty ratio of the original dot clock CK1 changes according to the instantaneous value Vx. For example, when the rising edge (input timing) of the light beam detection signal S10 is near the rear end of the cycle of the sawtooth wave signal S22 as shown in FIG. 4A, the "H" level period of the original dot clock CK1 is Extremely shorter than the "L" level period. On the contrary, as shown in FIG. 4B, the light beam detection signal S
When the rising edge of 10 is near the front end of the cycle of the sawtooth wave signal S22, "L" of the original dot clock CK1.
The level period is extremely shorter than the "H" level period.

Thus, the duty ratio is 0% or 10
If the original dot clock CK1 close to 0% is used as it is as a control clock, malfunction may occur due to omission of detection of a pulse edge.

Therefore, in the control signal generator 1 of the present embodiment, the dot clock SYN with an appropriate duty ratio is used.
A clock switching unit 50 is provided to supply CK.

The clock switching unit 50 includes a reference value setting unit 5
1, a select signal generator 52, a selector 53, and a pulse shaper 54. Reference value setting unit 51
5, the selection signal generating unit 52 sets the setting range Ra excluding both ends of the amplitude R in the sawtooth wave signal S22.
Show against. That is, the voltage signal corresponding to the lower limit value V1 and the upper limit value V2 of the setting range Ra is output. Lower limit value V
1 is slightly larger than the minimum value Vmin of the sawtooth wave signal S22 (V2>V1> Vmin), and the upper limit value V2 is slightly smaller than the maximum value Vmax of the sawtooth wave signal S22 (Vma).
x> V2).

The select signal generator 52 includes a hold unit 3
The instantaneous value Vx stored as 0 is compared with the input values (lower limit value V1 and upper limit value V2) from the reference value setting unit 51, and the select signal S52 indicating the comparison result is output.

The selector 53 is responsive to the select signal S52 to output the original dot clock CK1 or the fixed clock CK2.
Is selectively selected and sent to the pulse shaping section 54. Instantaneous value V
When x is a value within the setting range Ra, the duty ratio of the original dot clock CK1 is within a proper range.
The original dot clock CK1 whose timing completely matches the light beam detection signal S10 is sent to the pulse shaping unit 54. On the other hand, when the instantaneous value Vx is not within the setting range Ra, there is a possibility of malfunction as described above. Therefore, the fixed clock CK is used instead of the original dot clock CK1.
2 is sent to the pulse shaping section 54.

In the example of FIG. 5, n lines, (n +
In line 1) and line (n + 3), the instantaneous value Vx is a value within the setting range Ra, and the select signal S52 indicates the selection of the original dot clock CK1. (N + 2)
In the line, the instantaneous value Vx is a value outside the setting range Ra,
The select signal S52 gives an instruction to select the fixed clock CK2.

As shown in FIG. 4, the rising edge of the fixed clock CK2 is the sawtooth wave signal S2.
Since 2 coincides with the timing when the minimum value Vmin is reached, a slight phase difference is usually generated between the fixed clock CK2 output from the selector 53 and the light beam detection signal S10. However, this phase difference can be made a slight difference in which the positional deviation of dots on the reproduced image is not noticeable by selecting the setting range Ra in a wide range.

The pulse shaping section 54 is composed of, for example, a multivibrator circuit and outputs a pulse having a duty ratio of 50% synchronized with an input signal as a dot clock SYNCK. That is, the pulse shaping section 54 converts the original dot clock CK1 into the dot clock SYNCK having a duty ratio of 50%.

In the above embodiment, the fixed clock CK
Instead of inputting 2 to the pulse shaping section 54, the dot clock SYNCK may be output as it is. The duty ratio of the dot clock SYNCK is not always 50.
It does not have to be%.

Instead of the sawtooth wave signal S22, a ramp waveform signal whose instantaneous value changes in an exponential curve can be used. However, one monotonous change period (for example, increase period)
It is desirable to use a waveform in which the other monotonically changing period (for example, the decreasing period) is extremely short (zero is the best) as compared with.

[0038]

According to the inventions of claim 1 and claim 2,
A control clock for modulating the light beam at a constant cycle in synchronization with the deflection of the light beam can be generated by using an oscillating element having a frequency about the same as that of the control clock regardless of signal delay. That is, the frequency of the control clock can be increased to the same level as that of the oscillating element without increasing the positional deviation of dots between lines and minimizing the generation of high-frequency noise, thereby increasing the speed of image scanning. be able to.

[Brief description of drawings]

FIG. 1 is a perspective view showing an outline of a scanning optical system according to the present invention.

FIG. 2 is a block diagram of a control signal generation device of the present invention.

FIG. 3 is a waveform diagram of an output signal of each unit in the control signal generation device.

FIG. 4 is a diagram showing a relationship between a light beam detection signal and a pulse width of an original dot clock.

5 is a time chart showing the operation of the clock switching unit of FIG.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 control signal generation device 10 photodetector 22 sawtooth wave generation unit (signal generation unit) 23 fixed clock generation unit (second clock signal generation unit) 30 hold unit (signal holding unit) 40 original dot clock generation unit (clock Signal generation means) 50 Clock switching unit (clock switching means) CK1 Original dot clock (clock signal) CK2 Fixed clock (second clock signal) Ra setting range S10 Light beam detection signal S22 Sawtooth wave signal (ramp waveform signal) V1 Lower limit value V2 Upper limit value Vmin Minimum value Vmax Maximum value Vx Instantaneous value

Claims (2)

[Claims] 1. A photodetector for detecting a light beam for scanning an original image line-sequentially, a signal generating means for outputting a ramp waveform signal having a constant amplitude and period, and a light beam from the photodetector. In response to the input of the detection signal, the signal holding means for storing the instantaneous value of the ramp waveform signal at that time, by the magnitude comparison between the ramp waveform signal and the instantaneous value stored by the signal holding means, A control signal generation device for scanning a light beam, comprising: a clock signal generation unit that generates a clock signal having a constant cycle in synchronization with the light beam detection signal. 2. A second clock signal generating means for generating a second clock signal having a constant cycle in synchronization with the ramp waveform signal, and the instantaneous value stored in the signal holding means is a minimum of the ramp waveform signal. When the value is within the setting range from the lower limit value larger than the value to the upper limit value smaller than the maximum value, the clock signal is selected, and when the value is out of the setting range, the second clock signal is selected and selected. 2. The control signal generation device for scanning a light beam according to claim 1, further comprising clock switching means for selectively outputting the clock signal or the second clock signal.