JPH08149497A - PAL signal color demodulation circuit - Google Patents

Abstract

PURPOSE: To provide the color demodulation circuit for PAL signal with simple configuration by providing a phase shift circuit, vector adder, a pair of demodulation multipliers, VCO circuit for generating a sub-carrier, and phase detection circuit for detecting the phases of a burst signal and the sub-carrier, or the like. CONSTITUTION: When demodulating a color difference signal by digital signal processing, the phase of the sub-carrier is shifted 9 at 0 deg., 90 deg., 180 deg. and 270 deg. by providing a phase shift circuit 9, vector adder 10 and a pair of demodulation multipliers 3 and 4. Then, the vectors of two adjacent carriers are added and multiplied with a chroma signal. Thus, the signal can be demodulated to signals B-Y and R-Y and a memory or a high frequency integrated circuit is unnecessitated. Besides, when a demodulation arithmetic circuit composed of a current reverse circuit, a pair of demodulation selectors and a switch timing generating circuit or the like is used, the circuit configuration can be further simplified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PAL signal color demodulation circuit for demodulating a color difference signal of a PAL signal, which is one of the transmission formats of television signals, by digital signal processing.

[0002]

2. Description of the Related Art FIG. 7 shows a conventional PA using an analog method.
FIG. 3 is a block diagram of an L (Phase Alternation by Line) signal demodulation circuit. In the figure, the composite PAL signal is input to the YC separation circuit 1 and separated into a luminance signal Y and a chroma signal C. The luminance signal Y is input to the Y signal processing circuit 2, and the frequency and contrast are corrected.

On the other hand, the chroma signal C output from the YC separation circuit 1 is input to the demodulation multipliers 3 and 4 for color demodulation and also to the burst extraction circuit 20 for reference of the color synchronization system operation. The burst signal that becomes is extracted. This burst signal is an APC (Automatic Phase)
It is input to the control circuit 5 and the phase detection circuit 6.

The APC circuit 5 is composed of a phase comparator 5a, a low-pass filter (LPF) 5b, and a voltage controlled crystal oscillator (VCXO) 5c externally attached to a crystal oscillator with an oscillation frequency of 4.43 MHz. PLL (Phase Locked Loop) that generates 4.43 MHz subcarrier locked to the signal
Is composed.

The phase detection circuit 6 uses the burst signal and the VCX.
The output signal of O5c is compared to monitor whether or not synchronization is achieved. In the PAL system, since the phase of the burst signal alternates every 1H (H is a horizontal period), a BID signal that is inverted every 1H (fH / 2 period) is generated accordingly, and the synchronization is not achieved. At this time, the polarity of the BID signal is inverted.

Since the subcarrier output from the APC circuit 5 is synchronized with the burst signal, the burst signal is +
When it is in (RY), the burst position is 0 ° in phase, and in-(RY), the burst position is 0 ° in phase.

Burst is + for this subcarrier
When it is in (RY), as shown in FIG.
Or -135 ° phase-shifted, and when it is at-(RY), the chroma signal C is multiplied by the carrier whose phase is shifted by 45 ° -135 ° to obtain (RY) respectively.
The signal and the (BY) signal can be demodulated.

Therefore, the subcarrier output from the APC circuit 5 is 135 °, −13 at the demodulation carrier generation circuit 21.
If the phase is shifted by 5 °, 45 ° or −45 °, the output is switched according to the alternating phase by the BID signal output from the phase detection circuit 6 and input to the demodulation multipliers 3 and 4,
A (BY) signal and an (RY) signal are obtained at the outputs of the demodulation multipliers 3 and 4, respectively.

In order to perform digital signal processing on such a demodulation circuit, the oscillation frequency of the VCXO 5c is set to, for example, 4
It is necessary to use fsc. In that case, the minimum phase unit that can be processed by the gate circuit such as a flip-flop is 90 °, and the signal processing in units of 45 ° required for PAL signal processing becomes impossible. Therefore, a memory for converting the angle into a trigonometric function for calculation is required, resulting in a large circuit configuration and a large scale, which is expensive.

In order to process in units of 45 °, V
It is possible to set the oscillation frequency of the CXO5c to 8 fsc and perform signal processing with an 8 fsc clock, but for that purpose, 20 MHz
An integrated circuit having characteristics exceeding the above is required, which not only makes it extremely expensive, but also makes it difficult to take clock timing.

[0011]

As described above, when a video signal is processed as a digital signal, the phase timing that can be processed is determined in relation to the operation clock.
Therefore, when handling a phase signal in units of 45 ° such as a PAL signal, it is necessary to interpose a memory and the like, which has a disadvantage that the circuit configuration and the scale become large.

Therefore, an object of the present invention is to provide a PAL signal color demodulation circuit having a simple structure by digital signal processing.

[0013]

A color demodulation circuit for a PAL signal according to the present invention inputs an APC circuit which generates a clock signal phase-synchronized with a burst signal of a chroma signal and an output of the APC circuit to generate a subcarrier. VCO circuit, a phase shift circuit for inputting the output of the VCO circuit to shift the phase of the subcarrier, a vector adder for vector-adding the subcarriers phase-shifted by the phase shift circuit, and an output signal of the vector adder. And a demodulation multiplier that multiplies the chroma signal and demodulates the color difference signal.

The color demodulation circuit for PAL signals according to the present invention comprises:
An APC circuit that generates a clock signal that is phase-synchronized with the burst signal of the chroma signal, a VCO circuit that inputs the output of the APC circuit to generate a subcarrier, and a phase detection circuit that detects the phase between the burst signal and the subcarrier. , A polarity inversion circuit that inverts the polarity of the chroma signal, a pair of demodulation selectors that switch the chroma signal and the polarity inversion chroma signal to output a color difference signal, the output of the phase detection circuit and VC.
And a switch timing generation circuit for inputting the output of the O circuit and instructing the switching timing of the pair of demodulation selectors.

[0015]

According to the PAL signal color demodulation circuit of the present invention, in demodulating a color difference signal by digital signal processing, a phase shift circuit, a vector adder, and a pair of demodulation multipliers are provided, and a subcarrier is set to 0. °, 90 °, 1
Phase shifts to 80 ° and 270 °, vector addition of two adjacent carriers, and multiplication by a chroma signal can be demodulated into a (BY) signal and an (RY) signal. Is unnecessary. Further, the circuit configuration can be further simplified by using a demodulation arithmetic circuit including a polarity inverting circuit, a pair of demodulation selectors, a switch timing generation circuit, and the like.

[0016]

FIG. 1 is a block diagram showing an embodiment of a color demodulation circuit for PAL signals according to the present invention. The same parts as those shown in FIG. In this embodiment, the composite PAL input to the YC separation circuit 1 is input.
The signal is separated into a luminance signal Y and a chroma signal C, and the luminance signal Y is corrected in frequency and contrast in the Y signal processing circuit 2.

The chroma signal C is input to the demodulation multipliers 3 and 4 for color demodulation, and a burst switch circuit 7 for arranging the 1H alternating burst signals, which is the reference of the color synchronization system operation, in one direction. Entered in.

Generally, the chroma signal C of the PAL system alternates every 1H in the ± (RY) direction. However, in the signal processing of the color synchronization system, only the alternation information is left and the phase of the burst signal is changed. Processing in one direction is easier. Therefore, in the burst switch circuit 7, the phase detection circuit 6
Based on the fh / 2 period BID signal output from the burst signal as shown in FIG.
As shown in (b), the processes are collectively performed in the + (RY) direction.

The burst signal output from the burst switch circuit 7 is input to the APC circuit 5 and the phase detection circuit 6. The APC circuit 5 has a configuration in which a phase comparator 5a, a low-pass filter (LPF) 5b, and a voltage-controlled crystal oscillator (VCXO) 5c to which a 17.7 MHz crystal oscillator is externally attached are connected in a PLL, and a burst signal is generated. Locked 4 fsc (17.7 MHz)
To generate a clock and supply it to the voltage controlled oscillator (VCO) 8.

The phase detection circuit 6 uses the burst signal and VCO 8
Of the PAL signal, the burst signal phase alternates every 1H, so that it is inverted every 1H (fh / 2). (Period) When the BID signal is generated and the synchronization is not obtained, the polarity of the BID signal is inverted.

FIG. 3 shows the burst signal (C signal) when APC is locked and the sampling state at the 4 fsc clock. When the signal processing is performed with the 4fsc clock, the APC locked clock samples the peak and center of the chroma signal C at the 1fsc cycle (circles in the figure).

Therefore, in the digital signal processing using the 4 fsc clock, the processing is performed at a cycle of 90 ° of the C signal phase. For example, in the burst switch circuit 7 described above, the-(RY) direction is used. Burst signal +
In order to put them together in the (RY) direction, if they are delayed by 3 clocks, there is a 180 ° phase delay, and they are put together in the same direction.

The clock output from the APC circuit 5 is VCO.
Enter in 8. This VCO 8 has an operating frequency of 4 fsc, and advances the phase by 90 ° for each clock.
It is a fixed oscillator that repeats 1, 0, -1, and is an oscillator of 4.43 MHz (fsc) that makes one cycle with 4 clocks.

The output of the VCO 8 is given to the phase shift circuit 9. The phase shift circuit 9 shifts the phase to 90 °, 180 ° and 270 ° as shown in FIG. This phase shift is performed by delaying the output of the VCO 8 by 1, 2, and 3 clocks, respectively, by utilizing the delay of 90 degrees in units of 4fsc clock as in the burst switch. Thus, in the phase shift circuit 9, 0 °, 90 °, 180 °, 270 synchronized with the burst signal.
It is possible to generate four-phase subcarriers of 4 °.

This subcarrier is used to demodulate the chroma signal C of the PAL signal.
゜ The phases do not match. However, if two adjacent carriers having a 90 ° phase difference are vector-added, the added energy becomes the inner product of the vectors, and therefore appears in the direction of 45 °. If this principle is used, (BY), ± (R-
It becomes possible to generate demodulation carriers that coincide with the Y) axis.

That is, for the carriers in the (BY) axis direction, those of 180 ° and 270 ° of the four phase subcarriers may be added, and similarly, 0 ° and 270 in the + (RY) axis direction.
The angles of 90 ° and 180 ° in the ° and-(RY) axes may be added. In the vector adder 10 that operates based on such a principle, the demodulation axes alternate between positive and negative in order to demodulate the (RY) signal. Therefore, the BI detected by the phase detection circuit 6 is output.
The demodulation carrier is created by switching according to the D signal. The output of the vector adder 10 is a pair of demodulation multipliers 3,
4 and is multiplied by the chroma signal C from the YC separation circuit 1 to demodulate the (BY) signal and the (RY) signal, respectively.

FIG. 5 is a block diagram showing another embodiment of the PAL signal color demodulation circuit according to the present invention. The same components as those shown in FIG. 1 are designated by the same reference numerals. In this embodiment, the YC separation circuit 1, the Y signal processing circuit 2, the AP
The C circuit 5, the phase detection circuit 6, the burst switch circuit 7, and the VCO 8 have exactly the same configurations as those of the above-mentioned embodiment, and therefore their explanations are omitted. Further, the present embodiment shows an embodiment in which the phase shift circuit 9, the vector adder 10, and the demodulation multipliers 3 and 4 in the above-mentioned embodiments are integrated as a demodulation arithmetic circuit 11.

Here, the configuration of the demodulation arithmetic circuit 11 will be described together with the operation with reference to the table shown in FIG. The input chroma signals Co to C6 in the first stage of the table shown in FIG. 6 represent the signals sampled at the 4fsc clock.
The subcarrier output by 8 corresponds to 0 ° of the VCO.
The second row of the table shows the states of four-phase subcarriers that are the basis of demodulation. In the third row of the table, (BY), ±
The result of vector addition performed to find the carrier that coincides with the (RY) axis direction is shown. Further, the fourth row of the table shows the multiplication result of the chroma signal C and the demodulation carrier (the third row value).

As can be seen from the result of this multiplication, (B-
In order to obtain the Y) and (RY) demodulated signals, the polarities of the chroma signal C sampled at 4 fsc should be inverted under a certain condition. The demodulation calculation circuit 11 is a concrete configuration of this table.
a, demodulation selectors 11b and 11c, and a switch timing generation circuit 11d.

The switch timing generation circuit 11d is
Based on the subcarrier output from the VCO 8 and the BID signal output from the phase detection circuit 6, a timing signal that produces the operation shown in the table of FIG. 6 is generated, and using this switching signal, the demodulation selector 11b, By selecting the positive / negative chroma signal C input to 11c, the (BY) and (RY) demodulated signals can be obtained as in the embodiment of FIG.

Thus, according to the embodiment shown in FIG.
Polarity inversion circuit 11a and demodulation selectors 11b and 11c
And the SW timing generation circuit 11d has a simple configuration.
The digital demodulation of the AL signal can be realized.

[0032]

According to the present invention, it is possible to provide a simple and inexpensive device, which does not require the provision of a memory or a high frequency integrated circuit as in the prior art. Also, a phase shift circuit,
According to the configuration in which the demodulation arithmetic circuit is provided, paying attention that the processing result by the logical configuration including the vector adder and the demodulation multiplier becomes equal to the result of the polarity inversion of the chroma signal, the device is simpler and less expensive. The effect that can be obtained is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is an explanatory diagram of burst switching according to the present invention.

FIG. 3 is an explanatory diagram of sampling with a 4fsc clock according to the present invention.

FIG. 4 is an explanatory diagram of a phase shift according to the present invention.

FIG. 5 is a block diagram showing another embodiment of the present invention.

FIG. 6 is a table showing calculation results according to the embodiment shown in FIG.

FIG. 7 is a block diagram of a conventional device.

FIG. 8 is an explanatory diagram showing a conventional phase shift situation.

[Explanation of symbols]

 1 YC Separation Circuit 2 Y Signal Processing Circuit 3, 4 Demodulation Multiplier 5 APC Circuit 6 Phase Detection Circuit 7 Burst Switch Circuit 8 VCO 9 Phase Shift Circuit 10 Vector Adder 11 Demodulation Operation Circuit 11a Polarity Inversion Circuit 11b, 11c Demodulation Selector 11d switch timing generator

Claims (2)

[Claims] 1. An APC circuit that generates a clock signal that is phase-synchronized with a burst signal of a chroma signal, a VCO circuit that inputs an output of the APC circuit to generate a subcarrier, and an input of an output of the VCO circuit. A phase shift circuit for shifting the phase of the subcarriers, a vector adder for vector-adding the subcarriers phase-shifted by the phase shift circuit, and a color difference signal by multiplying an output signal of the vector adder and a chroma signal. And a demodulation multiplier that demodulates the PAL signal. 2. An APC circuit that generates a clock signal that is phase-synchronized with a burst signal of a chroma signal, a VCO circuit that receives the output of the APC circuit and generates a subcarrier, and the burst signal and the subcarrier. A phase detection circuit that detects a phase, a polarity inversion circuit that inverts the polarity of the chroma signal, a pair of demodulation selectors that switch the chroma signal and the polarity inversion chroma signal to output a color difference signal, and the phase detection circuit And a switch timing generation circuit for inputting the output of the VCO circuit and instructing the switching timing of the pair of demodulation selectors, the color demodulation circuit of the PAL signal.