JPH0818018A - Nonvolatile semiconductor memory device - Google Patents

Abstract

(57) [Abstract] [Purpose] Write confirmation read operation and write pulse rise and fall, erase confirmation read operation and erase pulse rise and fall are accelerated to enable high-speed programming and erase. Providing an EEPROM. In an EEPROM using electrically rewritable non-volatile memory cells, an array of non-volatile memory cells formed on the same chip is divided into two, and each sub-array ARYl, ARYr has the same word. It is characterized in that data writing is simultaneously performed to the memory cells connected to the line, and while the data writing operation is being performed in one sub-array, the write confirmation read operation is performed in the other sub-array.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable nonvolatile semiconductor memory device, and more particularly to an array-divided nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art As a rewritable non-volatile semiconductor memory device, an electrically rewritable EEPROM has hitherto been available.
M is known. Among them, a NAND type E in which a plurality of memory cells are connected in series to form a NAND cell block
EPROMs are attracting attention because they can be highly integrated.

One memory cell of a NAND type EEPROM has a FETMOS structure in which a floating gate and a control gate are laminated on a semiconductor substrate with an insulating film interposed therebetween, and a plurality of memory cells adjacent to each other have a source, The cells are connected in series so as to share the drain to form a NAND cell. Such NAND cells are arranged in a matrix to form a memory cell array.

NAND arranged in the column direction of the memory cell array
The drains on one end side of the cells are commonly connected to the bit line via the select gate transistors, and the sources on the other end side are also connected to the common source line via the select gate transistors. The control gate of the memory transistor and the gate electrode of the selection gate transistor have control gate lines (word lines) in the row direction of the memory cell array,
Commonly connected as a select gate line.

The operation of this NAND type EEPROM is as follows. Data writing is sequentially performed from the memory cell farther from the bit line. Explaining the case where the transistor is an n-channel, a high potential (for example, 20 V) is applied to the control gate of the selected memory cell, and the control gate and the selection gate transistor of the non-selected memory cell on the bit line side from this are applied. An intermediate potential (for example, 1
0V) is applied. 0 for the bit line depending on the data
V (eg, defined as “1” data) or an intermediate potential (eg, defined as “0” data) is applied. At this time, the potential of the bit line is transmitted to the drain of the selected memory cell through the selection gate transistor and the non-selected memory cell.

When there is data to be written (“1” data), a high electric field is applied between the gate and drain of the selected memory cell or between the gate and the substrate, and electrons are tunnel-injected from the substrate to the floating gate. . As a result, the threshold value of the selected memory cell moves in the positive direction. When there is no data to write (“0” data), there is no threshold change.

At the time of erasing data, a high potential is applied to the p-type substrate (in the case of a well structure, the n-type substrate and the p-type well formed therein), the control gates and select gate transistors of all memory cells are The gate is set to 0V. As a result, in all the memory cells, electrons in the floating gate are emitted to the substrate, and the threshold value moves in the negative direction.

At the time of data reading, the non-selected memory cell on the bit line side of the selected gate transistor and the selected memory cell is turned on, and 0V is applied to the gate of the selected memory cell. At this time, by reading the current flowing through the bit line, the data of "0" and "1" can be discriminated.

Such a conventional NAND type EEPRPM
In general, a so-called verify operation called a write confirmation read operation and an erase confirmation read operation is usually performed after the write operation and the erase operation. For example, in the case of a 16 Mbit NAND EEPRPM write operation, a plurality of write pulses are input to the control gate of the selected memory cell, and a write confirmation read operation is performed for each write pulse.

Specifically, as described above, during the write operation, a high potential (for example, 20 V) and an intermediate potential (for example, 1 V).
0 V) is required and these are generated by the booster circuit in the chip, but it takes 25 μs to rise and fall the pulses of the high potential and the intermediate potential. Also, although the threshold voltage of the selected memory cell moves in the positive direction during the write operation, it is determined whether the threshold voltage is within the target voltage range,
That is, in order to perform the write confirmation read operation, it is necessary to start from the precharge of the bit line, select the control gate line, sense amplifier operation, and a series of read operations equivalent to the random read operation. It takes 25 μs.

The time width of the write pulse is 20 μs.
When writing is performed with 6 pulses, the time required for that is (25 + 20 + 25) × 6 = 420 μs. Therefore, 71% of the total writing time is 300 μs
Is spent for the rise and fall of the high potential and the intermediate potential and the write confirmation read operation, and the remaining 29% of 120 μs.
Is the total time of the actual write pulse. Also, 16M
In the erase operation of the bit NAND type EEPROM as well, most of the time is spent for the erase pulse generation and erase confirmation read operation.

For example, when erasing a large number of blocks (multi-block erase), one block, that is, 512 bytes (4 Kbits) of one NAND block is set as a minimum unit, and a maximum of 5 blocks.
Simultaneous erasing of the 12-byte NAND block is performed. In this erase confirmation read operation, since the threshold voltage of the selected memory cell after erase moves in the negative direction, the write confirmation read operation is performed to determine whether or not the threshold voltage is within the target negative voltage region. Can be done in less time. The threshold voltage after writing is, for example, 0.5 V to 3 V depending on whether the threshold voltage after erasing is 0 V or less.
This is because the memory cell current becomes larger than that in the determination as to whether or not it is within the range, and the precharged bit line can be discharged at such a high speed.

However, even in the erase confirmation read operation, the precharge of the bit line is required first, and then the control gate line in the erased NAND block is selected to operate the sense amplifier. In each erased NAND block, all the control gate lines are selected, which is different from the normal random read operation, but this erase confirmation read operation is almost equivalent to the random read operation, and is 1NA.
It takes about 15 μs to perform the erase confirmation read operation of the ND block.

Therefore, the time required for multi-block erase of all 512 NAND blocks is 512 NAND.
Address 200ns × 512, erase pulse rise and fall 200μs, erase pulse time width 3
ms, 15 μs × 512 for erase confirmation read operation, which is about 8 ms in total, and 63% of 5 ms is spent for erase confirmation read operation other than the actual erase operation.

The write confirmation read operation and the erase confirmation read operation are not limited to the NAND type EEPROM,
This is an indispensable operation mode that is also performed in the conventional NOR type EEPROM. The ratio of the write confirmation read operation and the rise / fall of the write pulse to the whole write time is very large, and the ratio of the erase confirmation read operation and the rise / fall of the erase pulse to the whole erase time is very large. NA that writing time and erasing time are long
This is a problem not only in the ND type EEPROM but also in the NOR type EEPROM.

In addition, the ratio of the write confirmation read operation and the rise and fall of the write pulse to the entire write time, and the ratio of the erase confirmation read operation and the rise and fall of the erase pulse to the total erase time are NAND. Type EEPROM and N
It will increase as the capacity of the OR type EEPROM increases. This is because the wiring resistance and the capacitance of the control gate line, the wiring resistance and the capacitance of the bit line, and the capacitance of the well portion of the memory cell increase as the capacitance increases, so that the charging and discharging time of the control gate line and the bit line becomes long. This is because the writing confirmation reading and the erasing confirmation reading are delayed. further,
This is because the capacities of the control gate line, the bit line, and the well portion of the memory cell increase, so that the rise and fall times of the write pulse and erase pulse increase.

[0017]

As described above, the conventional N
In AND type EEPROM and NOR type EEPROM,
In the entire programming time (or the entire erasing time), the ratio of the time required for the write confirmation read operation (or the erase confirmation read operation) and the rise and fall of the write pulse (or the erase pulse) becomes large, resulting in the write operation. Also, there is a problem that the speed of erasing is impaired. Further, this problem is caused by the NAND type EEPROM and the NOR type EEPROM.
It became more remarkable as the capacity was increased.

The present invention has been made in consideration of the above circumstances, and an object thereof is to perform a write confirmation read operation and a rise / fall of a write pulse, an erase confirmation read operation and a rise of an erase pulse, An object of the present invention is to provide a non-volatile semiconductor memory device in which the fall time is accelerated and, as a result, high speed writing and high speed erasing are possible.

[0019]

In order to solve the above problems, the present invention employs the following configurations. That is, according to the present invention, in a nonvolatile semiconductor memory device using a rewritable nonvolatile memory cell, an array of nonvolatile memory cells formed on the same chip is divided into a plurality of subarrays, and at least two of the divided subarrays are divided. Data writing or erasing at the same time, and the data writing or erasing timing of another sub-array is shifted from the data writing or erasing timing of any sub-array.

The preferred embodiments of the present invention are as follows. (1) The array is divided into two, and data writing or erasing is performed simultaneously in each divided sub-array, and the data writing or erasing timing of one sub-array is set to the data writing or erasing timing of the other sub-array. I tried to shift it. (2) Data writing or erasing consists of data writing operation or erasing operation and subsequent write confirmation read operation or erase confirmation read operation multiple times, and data writing operation or erasing operation is performed on one sub-array. In the meantime, perform the write confirmation read operation or erase confirmation read operation on the other sub-array. (3) Start the first data write operation in one sub-array, start the subsequent write confirmation read operation after the data write operation is completed, and at the same time, start the first data write operation in the other sub-array and write the data. After the operation is completed, start the subsequent write confirmation read operation, and at the same time, start the next data write operation in one sub-array. (4) If the time required for the write operation or erase operation is longer than the time required for the write confirmation read operation or erase confirmation read operation, after the write confirmation read operation of one sub array is completed, the write operation of the other sub array is completed. Wait for the interval and start the write operation of one subarray and the write confirmation read operation of the other subarray at the same time. (5) When the time required for the write confirmation read operation or erase confirmation read operation is longer than the time required for the write operation or erase operation, the write confirmation read operation of the other subarray ends after the write operation of one subarray ends. Wait for the interval and start the write confirmation read operation of one sub-array and the write operation of the other sub-array at the same time. (6) Data writing or erasing is simultaneously performed on memory cells connected to different word lines of different sub-arrays. (7) A plurality of sub-arrays share a word line, and data writing or erasing is simultaneously performed on memory cells connected to the same word line of different sub-arrays. (8) The non-volatile semiconductor memory cells forming the array are electrically rewritable non-volatile memory cells, and a plurality of these are connected in series to form a NAND cell.

[0021]

According to the present invention, a memory cell array is divided into at least two, and while a write operation or an erase operation is selectively performed on some of the memory cells in a divided sub-array, another sub-array is Write and read operations or erase and read operations are selectively performed simultaneously in the memory cells of the same section, and the capacitance and resistance of the control gate line and bit line are reduced due to the array division, and the write or erase operation and the write confirmation and read operation are performed. Or by performing the erase confirmation read operation simultaneously and alternately in each sub-array,
The total writing and erasing time including the confirmation reading operation can be shortened.

For example, a 16 Mbit NAND type EEPR
When the memory cell array of PM is divided into two, A and B, and the write operation and the write confirmation read operation are simultaneously and alternately performed in the sub-array A and the sub-array B, the high potential pulse and the intermediate potential pulse for writing are Startup and shutdown is 1
2.5 μs, the write confirmation read operation is shortened to 15 μs. This is because the resistance and the capacitance of the control gate are both halved by dividing the memory cell array into two.
This is because the number of bit lines to be precharged has been halved.

Therefore, the time width of the write pulse is 20 μs.
When writing is performed with 6 pulses, the time required for the writing is (12.5 + 20 + 15) × 6 + 15 = 300 μs, which is much shorter than the conventional time. Note that the sub-array A is added with 15 μs in the second term on the left side of the above equation.
This is because the write operation and the write confirmation read operation are out of phase between the sub array B and the sub array B, and the sixth write confirmation read operation is finally performed in the sub array A or the sub array B.

Similarly, the speed of erasing is also increased,
512 NAND blocks The time required for all multi-block erase is 2 to load 512 NAND addresses.
00ns x 512, 10 for erase pulse rise and fall
0 μs, the erase pulse time width is 3 ms, and the erase confirmation read is 5 μs × 512, which is about 5.76 ms in total, which is much shorter than in the past. Therefore, according to the present invention, high speed writing and erasing are possible.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. In FIG. 1, M11l to Mmnl and M11r to Mmnr are memory cells, LA1l to LAnl, LA1r to LAnr are sense amplifier / data latch circuits, R / D1 to R / Dm are row decoder circuits, and WL1l to WLml and WL1r to WLmr are respectively. Word line, A
RYl and ARYr are sub-arrays formed by dividing the memory cell array.

The gist of the present invention is to divide a memory cell array formed on the same chip into at least two and perform a write confirmation read operation on the sub array ARYr during the write operation of the sub array ARYl, and a write confirmation read on the sub array ARYl. A write operation is performed in the sub-array ARYr during operation.

For example, consider the case where the word line WL2l is selected. In this case, the row decoders R / D1 to R / Dm
According to the input address and control circuit, the word lines WL2l and WL2r can be simultaneously selected for the left and right sub-arrays ARYl and ARYr sandwiching the row decoder, or the word lines WL2l and WL2r can be independently selected. Here, the word line W in the sub-array ARYl
A case of simultaneously selecting L2l and the word line WL2r in the sub-array ARYr will be described.

First, a row address for selecting the word lines WL2l and WL2r is input. Next, the data to be written is sequentially page-loaded from LA1l to the sense amplifier / data latch circuit. And just LAnl
Loaded, the word line WL2l is selected next,
Sense amplifier / data latch circuits LA1l-LAnl are connected to the memory cells M21l-M2nl via bit lines BL1l-BLnl.
The data loaded in will start to be written.

The data to be written is continuously page-loaded from LA1r to LAnr even after being loaded into the sense amplifier / data latch circuit LAnl. And L
When loaded to Anr, word line WL2r is selected,
Sense amplifier / data latch circuits LA1r-LA are connected to the memory cells M21r-M2nr via bit lines BL1r-BLnr.
The data loaded in nr begins to be written.

In parallel with the write operation for the word line WL2r of the sub-array ARYr, the sub-array ARY
A write confirmation read operation is performed on the word line WL2l of l. This write confirmation read operation is performed on the word line WL.
For 2l, it is performed after applying the write pulse for a certain time,
It is determined whether the threshold voltage of the written memory cell has reached a target value.

For this determination, a bit-by-bit verify circuit provided in each bit line is used, and the sense amplifier / data latch circuit of the bit line connected to the memory cell that needs to be rewritten can be rewritten. The data is stored in. Therefore, this is different from the normal read operation in that the sense amplifier / data latch circuit relating to the memory cell that needs to be rewritten by using the bit-by-bit verify circuit is different from the normal read operation, but other than that. Is the same as the normal read operation.

That is, with respect to the word line WL2l, the word line WL2l is temporarily brought into a non-selected state after the application of the write pulse for a certain time, and then the bit lines BL1l to BLnl are precharged. Next, the word line WL2l is selected again. However, the voltage applied to the selected word line at this time is different between writing and reading. Then, the memory cell M21l
The data of M2nl to M2nl are read to the bit lines BL1l to BLnl, and the sense amplifier / data latch circuit and the bit-by-bit verify circuit connected thereto detect that the data needs to be written again. It is stored in the latch circuits LA1l to LAnl.

The above operation is performed by the word line WL2l in the sub-array ARYl and the word line W in the sub-array ARYr.
Alternately repeated with L2r. That is, while the write operation is performed on the word line WL2r, the write confirmation read operation is performed on the word line WL2l, and then the write operation is performed on the word line WL2r while the write operation is performed on the word line WL2l. A confirmation read operation is performed. Then, the selected memory cells M21l-M
Of 2nl and M21r to M2nr, when the threshold voltages of the memory cells to be written all reach the target value, the entire write operation is completed.

This state is shown in FIG. FIG. 2A shows a case where the time required for the write operation is equal to the time required for the write confirmation read operation (verify), and the first data write operation is started in the sub-array ARYl, and this is performed after the data write operation is completed. At the same time when the write confirmation read operation subsequent to is started, the first data write operation is started in the sub-array ARYr. And sub-array ARY
After the data write operation is completed at r, the subsequent write confirmation read operation is started, and at the same time the sub array ARY
Start the next data write operation with l. That is, the timings of the write operation and the write confirmation read operation in the sub-arrays ARYl and ARYr are completely opposite.

FIG. 2B shows a case where the time required for the write operation and the time required for the write confirmation read operation are different (for example, the write operation time is longer). In this case, the sub-array ARYl waits for the next write operation to start until the write operation of the sub-array ARYr ends even after the write confirmation read operation ends. The same applies to the sub-array ARYr.

In this way, the waiting time from the write confirmation read operation to the next write operation is wasted, but the sub-arrays ARYl and ARYr do not simultaneously perform the write operation. The write operation requires boosting the word line, and the need for boosting both word lines at the same time increases the load on the booster circuit. However, this problem can be avoided by using FIG. 2B. .

If the write operation time is shorter than that shown in FIG.
Contrary to (b), it is sufficient to wait for the start of the write confirmation read operation until the end of the write confirmation read operation of the other even after the end of the write operation of one. In addition, if there is no problem even if the load on the booster circuit increases, the case shown in FIG.
As shown in (c), the waiting time can be eliminated to speed up data writing.

Next, a case will be described in which the sub-array ARYr performs the erase confirmation read operation while the sub-array ARYl is in the erase operation. FIG. 3 is a sectional view of the nonvolatile semiconductor memory device shown in FIG. For example, on the surface of the n-type semiconductor substrate 10 (n-sub), the sub-array ARYl,
P-wells 11 and 12 for ARYr (cell p-welll, cel
The case in which the row decoder other than the memory cell, the sense amplifier / data latch circuit and the p-type well 14 (peripheral p-well) other than the memory cell are formed will be described. The peripheral p-type well 14 is provided with a CMOS peripheral circuit.
You may provide the n-type well 15 (n-well) for comprising.

FIG. 4 is a sectional view when a p-type semiconductor substrate is used. On the surface of the p-type semiconductor substrate 20 (p-sub), n-type wells 2 for sub-arrays ARYl and ARYr are formed.
1, 22 (cell n-welll, cell n-wellr) and p-type wells 23 and 24 (cell p-well) in each n-type well.
l, cell p-wellr), a row decoder other than a memory cell, a sense amplifier / data latch circuit, and a p-type well 25 (peripheral p-well) for a peripheral circuit are formed. In addition, an n-type well 26 (n-well) for forming the peripheral circuit in CMOS may be provided.

In the case of such a p-type semiconductor substrate, the p-type semiconductor substrate 20 does not have a high voltage during the erase operation, and the n-type well or 22 between the sub-arrays performing the erase operation and p
The mold well 23 or 24 is at a high voltage.

Here, the word lines WL (m-1) l in the sub-array ARYl and WL1l to WL (m-2) l other than WLml, and the word lines WL (m-1) r and WLmr in the sub-array ARYr. Consider a case where the block erase operation is performed for WL1r to WL (m-2) r other than. In this case, first, the sub-array AR
Starting from the erase operation of Yl, the n-type semiconductor substrate 10, the p-type well 11 for the sub-array ARYl, and the word lines of the memory cells not to be erased, that is, WL (m-1) l and WLml, become high voltage, and the selected word The lines WL1l to WL (m-2) l are grounded, the memory cells M11l to M (m-2) nl are erased, and their threshold voltages are shifted in the negative direction.

During this period, the sub-array ARYr may perform the read operation without performing the erase operation. The erase operation in the sub-array ARYl starts, and after a certain specific time elapses, the erase confirmation read operation is performed in the sub-array ARYl. That is, the bit lines BL1l to BLnl are precharged and the word lines WL1r to WL of the erased memory cells are
Up to (m-2) l, the erase confirmation read operation is repeated in sequence. The erase operation is performed in the sub-array ARYr in parallel in time with the erase confirmation read operation in the sub-array ARYl. That is, the n-type semiconductor substrate 10 and the sub-array AR
The p-type well 12 for Yr and the word lines of the memory cells that are not erased, that is, WL (m-1) r and WLmr, become high voltage,
The selected word lines WL1r to WL (m-2) r are grounded, the memory cells M11r to M (m-2) nr are grounded, and the sub-arrays M11r to M11r to
The M (m-2) nr are erased and their threshold voltages shift in the negative direction.

If the erase confirmation read operation in the sub-array ARYl reveals that the erase is insufficient, then the sub-array A
After the erase operation in RYr, the erase operation in subarray ARYl begins again. In this case, the erase operation can be performed only on the word line of the memory cell in which the erase is insufficient.
In parallel with this, the erase confirmation read operation is performed in the sub-array ARYr.

The erase operation and erase confirmation read operation as described above are alternately repeated in the sub-arrays ARYl and ARYr to select the selected memory cells M11l to M (m-2) n.
When the threshold voltages of l and M11r to M (m-2) nr are all below the target value, the entire erase operation is completed.

As described above, according to this embodiment, the memory cell array is divided into two sub-arrays ARYl and ARYr, and while one sub-array selectively performs the write operation or the erase operation, the other sub-array selectively operates. At the same time, the write confirmation read operation or erase confirmation read operation is performed. Confirmation reading is performed by alternately reducing the capacitance and resistance of the control gate line and the bit line due to the array division and simultaneously performing the writing operation or the erasing operation and the writing confirmation reading operation or the erase confirmation reading operation in each sub-array. The total writing and erasing time including the operation can be shortened.

That is, the write confirmation read operation and the rise and fall of the write pulse, and the erase confirmation read operation and the rise and fall of the erase pulse are speeded up, whereby high speed write and high speed erase can be realized. . Further, according to the present invention, rewriting of data (writing after erasing data) can be performed in a short time, and not only the function as SSF (solid state file) is sufficiently fulfilled but also before shipment. Test time is greatly reduced, which leads to lower costs. (Embodiment 2) Next, an embodiment in which the present invention is applied to a NAND type EEPROM will be described. Although the basic structure is the same as that shown in FIG. 1, the memory cell array is composed of NAND cells in this embodiment.

5 to 7 show N in the sub-array ARYl.
8 to 10 are layout diagrams of the AND type memory cell array, and FIGS. 8 to 10 are layout diagrams of the NAND type memory cell array in the sub-array ARYr. The memory cell in each sub-array has a FETMOS structure in which a floating gate and a control gate are stacked on a semiconductor substrate with an insulating film interposed therebetween, and eight memory cells adjacent to each other share a source and drain. Are connected in series to form a NAND cell. Such NAND cells are arranged in a matrix to form a memory cell array.

NAND arranged in the column direction of the memory cell array
The drains on one end side of the cells are commonly connected to the bit line via the select gate transistors, and the sources on the other end side are also connected to the common source line via the select gate transistors. The control gate of the memory transistor and the gate electrode of the selection gate transistor have control gate lines (word lines) in the row direction of the memory cell array,
Commonly connected as a select gate line.

FIG. 11 is a circuit diagram of the sub-array ARYl side of the core part of the column system, such as a sense amplifier / data latch circuit, a bit-by-bit verify circuit, a batch detection circuit, and a precharge circuit, and FIG. 12 is a row on the sub-array ARYr side. It is a decoder circuit diagram. These circuits are not directly related to the present invention and are similar to the conventional device.

For example, a case will be described in which the write operation and the write confirmation read operation are alternately performed in parallel in time with respect to the word line WL11l in the sub-array ARYl and the word line WL11r in the sub-array ARYr.

13 to 15 are operation timing charts of the first half of the main node, and FIGS. 16 to 18 are operation timing charts of the latter half of the main node. Chip enable / CE
And the write enable / WE is changed from the "H" level to the "L" level, and the write operation is started. In this case, the write operation may be started by incorporating a write command into the input / output pin I / O pin from outside the chip.

First, from the input / output buffer to the input / output line I /
Data is written to the sense amplifier / data latch circuits LA1l to LAnl for the sub-array ARYl via O and I / OB. This is performed according to the column address generated from the column address counter in the chip as shown in FIG. 14 or the column address input from the outside, according to the column selection signals CSL1l, CSL2l, ..., CSL (n-1) l, C.
When SLnl sequentially becomes "H" level, serial data is sequentially written in the sense amplifier / data latch circuit in synchronization with this.

During the writing of data to the sense amplifier / data latch circuit, the write precharge control signal BLCU1 for the sub-array ARYl changes from Vss to VH + α,
All bit lines BL1l to BLnl of the sub-array ARYl are Vcc
It is precharged (preliminarily charged) to a higher intermediate potential VH.

Regarding the sub-array ARYl, the write control signal BLCDl is changed from Vss to V after data is written in the last n-th sense amplifier / data latch circuit LAnl.
It becomes H + α, and the bit line is discharged according to the data written in the sense amplifier / data latch circuit. That is, the bit line of the memory cell for writing is Vss (“1”
In the case of data), the bit line which is not written is kept at the intermediate potential VH (in the case of "0" data).

After that, the selected word line WL11l becomes V
The write potential becomes Vpp from ss, and other word lines WL12
The selection gate line SGD1l on the side of 1 to WL18l and the bit line contact changes from Vss to VH + α. At this time, electrons are injected ("1" written) into the floating gate in the memory cell connected to the bit line which is at Vss.

Next, in the sub-array ARYl, write confirmation read is performed. That is, the bit line reset signal PRSTDl changes from Vss to Vcc and is reset to Vss, and then the bit line precharge signal PREB.
l changes from Vcc to Vss, and the bit lines BL1l to BLnl are charged to the precharge potential VR for reading.

After that, the selected word line WL11l is set to V
ss is kept and the other word lines WL12l to WL18l of the same NAND cell block and the select gate lines SGD1l and SGS on the bit line contact side and the memory cell source line side are held.
1l changes from Vss to Vcc. In this case, WL12l to WL18
The levels of l, SGD1l, and SGS1l may be boosted above Vcc. As a result, the bit lines of the memory cells which are not programmed and the bit lines of the memory cells which are insufficiently programmed are discharged from VR to Vss.

Next, after the word lines WL12l to WL18l and the select gate lines SGD1l and SGS1l are returned to Vss, the comparison control signal CONl changes from Vss to Vcc, and the write data of the sense amplifier / data latch circuit and the write confirmation read And the bit line potential of. That is, regarding the memory cell to be written, the write data node VRY1l
Since (Fig. 11) is Vss, if the bit line is discharged to Vss, it means that the programming of the memory cell is insufficient and the threshold voltage shifts in the positive direction above the desired voltage. Since it has not occurred, the bit line maintains Vss in the next write cycle. Then, the bit line is not discharged to the memory cell which has been sufficiently written.

Therefore, in the next write cycle, writing is not performed for this bit line. Further, regarding the memory cell which is not programmed from the beginning, since the write data node VRYl is Vcc, the bit line is charged again. At this time, in the previous write cycle, the bit lines of the memory cells that have been sufficiently written and the bit lines of memory cells that have not been written from the beginning are charged to Vcc-Vth. Vth is Tr. 1 (FIG. 11).

Then, the write control signal BLCDl becomes Vss.
When the bit line information is transmitted to the sense amplifier / data latch circuit, that is, the write data node VRYl becomes Vss only for the memory cell to be written in the next write cycle.

Then, the batch detection circuit determines whether or not all writing has been completed. That is, when the collective detection reset signal RSTINl becomes Vss and the collective control signal APCONl for writing changes from Vss to Vcc, the situation of page writing is transmitted to the collective detection read signal SENSEl. That is, if SENSEL is discharged from Vcc to Vss, at least one write node VRYl is V
ss is set, and the write operation is continued.
Then, when all the write nodes VRYl become Vcc and the collective detection read signal SENSEl is no longer discharged, the write operation ends.

In the description of the present embodiment, the write operation and the write confirmation read operation are repeated twice for the sub-arrays ARYl and ARYr, and SENSEL and SENSER are set to V.
Writing is finished when the discharge to ss is stopped.

Now, during the write operation and the write confirmation read operation in the sub-array ARYl as described above,
In the sub-array ARYr, these operations are also performed in parallel in time, with their phases being shifted. That is, the page load of the write data is performed by inputting / outputting the input / output buffers to the sense amplifier / data latch circuits LA1r to LAnr for the sub array ARYr even after the data is written to the sense amplifier / data latch circuits LA1l to LAnl for the sub array ARYl. Data is written via the input / output lines I / O and I / OB.

Then, as in the case of the sub-array ARYl, all the bit lines BL1r to BLnr of the sub-array ARYr are precharged (pre-charged) to an intermediate potential VH higher than Vcc.
Then, after the last nth sense amplifier / data latch circuit LAnl, LAnr is written with data, the bit line is discharged according to the data written in the sense amplifier / data latch circuit. The writing operation is sequentially performed. Subsequent confirmation read operations for the sub-array ARYr are the same as those for the sub-array ARYl.

As described above, according to this embodiment, the array of NAND cells is divided into two sub arrays ARYl and ARY.
In the first embodiment, by dividing into r and performing the write confirmation read operation or the erase confirmation read operation selectively in the other subarray while the write operation or the erase operation is selectively performed in one subarray. Similarly, the total writing and erasing time including the confirmation reading operation can be shortened.

The present invention is not limited to the above embodiments. In the embodiment, the example in which the memory cell array is divided into two has been described, but it may be divided into three or more. In this case, data writing or erasing may be simultaneously performed in all sub arrays, or data writing or erasing may be simultaneously performed in two sub arrays. In short, at least two sub-arrays should be programmed or erased at the same time, and one sub-array and the other sub-array should be shifted in timing between the write or erase operation and the write confirmation read operation or erase confirmation read operation.

The memory cell structure is not always FET.
The configuration is not limited to the MOS type, and any configuration that allows electrical rewriting may be used. Furthermore, when a plurality of memory cells are connected to form a memory cell unit, not only the NAND type but also the NOR type can be applied. In addition, various modifications can be made without departing from the scope of the present invention.

[0068]

As described above, according to the present invention, the memory cell array is divided into at least two, and in different sub-arrays, the write confirmation read operation or the erase confirmation read operation is performed in parallel in time with the write operation or the erase operation. At the same time, a non-volatile semiconductor memory device capable of high-speed writing and erasing can be obtained as a result.

Further, according to the present invention, rewriting of data (writing after erasing data) can be performed in a short time, and not only the function as SSF (solid state file) is sufficiently fulfilled. Pre-shipment test time is significantly reduced, leading to lower costs.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a nonvolatile semiconductor memory device according to a first embodiment.

FIG. 2 is a diagram for explaining a timing difference between a write operation and a write confirmation read operation in two sub arrays.

FIG. 3 is a view AA ′ of the nonvolatile semiconductor memory device of FIG.
Sectional view.

FIG. 4 is a sectional view showing a modified example of FIG.

FIG. 5 is a layout diagram of a NAND type memory cell array in the sub-array ARYl.

FIG. 6 is a layout diagram of a NAND type memory cell array in the sub-array ARYl.

FIG. 7 is a layout diagram of a NAND type memory cell array in the sub-array ARYl.

FIG. 8 is a layout diagram of a NAND type memory cell array in the sub array ARYr.

FIG. 9 is a layout diagram of a NAND type memory cell array in the sub-array ARYr.

FIG. 10 is a layout diagram of a NAND type memory cell array in the sub-array ARYr.

FIG. 11 is a circuit configuration diagram of a core part of a column system on the sub-array ARYl side.

FIG. 12 is a circuit configuration diagram of a row decoder section on the sub-array ARYr side.

FIG. 13 is a diagram showing the operation timing of the first half of the main node in the second embodiment.

FIG. 14 is a diagram showing the operation timing of the first half of the main node in the second embodiment.

FIG. 15 is a diagram showing the operation timing of the first half of the main node in the second embodiment.

FIG. 16 is a diagram showing operation timing of the latter half of the main node in the second embodiment.

FIG. 17 is a diagram showing operation timing of the latter half of the main node in the second embodiment.

FIG. 18 is a diagram showing operation timing of the latter half of the main node according to the second embodiment.

[Explanation of symbols]

M11l to Mmnl, M11r to Mmnr ... Memory cells BL1l to BLnl, BL1r to BLnr ... Bit lines WL1l to WLml, WL1r to WLmr ... Word lines WL11l to WLm8l, WL11r to WLm8r ... Word lines SGS1l to SGSml, SGSml, SGSml, SGSml, SGSml, SGR. Select gate lines SGD1l to SGDml, SGD1r to SGDmr ... Drain side select gate lines ARYl, ARYr ... Sub-arrays R / D1 to R / Dm ... Row decoder circuits LA1l to LAnl, LA1r to LAnr ... Sense amplifier / data latch circuit 10 ... N type Semiconductor substrate 11, 12 ... p-type well for sub-array 14 ... p-type well for peripheral circuit 15 ... n-type well for peripheral circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Fujio Masuoka 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Incorporated Toshiba Research and Development Center

Claims (5)

[Claims] 1. An array of non-volatile memory cells formed on the same chip is divided into a plurality of sections, and data writing or erasing is simultaneously performed by at least two of the divided plurality of sub-arrays, and data writing or erasing of an arbitrary sub-array is performed. A nonvolatile semiconductor memory device characterized in that the timing of writing or erasing data of another sub-array is shifted with respect to the timing of erasing. 2. An array of non-volatile memory cells formed on the same chip is divided into two, data writing or erasing is performed simultaneously in each of the divided sub-arrays, and data writing or erasing timing of one sub-array. As opposed to
A nonvolatile semiconductor memory device characterized in that the timing of data writing or erasing of the other sub-array is shifted. 3. A data write or erase operation comprises a data write operation or an erase operation and a plurality of subsequent write confirmation read operations or erase confirmation read operations, and the data write operation or erase operation is performed on an arbitrary sub-array. Between,
3. The nonvolatile semiconductor memory device according to claim 1, wherein a write confirmation read operation or an erase confirmation read operation is performed in another sub-array. 4. The non-volatile memory according to claim 1, wherein a plurality of sub-arrays share a word line, and data writing or erasing is simultaneously performed with respect to memory cells connected to the same word line of different sub-arrays. Semiconductor memory device. 5. The non-volatile semiconductor memory cell forming the array is an electrically rewritable non-volatile memory cell, and a plurality of cells are connected in series to form a NAND cell. 3. The nonvolatile semiconductor memory device according to 1 or 2.