JPH0818059A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Abstract] [Objective] In an insulated gate semiconductor device in which a channel region is formed of a polycrystalline semiconductor mainly composed of silicon, the resistance of the source / drain region is increased by thinning the channel layer of the thin film transistor. Suppresses and enables improvement of characteristics. [Structure] A region into which nitrogen is introduced is provided in the vicinity of an interface between a channel layer, a gate insulating film, and an interlayer insulating film. Specifically, (1) 1E19 (1 × 10 ¹⁹ ) (pieces / cm3) in the vicinity of the interface with the insulating film in a part or the whole of the source / drain region.
It contains the above nitrogen (N). Or (2) sauce
1E1 is provided in the vicinity of the interface between the source / drain region of the insulating film which contacts the upper part or the lower part of the drain region.
9 (1 × 10 ¹⁹ ) (pieces / cm 3) or more of nitrogen (N) is contained. As a manufacturing method, a treatment in a nitrogen or a plasma atmosphere containing nitrogen is performed. Heat treatment at high temperature for a short time in an atmosphere containing nitrogen. A CVD method using nitrogen or a compound containing nitrogen. Nitrogen (N) ion implantation. Etc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a semiconductor device on an insulating amorphous material and its manufacturing method.

[0002]

2. Description of the Related Art In recent years, due to the need for large-scale, high-resolution liquid crystal display panels, three-dimensional ICs, etc., high performance is achieved on insulating amorphous substrates such as glass and quartz and insulating amorphous materials such as SiO2. There is a demand for a technique for forming a thin film transistor.

As such a semiconductor device using amorphous silicon or polycrystalline silicon as a device material, good results have been obtained in terms of variations in characteristics of each device and yield. In particular, the one using polycrystalline silicon as the element material has a relatively high movement due to the technique of melting and recrystallization by laser light and the technique of solid-phase growing amorphous silicon to form a polycrystalline silicon film of large grain size. A device having a certain degree can be manufactured relatively easily. Therefore, L
It has become possible to be applied as a switching element or a driving element of a CD or an image sensor.

[0004]

However, in order to increase the definition and capacity of liquid crystal panels and to apply them to SRAMs, elements having higher on / off ratios have been demanded. In the case of a thin film transistor, off-leakage is reduced by reducing the film thickness of the polycrystalline silicon layer that becomes the channel,
It is known that subthreshold swing can be improved. However, if the thickness of the polycrystalline silicon layer serving as the channel is simply reduced, the resistance of the source / drain regions is extremely increased and the on-current is reduced. As a result, it is difficult to obtain a high on / off ratio. Particularly when a Pch thin film transistor is to be formed, B (boron) used as an impurity easily diffuses into a silicon oxide film used as a gate insulating film or an interlayer insulating film, so that a film of a polycrystalline silicon layer to be a channel is formed. The thinner the sauce,
The concentration of impurities in the drain region is likely to drop extremely,
Such a phenomenon is likely to occur.

When the application of the thin film transistor to SRAM is considered, the current consumption and stability of the memory cell largely depend on the characteristics of the thin film transistor used. The current consumption in the memory cell portion is substantially defined by the leak current of the thin film transistor, and the stability of the memory cell on the low voltage side is defined by the on-current and subthreshold characteristics of the thin film transistor. Therefore, the improvement of the characteristics of the thin film transistor is very effective in reducing the voltage and power consumption of the SRAM. In order to improve those characteristics of the thin film transistor, thinning the polycrystalline silicon layer to be the channel region is a very effective means.

On the other hand, when a thin film transistor is used in an SRAM cell, the drain region of the thin film transistor is rarely directly connected to the power supply wiring in each memory cell, and the source region is used as a part of the power supply wiring. It is often the case that each or every tens of cells are connected to the power supply wiring. Therefore, if the resistance of the source region is increased, a large series resistance is added to the power supply, and the stability of the memory cell is reduced. When an attempt is made to improve the characteristics of the thin film transistor by reducing the thickness of the layer that will be the channel region, the increase in the parasitic resistance of the source / drain that accompanies it becomes a particularly serious problem for the application to SRAM.

The object of the present invention is to solve the above problems.
This is to suppress an increase in parasitic resistance of the source / drain regions due to the thinning of the layer serving as the channel of the thin film transistor.

[0008]

In order to solve the above problems, the semiconductor device of the present invention comprises: (1) 1E19 at least in the vicinity of the interface with the insulating film in a part or the whole of the source / drain region. It is characterized by containing (1 × 10 ¹⁹ ) (pieces / cm 3) or more of nitrogen (N).

(2) 1E19 (1 × 1) at least in the vicinity of the interface between the source / drain region and the insulating film in contact with at least a part or the whole of the source / drain region above or below
It is characterized by containing nitrogen (N) of 0 ¹⁹ ) (pieces / cm 3) or more.

Further, according to the method of manufacturing a semiconductor device of the present invention, (3) after forming a gate insulating film or an insulating film as a base, after performing a treatment in nitrogen or a plasma atmosphere containing nitrogen, A feature is that a polycrystalline semiconductor layer to be a channel region is formed.

(4) After forming a gate insulating film or an insulating film to be a base, after performing a heat treatment at a high temperature for a short time in an atmosphere containing at least nitrogen, a polycrystalline semiconductor layer to be a channel region is formed. Is characterized by.

(5) The gate insulating film, the underlying insulating film, or the insulating film covering the upper part is formed by the CVD method using nitrogen or a compound containing nitrogen as a part of the raw material gas. And

(6) The method is characterized in that after the polycrystalline semiconductor layer to be the channel region is formed, the treatment is performed in nitrogen or a plasma atmosphere containing nitrogen.

(7) The method is characterized in that after the polycrystalline semiconductor layer to be the channel region is formed, heat treatment is performed at a high temperature for a short time in an atmosphere containing at least nitrogen.

(8) The method is characterized by including a step of implanting nitrogen (N) ions at least in the vicinity of the source / drain regions.

[0016]

FIG. 1 is a process sectional view showing an example of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 1A shows a gate electrode 102 of a thin film transistor and a gate insulating film 10 on an insulating substrate 101.
3 shows a state in which 3 is formed.

As the insulating substrate 101, a substrate obtained by surface-oxidizing a silicon substrate and then forming a silicon oxide layer by the atmospheric pressure CVD method on the surface is used. In the case of application to SRAM or the like, the same process is used after forming an interlayer insulating film on a silicon substrate on which MOS transistors are formed.

The polycrystalline silicon layer forming the gate electrode 102 has a film thickness of about 1000Å and is formed by low pressure CVD using silane (SiH4) as a source gas.
The substrate temperature during film formation is 540 ° C., and the film is in an amorphous state immediately after film formation. After introducing N or P or As, which is an N-type impurity, by implanting ions into this, heat treatment is performed at 800 ° C. for 20 minutes to polycrystallize. By using such a process, it is possible to obtain a polycrystalline silicon film having a flat surface morphology, and the gate insulating film 10 formed on the polycrystalline silicon film.
3 contributes to the improvement of the breakdown voltage and the improvement of the on-current of the manufactured thin film transistor.

After patterning the polycrystalline silicon layer by photolithography and etching,
The gate insulating film 103 is formed. Gate insulating film 103
Is a film having a film thickness of about 200 liters and formed at a substrate temperature of 520 ° C. by a low pressure CVD method using silane and oxygen (O 2) as source gases.

After forming the gate insulating film 103, a process for introducing nitrogen (N) into the surface is performed. For this treatment, a parallel plate type plasma treatment apparatus was used, and an internal pressure of 0.1 Torr. Plasma processing is performed at a substrate temperature of 300 ° C. for 5 minutes. By this treatment, a region containing nitrogen can be formed on the surface of the gate insulating film 103.

This treatment is not limited to a nitrogen atmosphere, but a nitrous oxide atmosphere or an atmosphere containing an appropriate amount of nitrogen (N),
For example, nitrogen (N2) in an atmosphere of oxygen or Ar, He, etc.
Alternatively, even when the treatment is performed in an atmosphere in which nitrous oxide (N2O) is added by several% to 20%, the same effect can be obtained by selecting an appropriate processing condition such as power and substrate temperature.

It is also possible to use a lamp annealing treatment in an atmosphere containing an appropriate amount of nitrogen (N) for this treatment. For example, 10% in an atmosphere of Ar, He, etc.
~ 900 ° C in an atmosphere containing tens of% of nitrous oxide,
Almost the same effect is obtained by performing the lamp annealing for 10 seconds.

FIG. 1 (b) shows a process of forming a source / drain region by ion implantation after forming a polycrystalline silicon layer 105 to be a channel region on the gate insulating film. is there.

First, a polycrystalline silicon film 105 to be a channel region is formed on the gate insulating film 103. The polycrystalline silicon layer 105 has a film thickness of about 200 Å and is made of disilane (S
i2H6) is used as a source gas to form a film by a low pressure CVD method. The substrate temperature during film formation is 480 ° C., and the film is in an amorphous state immediately after film formation. Then, in a nitrogen atmosphere at 600 ° C,
A polycrystalline silicon film having a large grain size of about 1 μm is obtained by polycrystallizing by performing heat treatment for 8 hours + 650 ° C., 2 hours + 700 ° C., and 1 hour. After this step, ion implantation for adjusting the threshold voltage Vth of the manufactured thin film transistor may be performed.

Next, a resist mask is formed on the region to be the channel by photolithography. The pattern of this resist mask is provided so as to have a drain side offset with respect to the gate electrode 102, and an offset is formed on the drain side of the thin film transistor to be manufactured. After that, BF2 ion was 8E14 at 25 keV.
Implanting (pieces / cm 2) forms source / drain regions.

FIG. 1C shows the source of the thin film transistor.
It shows a state in which a drain region is formed.

First, after removing the resist for performing ion implantation, a process for introducing nitrogen into the surface is performed again. For this treatment, plasma treatment in a nitrogen atmosphere under the same conditions as the treatment performed after forming the gate insulating film 103, or lamp annealing treatment in an atmosphere containing nitrogen is used.

Next, the interlayer insulating film 108 is formed. The interlayer insulating film 108 has a film thickness of about 1000Å and is formed by a low pressure CVD method using silane and oxygen as source gases. After forming the interlayer insulating film 108, heat treatment is performed at 850 ° C. for 20 minutes to activate the impurities introduced into the source / drain regions by ion implantation.

FIG. 1D shows a completed state of the thin film transistor, in which the contact hole 110 is formed in the interlayer insulating film 108 by photolithography and etching processes.
After forming the wiring layer, the wiring layer 109 is formed.

For the wiring layer 109, tungsten (W) and aluminum (Al) formed by sputtering are used. Since the channel polycrystalline silicon layer 105 is thin, it is difficult to form a contact with aluminum directly. For this reason, a tungsten (W) layer having a film thickness of 200 Å is provided as a barrier metal at the interface between the polycrystalline silicon layer 105 and the wiring layer 109.

By forming a pattern on the wiring layer 109 by photolithography and etching, the step of forming a thin film transistor is completed.

The thickness of the polycrystalline silicon 105 is set to 300 Å or less without performing the step of introducing nitrogen into the surface of the gate insulating film 103 and the step of introducing nitrogen into the surface of the polycrystalline silicon layer 105 as described above. In this case, since the impurities introduced into the source / drain regions by ion implantation diffuse into the gate insulating film and the interlayer insulating film during the heat treatment for activation, it becomes difficult to keep the impurity concentration in the source / drain regions high. . Therefore, the resistance of the source / drain regions increases, and it becomes difficult to improve the characteristics of the thin film transistor.

However, when a layer containing nitrogen is provided in the vicinity of the boundary between the polycrystalline silicon layer 105 and the gate insulating film 103 and in the vicinity of the interlayer insulating film 108 by using the above-described process, impurities such as boron It becomes possible to suppress diffusion. Therefore, diffusion of impurities introduced into the source / drain regions into the gate insulating film 103 and the interlayer insulating film 108 is suppressed, and even when the polycrystalline silicon layer 105 is thinned to 200 Å as described above, It was possible to suppress an extreme increase in resistance. For this reason,
It was possible to produce a thin film transistor with small off-leakage without causing a decrease in on-current. It has been confirmed that such improvement of the performance of the thin film transistor by thinning the polycrystalline silicon layer 105 is extremely effective up to about 100 Å.

The effect of suppressing the diffusion of impurities as described above is
It is recognized under the condition that the peak value of nitrogen content by SIMS analysis near the interface is 1E19 (1 × 10 ¹⁹ ) (pieces / cm 3) or more. Particularly, when the peak value of nitrogen content is 1E20 (1 × 10 ²⁰ ) (pieces / cm3) or more and the width of the region into which nitrogen is introduced is 20 to 40 Å or more, a high effect is obtained. Has been obtained.

FIG. 2 is a process sectional view showing another example of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2A shows a polycrystalline silicon layer 2 which becomes a channel region of a thin film transistor on an insulating substrate 201.
05 and the gate insulating film 203 are formed.

The insulating substrate 201 is the same as that of the embodiment shown in FIG.

First, a polycrystalline silicon layer 205 is formed on the insulating substrate 201. The polycrystalline silicon layer 205 has a film thickness of about 200Å, and uses disilane as a source gas for low pressure CVD.
The film is formed by the method. At the substrate temperature of 500 ° C during film formation,
Immediately after the film formation, it is in an amorphous state. After the film formation, heat treatment is performed at 650 ° C. for 3 hours to form a polycrystalline silicon film having a large grain size.

After forming a pattern on the polycrystalline silicon layer 205 by a photolithography and etching process, a gate insulating film 203 is formed. Gate insulating film 20
No. 3 has a film thickness of about 200 liters and is formed at a substrate temperature of 480 ° C. by a low pressure CVD method using silane and oxygen as source gases.

FIG. 2B shows a state in which the gate electrode 202 of the thin film transistor is formed.

First, a polycrystalline silicon layer for forming the gate electrode 202 is formed. This polycrystalline silicon layer is formed by a low pressure CVD method with a film thickness of about 1500 Å using disilane as a source gas. Substrate temperature during film formation is 5
Phosphine (PH3) is added to the source gas at 00 ° C. to perform in situ doping. Subsequently, a pattern is formed on the polycrystalline silicon film by photolithography and etching steps.

FIG. 2C shows a step of performing ion implantation for forming source / drain regions of the thin film transistor.

First, the side wall 206 is formed.
The side wall 206 is formed by depositing a silicon oxide film of about 3000 Å by a CVD method using silane and oxygen as source gases and then performing etch back.
By providing such a side wall, an offset is formed between the source and the gate of the thin film transistor to be manufactured. The offset on the drain side can be formed not only by using such a sidewall but also by using a resist mask.

After forming the side wall 206, nitrogen (N) ions are applied at 25 keV for 1E14 (pieces / cm2),
BF2 ions are implanted at 25 keV for 8E14 (pieces / cm2) to form a source / drain region. The source / drain regions are formed in self-alignment with the gate electrode 202.

FIG. 2D shows a completed state of the thin film transistor.

After ion implantation for forming the source / drain regions, plasma treatment is performed in a nitrogen atmosphere to form an interlayer insulating film 208.

The plasma treatment in a nitrogen atmosphere is the same as the treatment in the embodiment shown in FIG.

The interlayer insulating film 208 has a thickness of about 1500Å
The substrate temperature is 480 ° C. by the low pressure CVD method using silane and oxygen as source gases. After forming the interlayer insulating film, heat treatment is performed at 850 ° C. for 20 minutes to activate the impurities introduced into the source / drain regions.

After the contact hole 210 is formed in the interlayer insulating film 208 by the photolithography and etching process, the wiring layer 209 is formed. For the wiring layer 209, similarly to the embodiment shown in FIG. 1, tungsten and aluminum formed by the sputtering method are used. Subsequently, the pattern of the wiring layer 209 is formed by photolithography and etching steps, thereby completing the step of forming the thin film transistor.

In the above-described embodiment, the source / drain regions and the layer into which nitrogen is introduced to prevent the impurities introduced into the source / drain regions from diffusing in the process of self-aligning with the gate electrode 202 are formed. are doing. Therefore, the same effect as that shown in FIG. 1 can be obtained in which the resistance increase in the source / drain region is suppressed, and nitrogen is not introduced into the silicon oxide film around the channel region. It is possible to suppress variations in characteristics such as threshold voltage.

Even in the case of the structure in which the gate electrode is provided on the substrate side of the channel polycrystalline silicon layer as in the embodiment shown in FIG. 1, nitrogen ions are implanted at the time of ion implantation for forming the source / drain regions. By performing the above, it is possible to introduce nitrogen only into the vicinity of the source / drain regions, and it is considered that the same effect can be obtained.

FIG. 3 is a process sectional view showing an example of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3A shows a gate electrode 302 of a thin film transistor and a gate insulating film 30 on an insulating substrate 301.
3 shows a state in which 3 is formed.

As the insulating substrate 301, a substrate obtained by surface-oxidizing a silicon substrate and then forming a silicon oxide film on the surface by atmospheric pressure CVD is used. P on a part of the substrate
A region in which the type impurities are diffused is provided.

The polycrystalline silicon layer forming the gate electrode 102 has a film thickness of about 1000Å and is formed at a substrate temperature of 580 ° C. by low pressure CVD using silane (SiH 4) as a source gas. By implanting ions into this, N-type impurities such as P or As are introduced.

A pattern is formed on the polycrystalline silicon layer by photolithography and etching. Here, in addition to the pattern of the gate electrode 302, a pattern is formed in a region which will be a drain of the thin film transistor.

Next, a gate insulating film 303 is formed. The gate insulating film 303 has a film thickness of about 200Å and is formed at a substrate temperature of 780 ° C. by a low pressure CVD method using silane and nitrous oxide as source gases.

FIG. 1B shows a process of forming a source / drain region by ion implantation after forming a polycrystalline silicon layer 305 to be a channel region on the gate insulating film. is there.

First, after forming the gate insulating film 303, through holes 304 are formed by photolithography and etching steps in a part of regions to be the source and drain of the manufactured thin film transistor.

Next, a polycrystalline silicon film 305 to be a channel region is formed. The polycrystalline silicon layer 305 has a film thickness of about 200Å and is formed by a low pressure CVD method using silane as a source gas. Substrate temperature during film formation is 540 ° C
Thus, it is in an amorphous state immediately after the film formation. Then the cap layer 3
06 is formed. The thickness of the cap layer 306 is 200Å
Then, the film is formed at a substrate temperature of 480 ° C. by a low pressure CVD method using silane and oxygen as source gases.

After forming a resist mask by photolithography on the region to be a channel, BF2
Ions are implanted at 40 keV for 8E14 (pieces / cm2) to form source / drain regions.

FIG. 3C shows the source of the thin film transistor.
It shows a state in which a drain region is formed.

First, after removing the resist mask, the cap layer 306 is removed by etching with hydrofluoric acid.
Then, the surface is oxidized in an oxygen atmosphere containing 20% nitrous oxide. Substrate temperature during oxidation is 8
The treatment is performed at 50 ° C. for 15 minutes.

Next, an interlayer insulating film 308 is formed.
The interlayer insulating film 308 has a film thickness of about 1000Å and is formed by a low pressure CVD method using silane and nitrous oxide as source gases. The substrate temperature during film formation is 780 ° C.

FIG. 3D shows a completed state of the thin film transistor.

After forming a contact hole 310 in the interlayer insulating film 308 by a photolithography and etching process, a wiring layer 309 is formed.

For the wiring layer 309, titanium (Ti), titanium nitride (TiN) and aluminum formed by the sputtering method are used. Polycrystalline silicon layer 305 and wiring layer 309
The contact is made with a structure in which the source region of the thin film transistor is connected to the region in the substrate where the P-type impurity is diffused, and the drain side is connected via a pattern formed of the same polycrystalline silicon layer as the gate electrode 302. By using such a structure, it is possible to stably obtain a low contact resistance even when the polycrystalline silicon layer 305 is made thinner.

In the embodiment described above, the gate insulating film 303
Since nitrous oxide is used during the film formation, the gate oxide film contains several% of nitrogen. Further, since nitrous oxide is added when the polycrystalline silicon layer 305 is oxidized,
A region containing 0.1 to several% of nitrogen also exists at the boundary between the polycrystalline silicon layer 305 and the interlayer insulating film 308. As described above, since the polycrystalline silicon layer 305 is sandwiched between layers containing nitrogen of about 0.1 to several percent, diffusion of impurities introduced into the source / drain regions into the gate insulating film 303 and the interlayer insulating film 308. Is suppressed, and even if the polycrystalline silicon layer 305 is thinned to 200 Å, it is possible to suppress an extreme increase in resistance of the source / drain regions.

FIG. 4 is a cell pattern diagram and an equivalent circuit diagram showing an example of the case where the semiconductor device according to the embodiment of the present invention is used as a load in an SRAM cell.

FIG. 4A shows the pattern of the MOS transistor formed in the substrate. The upward-sloping shaded area represents the active region in the substrate, and the upward-sloping hatched area represents the MOS.
The pattern of polycide used as a gate of a transistor is shown. Reference numerals 401 and 402 denote driver transistors of memory cells, and 403 and 404 transfer transistors.

FIG. 4B shows a pattern of the load thin film transistor stacked on FIG. 4A, in which the upward-sloping hatched portion indicates the gate electrode layer pattern of the thin-film transistor and the upward-sloping diagonal portion. Shows a pattern of a polycrystalline silicon layer which becomes a channel of a thin film transistor.

FIG. 4C shows an equivalent circuit of the memory cell shown in FIGS. 4A and 4B.
The elements 11 to 414 correspond to the elements 411 to 414 in FIG.
415 and 416 are 415 to 416 in FIG.
Is equivalent to Further, 417 is a power supply line, 4
Reference numeral 18 indicates a ground line.

Reference numerals 415 and 416 denote P-type thin film transistors for load, to which the semiconductor device of the present invention is applied. These thin film transistors are formed using the same steps as those of the embodiment shown in FIG. 3, and are composed of a polycrystalline silicon layer 405 and a gate electrode 402. In this case, since the MOS transistor is formed on the substrate, after forming the thin film transistor,
It is necessary to planarize before forming the wiring layer. For this reason, the structure in which the BPSG layer is laminated on the interlayer insulating film shown in FIG. 3 is used, and heat treatment is performed at 850 ° C. for 30 minutes to perform planarization.

When using such a memory cell configuration,
The power supply line 417 in the memory cell is similar to the source / drain region of the thin film transistor in the polycrystalline silicon layer 40.
5 is formed. The power supply lines in these memory cells are connected to a wiring having a lower resistance such as metal or polycide every several or several tens of cells.

In the case where the polycrystalline silicon layer 405 is simply thinned in order to improve the characteristics of the thin film transistor, 3
The increase in the resistance of the portion of the power supply line 417 in the memory cell from the area of 00 Å or less becomes a problem. Since the heat treatment for flattening the interlayer film is required as described above, such a phenomenon that the resistance of the power supply line increases cannot be avoided. However, by using the thin film transistor as described in FIGS. 1 to 3, it is possible to avoid the increase in the resistance of the power supply line, and it is possible to improve the performance of the thin film transistor by thinning the polycrystalline silicon layer 405. Become. For this reason, it has become possible to manufacture an SRAM with lower power consumption and capable of operating at lower voltage.

[0077]

As described above, according to the present invention, it is possible to suppress an increase in the parasitic resistance of the source / drain regions due to the thinning of the layer serving as the channel of the thin film transistor. For this reason, it has become possible to improve the performance of the thin film transistor by thinning the channel layer. Further, by applying such a thin film transistor to the load of the cell of the SRAM, it has become possible to manufacture an SRAM that can operate with lower power consumption and lower voltage.

[Brief description of drawings]

FIG. 1 is a process sectional view showing an example of a manufacturing process of a semiconductor device in an example of the present invention.

FIG. 2 is a process sectional view showing another example of the manufacturing process of the semiconductor device according to the embodiment of the invention.

FIG. 3 is a process sectional view showing another example of the manufacturing process of the semiconductor device according to the embodiment of the invention.

FIG. 4 is a diagram showing a semiconductor device according to an embodiment of the present invention as an SRAM
FIG. 7 is a pattern diagram showing another example of the case where the load is applied to the cell of FIG.

[Explanation of symbols]

101, 201, 301 ... Insulating substrate 102, 202, 302, 403 ... Gate electrode 103, 203, 303 ... Gate insulating film 304 ... Through hole 105, 205, 305 ... Polycrystal Silicon layer 206 ・ ・ ・ Sidewall 306 ・ ・ ・ Cap layer 107, 307 ・ ・ ・ Resist 108, 208, 308 ・ ・ ・ Interlayer insulating film 109, 209, 309 ・ ・ ・ Wiring layer 110, 210, 310 ・ ・ ・Contact holes 411, 412 ... Transfer transistors 413, 414 ... Driver transistors 415, 416 ... Thin film transistors 417 ... Power supply line 418 ... Ground line

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location H01L 27/11 21/336 H01L 27/10 381 9056-4M 29/78 311 Y

Claims (8)

[Claims] 1. An insulated gate semiconductor device having a channel region formed of a polycrystalline semiconductor mainly containing silicon,
1E19 (1 × 10 ¹⁹ ) (pieces / cm) at least in the vicinity of the interface with the insulating film in a part or the whole of the source / drain region
3) A semiconductor device containing the above nitrogen (N). 2. An insulated gate semiconductor device having a channel region formed of a polycrystalline semiconductor containing silicon as a main component,
Nitrogen (N) of 1E19 (1 × 10 ¹⁹ ) (pieces / cm3) or more is provided at least in the vicinity of the interface between the source / drain region and the insulating film in contact with at least a part or the whole of the source / drain region. A semiconductor device characterized by containing. 3. A method of manufacturing an insulated gate semiconductor device, wherein a channel region is formed of a polycrystalline semiconductor mainly composed of silicon, wherein a gate insulating film of the semiconductor device or an insulating film which is a base of the semiconductor device. And forming a polycrystalline semiconductor layer to be a channel region after performing a treatment in nitrogen or a plasma atmosphere containing nitrogen. 4. A method for manufacturing an insulated gate semiconductor device, wherein a channel region is formed of a polycrystalline semiconductor mainly containing silicon, after forming a gate insulating film or an insulating film as a base of the semiconductor device, A method of manufacturing a semiconductor device, which comprises performing a heat treatment at a high temperature for a short time in an atmosphere containing at least nitrogen and then forming a polycrystalline semiconductor layer to be a channel region. 5. A method of manufacturing an insulated gate semiconductor device, wherein a channel region is formed of a polycrystalline semiconductor mainly composed of silicon, wherein a gate insulating film, an insulating film serving as a base, or an insulating film covering an upper portion is formed. A method for manufacturing a semiconductor device, which is formed by a CVD method using nitrogen or a compound containing nitrogen as a part of a raw material gas. 6. A method of manufacturing an insulated gate semiconductor device in which a channel region is formed of a polycrystalline semiconductor containing silicon as a main component. A method for manufacturing a semiconductor device, which comprises performing the treatment in a plasma atmosphere containing the semiconductor device. 7. A method for manufacturing an insulated gate semiconductor device in which a channel region is formed of a polycrystalline semiconductor mainly containing silicon, and after the polycrystalline semiconductor layer to be the channel region is formed, at least nitrogen is contained. A method of manufacturing a semiconductor device, comprising performing heat treatment at a high temperature for a short time in an atmosphere. 8. A method for manufacturing an insulated gate type semiconductor device in which a channel region is formed of a polycrystalline semiconductor mainly composed of silicon, including a step of implanting nitrogen (N) ions at least in the vicinity of the source / drain regions. A method for manufacturing a semiconductor device, comprising: