JPH08181580A - Clock changeover circuit - Google Patents

Abstract

PURPOSE: To eliminate an output clock interrupt state for a discrimination period by adding a resonance section and a clock generating section to an input clock and keeping the clock longer than a time required for abnormity discrimination to the input clock. CONSTITUTION: A resonance signal 105 obtained by resonating a 1-system input clock signal at a resonance section 3 is converted into a clock signal by a clock generating section 5 to obtain a resonance clock signal 107 for holding four periods of the 1 system input clock signal. Since a 2-system input clock signal is normally received, a 2-system input monitor section 2 provides an output of a 2-system input state signal 104 as a normal state and a resonance clock signal 108 is obtained via the resonance section 4 and the clock generating section 6. Furthermore, a clock selection section 9 outputs an output clock signal 111 resulting from the signal 108 in place of the signal 111 resulting from the signal 107 based on the selection signal 110. Then the clock signal is held longer than the time required for abnormity discrimination of input monitor sections 1, 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock switching circuit, and more particularly to a clock switching circuit for determining a normal clock signal by deciding an input disconnection state of each clock signal of an active system and a standby system. .

[0002]

2. Description of the Related Art FIG. 3 shows an example of a conventional clock switching circuit of this type. In FIG. 3, the 1-system input monitoring unit 1 is
The input state of the system input clock signal 101 is detected as an input abnormality (input disconnection) by the absence of rising or falling of the clock within the arbitrarily set time T (time longer than one cycle of the input clock frequency). The detection signal 103 is generated. The 2-system input monitoring unit 2 also detects the input disconnection state of the 2-system input clock signal 102 and generates the detection signal 104.

These input monitoring units 1 and 2 have an input clock 1
It is realized by a retriggerable (retriggerable) monostable multivibrator circuit triggered by each rising or falling of 01 and 102, and the above-mentioned time T is determined by the time constant of this monostable multivibrator circuit.

The NOR circuit 7 generates a timing signal 109 for determining the switching timing in the clock selecting section 9 from the 1-system clock 101 and the 2-system clock 102, and the selection determining section 8 is based on the detection signals 103 and 104. The selection signal 110 is generated in synchronization with the switching timing signal 109.

The clock selection unit 9 switches between one of the 1-system clock signal 101 and the 2-system clock signal in synchronization with the selection signal 110 and derives the output clock signal 111.

FIG. 4 shows an example of waveforms of signals at various parts of the circuit of FIG. 3, in which the 1-system clock signal 101 currently selected is selected.
When the input state of is abnormal and is disconnected, the detection signal 103 generated from the 1-system input monitoring unit 1 after a predetermined time T has elapsed.
In response to, the normal clock signal 102 is switched to this normal clock signal 102 at a timing (NOR output) 109 synchronized with the trailing edge of the normal clock signal 102 immediately thereafter.

In the circuit of FIG. 3, the input clock signal is directly switched and output in the clock selection section 9, so at the time of clock switching, at least the time T (the time constant of the input monitoring sections 1 and 2 is set to the time constant). During the period (corresponding to the above), the state where there is no output clock occurs.

Therefore, Japanese Patent Laid-Open No. 63-287206 discloses the circuits shown in FIGS. First, referring to the circuit of FIG. 5, the active system and standby system clock signals A and B are input from the input terminals 101 and 102, respectively, and the input monitoring circuits 1 and 2 receive the active system and standby system clock signals A and B, respectively. The presence or absence of disconnection is monitored. The input monitoring circuits 1 and 2 are composed of, for example, RC monostable multivibrators, and when a disconnection of a time width corresponding to a time constant set by a resistor and a capacitor is detected, disconnection detection signals C and D are detected.
Respectively. In this example, the disconnection detection signals C and D are low level signals when disconnection is detected.

The disconnection detection signals C and D are input to the switching signal generating circuit 8 and the switching signal E is generated according to a certain algorithm. In this example, by using the inverter 81 and the NAND gate 82, the switching signal E is set to the low level only when the active system clock signal A is disconnected and the standby system clock signal B is not detected. There is.

On the other hand, the active system clock signal A and the standby system clock signal B are input to the selection circuit 9, and the active system is selected when the selection signal E is at high level, and the standby system is selected when the selection signal E is at low level. The clock signal F is sent to the LC resonance circuit 14.

Since the LC resonance circuit 14 is tuned to the frequency fo of the clock signal F, it is excited by the clock signal F and outputs the sine wave signal G of frequency fo. The sine wave signal G is sent to the SIN / TTL conversion circuit 15 by the TTL.
Regenerated and converted into the level clock signal H, and output terminal 11
It is sent from 1.

Next, the active clock signal A is cut off,
The operation when switching to the standby system will be described. However, here, it is assumed that the active system clock signal A and the standby system clock signal B have the same phase so that the problems described later do not occur.

FIG. 6 shows a waveform diagram of the signals A to H of each part of the circuit when the system switching occurs. Assuming that the input monitoring circuit 1 detects the disconnection of the input clock signal by the input disconnection of 5 time slots, the output E of the switching signal generation circuit 8 also becomes low level after the time slot as shown in FIG. The clock signal A is switched to the standby system clock signal B five time slots after the disconnection of the clock signal A, and the selection circuit 9 outputs the clock signal F which is disconnected for five time slots. To compensate for these five time slots,
The clock signal F is input to the LC resonance circuit 14.

Since the LC resonance circuit 14 is tuned to the frequency fo of the clock signal F, even if the clock signal F is interrupted for 5 time slots, the amplitude is gradually attenuated as shown in FIG. , The sine wave signal G having the frequency fo is continuously output, and the clock signal F is input again after 5 time slots, the amplitude of the sine wave signal G is restored to the original value. Therefore, unless the sine wave signal G disappears due to attenuation during the disconnection period of the clock signal F, the sine wave signal G is subjected to level conversion by the clock reproduction circuit 15 to reproduce the continuous output clock signal H. You can

The above is the explanation of the operation when the phases of the active clock signal A and the standby clock signal B are the same, but there is a phase difference of π between the active and standby clock signals A and B. In some cases LC after 5 time slots interruption
Since the clock signal F input to the resonance circuit 14 has a phase inversion with respect to the clock signal A input before switching, the sine wave signal G before switching is attenuated and the sine wave signal G before switching is attenuated. To generate a sine wave signal G with the phase reversed. Therefore, the sine wave signal G is attenuated to a level of zero after switching, and then a sine wave signal whose phase is newly inverted is excited by the clock signal after switching.

Therefore, when a phase difference (π) occurs between the active system clock signal A and the standby system clock signal B, the sine wave signal G is attenuated by the switched clock signal, and the pulse is lost before and after the switching. Becomes

Therefore, in this publication, a circuit as shown in FIG. 7 is proposed. 7, the same parts as those in FIG. 5 are designated by the same reference numerals, and frequency multiplication circuits 16 and 17 for doubling the frequencies f0 of the active system clock signal A and the standby system clock signal B respectively are provided, and these output C, D is selected by the clock selector 9 and this selected output F is set to 2fo
Is input to the resonance circuit 11 tuned to.

Then, the resonance output G is reproduced as a two-clock signal H by the first clock reproduction circuit 12, and the frequency-divided circuit 13 divides it by two to reproduce a clock signal I having a frequency fo. The clock signal I is input to the second resonance circuit 14 that is tuned to fo, the resonance output J is input to the second clock regenerating circuit 15, and the desired clock signal K is obtained from the output terminal 111. .

The phase difference between the clock signals of the active system and the standby system obtained by frequency multiplication by the frequency multiplication circuits 16 and 17 is in the vicinity of π, and the first clock signal reproduction circuit 12
From the above, a disconnection occurs for several time slocks (several cycles of the clock pulse) before and after the system switching. However, since this clock signal is divided by the frequency dividing circuit 13, the width of this disconnection becomes small and therefore By inputting the clock pulse after the round to the second resonance circuit 14 and reproducing the pulse by the second clock reproducing circuit 15, it is possible to obtain a continuous clock pulse without pulse omission.

[0020]

In the conventional circuit shown in FIG. 7, it is necessary to provide the frequency multiplying circuits 16 and 17 in the active system and the standby system, respectively, and the output of the clock selecting section 9 is 2fo and fo. Two resonance circuits having different resonance frequencies, and further the first and second clock recovery circuits 1
There is a problem that it is necessary to provide Nos. 2 and 15 and the circuit configuration becomes complicated to reduce the size and cost.

Further, in the output of the clock selection unit 9,
Since the resonance circuit is commonly provided in the active system and the standby system, the monitoring time constants of the input monitoring units 1 and 2 need to be set to the same, and the clock signals A and B of the active system and the standby system are set.
If the phase difference between the input monitoring units 1 and 2 is large, the time constant must be adjusted according to the phase difference to detect the disconnection of the input monitoring units 1 and 2, but the resonance circuit 11 is common. In addition, since the time constants cannot be adjusted independently and the Q indicating the sharpness of the resonance of the resonance circuit 11 is naturally common to the active system and the standby system, this resonance The number of resonances of the circuit is the same in both systems, and there is a drawback that a clock failure occurs due to the phase difference between the two system clocks and it is impossible to prevent a complete clock failure.

An object of the present invention is to provide a clock switching circuit having an extremely simple structure in which the characteristics of the circuit can be adjusted according to the phase states of the clock signals of the active system and the standby system and the clock is not interrupted. Is.

[0023]

A clock switching circuit according to the present invention generates a disconnection detection signal when each of the first system clock signal and the second system clock signal is not detected within a predetermined time. Second disconnection detecting means, first and second resonating means, each of which receives the first system clock signal and the second system clock signal as input, and sustains a resonance output longer than the predetermined time, respectively, and the first and second resonance circuits. First and second resonance clock generation means for respectively generating first and second resonance clock signals from each resonance output of the means, and the first and second resonance clock generation means according to the detection signals from the first and second disconnection detection means It is characterized in that it includes a selecting means for selectively switching and outputting a normal resonance clock signal among the second system resonance clock signals.

[0024]

A resonance circuit is provided independently for each of the input clock signals of the active system and the standby system, the clock is regenerated using the output of each resonance circuit, and the regenerated clock signal is selected by the clock selection unit. It is configured so as to be derived.
As a result, the Q of each resonance circuit can be adjusted and set independently, and as a result, the time constant of the input monitoring unit can also be set to each Q of these resonance circuits.
Can be set independently according to.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention, and the same portions as those in FIG. 3 are designated by the same reference numerals. The 1-system (active system) input monitoring unit 1 receives the 1-system clock signal 101 that is input.
When the rising edge or the falling edge of does not exist within an arbitrarily set time, an input abnormality is notified by the 1-system input state signal 103. The 2-system input monitoring unit 2 notifies the input abnormality by the 2-system input state signal 104 when the rising or falling of the input 2-system clock signal 102 does not exist within the time set arbitrarily. These input monitoring units 1 and 2 have the same retriggerable monostable multivibrator configuration as in the example shown in FIG.

The resonance units 3 and 4 output a 1-system resonance signal 105 and a 2-system resonance signal 106 that hold a clock for an arbitrarily set time used for abnormality determination. The clock generators 5 and 6 output the resonance clock signals 107 and 108 from the resonance signals 105 and 106, respectively.

The NOR circuit 7 uses the 1-system resonance clock signal 10
From the 7 and 2 system resonance clock signals 108, the switching timing signal 109 which is the timing when both system clock signals become low level is output. The selection determination unit 8 determines from the 1-system input state signal 103 and the 2-system input state signal 104 that
When the input clock selected as the output clock is in an abnormal state, the selection signal 110 for switching the system to the normal system is output in synchronization with the switching timing signal 109. The clock selection unit 9 selects the 1-system resonance clock signal 107 or the 2-system resonance clock signal 108 according to the selection signal 110 and outputs the output clock signal 111.

FIG. 2 is an operation explanatory diagram of the embodiment of the present invention, which is an operation example when the 1-system input clock signal 101 is in a disconnection state when the selection signal 110 selects the 1-system side. . The 1st system input monitoring unit 1 has 3 clock rising edges.
When there is no cycle or more, the 1-system input state signal 103 is changed to an abnormal state.

The resonance signal 105 obtained by resonating the 1-system input clock signal in the resonance unit 3 is converted into a clock signal in the clock generation unit 5 to convert the 1-system input clock signal into 4 clocks.
A resonance clock signal 107 holding a clock for a period is obtained. Since the system 2 input clock signal is normally input, the system 2 input monitoring unit 2 outputs the system 2 input state signal 104 as a normal state, and the resonance unit 4 and the clock generation unit 6
The resonance clock signal 108 is obtained via

The NOR circuit 7 outputs a switching timing signal 109 for switching when the clocks of both systems are low when the phases of the clocks of the first system and the second system are different. The selection determination unit 8 switches the selection signal 110 in synchronization with the switching timing signal 109 so as to select the second system side because the selected first system state has changed to the abnormal state.
The clock selection unit 9 switches the output clock signal 111 from the 1-system resonance clock signal 107 to the 2-system resonance clock signal 108 according to the selection signal 110 and outputs it.

[0032]

As described above, according to the present invention, when the phases of the input clock signals of both systems are not coincident with each other, only one cycle immediately after switching causes an error within half a cycle in the clock cycle due to the phase difference. Although it occurs, by adding a resonance unit and a clock generation unit to the input clock and holding the clock longer than the time required for the abnormality determination of the input clock, there is an effect of eliminating the output clock disconnection state during the determination time.

Further, by having the resonance section and the clock generation section in each system, it is possible to set the abnormality determination time of the input monitoring section independently for each system. Further, since the frequency multiplication circuit is unnecessary, the configuration of the entire circuit is simplified, and the size and cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a signal waveform diagram of each part showing the operation of the block of FIG.

FIG. 3 is a diagram showing an example of a conventional clock switching circuit.

FIG. 4 is a signal waveform diagram of each part showing the operation of the circuit of FIG.

FIG. 5 is a diagram showing another example of a conventional clock switching circuit.

FIG. 6 is a signal waveform diagram of each part showing the operation of the circuit of FIG.

FIG. 7 is a diagram showing still another example of a conventional clock switching circuit.

[Explanation of symbols]

 1, 2 Input monitoring unit 3, 4 Resonance unit 5, 6 Clock generation unit 7 NOR circuit 8 Selection determination unit 9 Clock selection unit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H03K 5/19 L 17/00 R 9184-5K F 9184-5K

Claims (3)

[Claims] 1. A first and a second disconnection detecting means for respectively generating disconnection detection signals when each of the first system clock signal and the second system clock signal is not detected within a predetermined time, and the first system and First and second resonance means for sustaining resonance outputs longer than the predetermined time, respectively, using the second system clock signal as an input, and first to second resonance outputs of the first and second resonance means, respectively.
Of the first and second system resonance clock signals according to the detection signals from the first and second system resonance clock generation means and the first and second disconnection detection means, respectively. A clock switching circuit comprising: a selection unit that selectively outputs a normal resonance clock signal. 2. The selecting means, in response to the detection signal, means for determining a switching timing in synchronization with the normal resonance clock signal, and means for deriving the normal resonance clock signal in accordance with the switching timing. The clock switching circuit according to claim 1, further comprising: 3. A time constant for detecting disconnection of each of the first and second disconnection detecting means can be independently set, and Q indicating the sharpness of each resonance of the first and second resonance means is 3. The clock switching circuit according to claim 1 or 2, wherein each of them can be independently set.