JPH0818529A - Synchronous multiplexing communication device - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To provide a communication device with a multiplexing frame demultiplexing function, which corrects the timing offset of the multiplexing unit demultiplexing and the timing offset of the interleave demultiplexing and shortens the time required for establishing frame synchronization and channel synchronization. A multi-bit expansion of an input interleaved synchronous multiplexing frame signal 81 is performed by a S / P converter 83 under a demultiplexing clock 82, and data output via a latch 86 is converted into a data selector 813. To 816, the data selectors 813 to 816 are connected to the data selectors 813 to 816 according to the correction information output from the subsequent multiplexing unit demultiplexing timing deviation and the interleave demultiplexing timing deviation detection unit 821.
Switch the input of. As a result, the multiplexing unit separation timing deviation and the interleave demultiplexing timing deviation are corrected without changing the lengths and clocks of the separated and output frames, and the time required for establishing frame synchronization and channel synchronization is shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous multiplexing communication device for transmitting a signal in which a plurality of frames of the same format are interleaved and multiplexed.

[0002]

2. Description of the Related Art FIG. 5 shows a multiplexing method for interleaving multiple frames of the same format. In the figure, reference numeral 11 denotes a channel 1 (hereinafter abbreviated as # 1) frame data string in a plurality of frames of the same format.
Reference numeral 2 is a # 2 frame data sequence, 13 is a # 3 frame data sequence, and 14 is a #N (N is the number of channels to be interleaved multiplexed, hereinafter abbreviated as interleaved multiplexing number) frame data sequence. .

Reference numeral 15 is a multiplexing unit W indicating how many bits each frame data is interleaved and multiplexed, and 16 indicates that the frame data string from # 1 to #N is interleaved multiplexed. Reference numeral 17 is an interleaved multiplexed data sequence, 18 is #N frame data, 19 is # 1 frame data, and 1
Reference numeral 10 is frame data of # 2.

Reference numeral 111 denotes conversion from parallel to serial, reference numeral 112 denotes a serial signal to be transmitted, and 113
Is the data transmission direction, 114 is the W bit of #N frame data, and 115 is 1 of # 1 frame data.
The first bit, 116 is the second bit of the # 1 frame data, 117 is the W bit of the # 1 frame data, 118 is the first bit of the # 2 frame data, and 119 is the multiplexing of the transmission data. The width of 1 bit, which is a unit of conversion, is shown.

FIG. 6 shows a conventional SDH (Sync).
hornous Digital Hierarchy)
Using STM (Synchronous Trans
port module) to receive a serial data signal in which N frames are interleaved and multiplexed, and to separate 8-bit parallel data of STM-N, which is a multiplexing unit, a frame synchronization pattern detection unit and a multiplexing unit separation unit This is a basic configuration of a device in which and are separately configured to simplify the circuit.

In FIG. 6, 21 is the received STM-N.
The serial data signal, 22 is the received STM-N
Reference numeral 23 is a clock, 23 is an STM-N (N is greater than or equal to 4) clock that includes timing correction information when separating multiplexing units, and 24 is 8-bit parallel data conversion of received serial data. A serial / parallel converter (hereinafter abbreviated as S / P converter)
Is an 8-bit latch that latches the converted parallel data.

Reference numeral 26 is 8-bit parallel STM-N data which is a multiplexing unit, 27 is an 8 frequency divider, and 28
Is a clock that is phase-synchronized with 25, 29 is a part that detects the frame synchronization bytes (A1, A2 bytes) and outputs timing correction information when separating the multiplexing unit, and 210 is the output timing. Correction information,
Reference numeral 211 is a portion for performing an operation of including correction information in 22 using 210.

FIG. 7 shows a frame synchronization byte (A1 byte) input as serial data in the configuration of FIG.
However, depending on the timing of separating the multiplexing unit, the multiplexing unit may be separated by a few bits (hereinafter abbreviated as a bit deviation), and therefore, an incorrect frame synchronization byte (A1 byte) is output. It shows the state.

In FIG. 7, 31 indicates a time axis, and 32
Is the received STM-N clock, 33 is the received STM-N serial data, 34 is the frame synchronization byte (A1 byte) which is one of the multiplexing units included in 33, and 35 is 34 It is a separation timing that is correctly separated into multiplex units, and 36 is a timing when 34 is separated with a 1-bit shift.

37 is the timing when 34 is separated by 2 bits, 38 is the timing when 34 is separated by 3 bits, 39 is the timing when 34 is separated by 4 bits, 310 Is a timing when 34 is shifted by 5 bits and is separated, 311 is a timing when 34 is shifted by 6 bits, and 312 is 7 when 34 is shifted by 7 bits.
This is the timing of separation by bit shifting.

FIG. 8 is an STM-N which has received timing correction information when the multiplexing unit is separated in the configuration of FIG.
By including it in the clock, the operation of changing the separation timing to correctly separate the frame synchronization byte (A1 byte) is shown.

In FIG. 8, 40 is a time axis, and 41
Is the received STM-N serial data, and 42 is 4
1 is a frame synchronization byte (A1 byte) included in 1, 43 is a received STM-N clock, 44 is a timing at which 42 is separated by 1 bit, and 4 is
5 is 1-bit shift correction information, 46 is an STM-N clock including 45, 47 is a correct separation timing, 48 is a timing when 42 is shifted by 2 bits, and 49 is 2 bits. This is shift correction information.

Reference numeral 410 is an STM-N clock including 49, 411 is a timing at which 42 is separated by 3 bits, and 412 is 3 bits deviation correction information.
413 is an STM-N clock including 412,
Reference numeral 14 is a timing at which 42 is separated by shifting by 4 bits, and 415 is 4-bit shift correction information.

Reference numeral 416 is an STM-N clock including 415, 417 is a timing when 42 is separated by shifting 5 bits, 418 is 5-bit shift correction information, and 419 is STM-N including 418. Reference numeral 420 is a clock, 420 is a timing at which 42 is separated by 6 bits, and 421 is 6-bit deviation correction information.

Reference numeral 422 is an STM-N clock including 421, 423 is a timing when 42 is separated by shifting by 7 bits, 424 is 7-bit shift correction information, and 425 is STM-N including 424. It is a clock.

First, a method of multiplexing data output on the sending side will be described. As shown in FIG. 5, the input frame data strings 11 to 14 of # 1 to #N are
It is divided for each W bit 15 which is a multiplexing unit, and is # 1,
Interleaving multiplexing is performed in the order of # 2, ..., #N. The multiplexed W bit parallel data 17 is
Parallel / serial conversion is performed to output as a transmission signal, and the serial data 119 is transmitted.

Next, the operation of the above conventional example will be described. In the configuration shown in FIG. 6, the input STM-N serial data 21 is converted into an 8-bit parallel signal 25 by the S / P converter 24 using the STM-N clock 22 which is in phase synchronization with the STM-N serial data 21, and -N clock 2
It is latched by the 8-bit latch 25 using a clock 28 obtained by dividing 2 by 8 into 8 and output as a separated multiplexing unit 26. However, as shown in FIG. 7, the input STM-N serial data is separated at eight different timings, and therefore incorrect data that is not multiplexed data may be separated. There is a street.

Taking the frame synchronization byte (A1 byte) portion in the input STM-N serial data as an example, the frame synchronization byte (A1 byte) 34 input as the serial data is originally at the timing of 35. However, since the initial state of the separation timing is indefinite, there is a case where the separation is started at any timing from 36 to 312.

Therefore, the frame synchronization byte (A1 byte) that is separated and output is the normal separation timing 3
It is output as F6h in 5, but 7Bh when separated at timing 36, BDh in 37, DE in 38
6Fh for h, 39, B7h for 310, D for 311
Bh and 312 are output as EDh.

In order to correct this, at 29 in FIG. 6, a boundary shift as a multiplexing unit of the frame synchronization bytes (A1, A2 bytes) is detected, and correction information 210 corresponding to the shift amount is output. This information is sent to STM- at 211.
Perform the operation to be included in the N clock.

More specifically, as shown in FIG. 8, at a timing 44 separated by shifting by 1 bit, correction information 45 having a 1-clock length of the STM-N clock is output, and the received STM-N clock is received. Mask for 1 clock. STM-
Since the separation timing is delayed by one clock by inputting the N clock 46 to the S / P converter, the separation timing 44 deviated by 1 bit is corrected to the normal separation timing 47.

Even when they are separated by a shift of 2 to 7 bits, correction information 49, 412, 415, 418, 421, 424 having a length of 2 to 7 clocks of the STM-N clock is similarly obtained.
Is output, and the received STM-N clock is masked for 2 to 7 clocks.
-N clocks 410, 413, 416, 419, 42
Input 2,425 to the S / P converter. As a result, the separation timing is delayed by 2 to 7 clocks, so that the separation timings 48, 411, 414, 4 are shifted by 2 to 7 bits.
17, 420, 423 are corrected to the normal separation timing 47.

By the above operation, the correct multiplexing unit can be separated from the received STM-N serial data.

FIG. 9 shows a conventional STM-1 frame channel 1 (hereinafter abbreviated as STM-1 # 1) in which a multiplexing unit separated from STM-N serial data is separated in the time axis direction and interleaved and synchronously multiplexed. ) ~ STM-
It is a basic configuration of a device that outputs one frame channel N.

In FIG. 9, 51 is the received STM-N.
52 is 8-bit parallel data of STM-N (N is greater than or equal to 4), which is a multiplexing unit separated from serial data (N is greater than or equal to 4).
Is the received STM-N (N is greater than or equal to 4)
The clock is a clock that is frequency-divided by 8 and is phase-locked to 51. 53 to 56 are 8-bit latches, 57 is an N divider, 58 is a clock obtained by dividing 52 by N, and 59. Is an 8-bit latch.

Reference numeral 510 is STM-1 # 1 8-bit parallel data, 511 is STM-1 # 2 8-bit parallel data, and 512 is STM-1 # N-1 8
Bit parallel data, 513 is STM-1 # N
Of the 8 bits of parallel data, 514 is a channel shift detection unit, 515 is channel shift correction information, and 516 is an STM-1 clock signal.

FIG. 10 shows the operation of the apparatus shown in FIG. In FIG. 10, 61 is a time axis, 62 is a clock obtained by dividing the received STM-N (N is greater than or equal to 4) clock by 8, and 63 is the received STM.
-N (N is greater than or equal to 4) is an STM-N (N is greater than or equal to 4) 8-bit parallel data signal that is a multiplexing unit separated from serial data, and 64 is included in 63. This is STM-1 # N-1 data.

Reference numeral 65 is STM-1 # N data included in 63, 66 is STM-1 # 1 data included in 63, 67 is STM-1 # 2 data included in 63, and 68 is STM-N (N is greater than or equal to 4) is a correct latch timing for separating an 8-bit parallel signal into STM-1 × N channels, and 69 is a latch timing in which 68 timing is shifted by one channel.

FIG. 11 shows the relationship between each channel and interleave multiplexing on the transmitting side. In the figure, 71 is STM-1 # 1 data, and 72 is ST.
M-1 # 2 data, 73 is STM-1 # N-1 data, 74 is STM-1 # N data, and 75
Is the interleave-multiplexed STM-N (N is greater than or equal to 4) data, and 76 is the transmission direction of the interleave-multiplexed data.

Next, the operation of the above conventional example will be described. In the configuration of FIG. 9, input STM-N (N is greater than or equal to 4) 8-bit parallel data 51
Is latched by the 8-bit latch 53 using the phase-locked clock 52. The latched data is further latched by the 8-bit latch 54 using the clock 52, and this is repeated N times.

If the data thus developed into N × 8 bits is latched at the correct separation timing using the clock 58 obtained by dividing 52 by N, 510 is obtained by STM.
-1 # 1 data, 511 is STM-1 # 2 data, 5
STM-1 # N-1 data for 12 and STM for 513
-1 # N data is output, and each STM-1 data can be separated.

However, as shown in FIG. 11, since the received STM-N (N is larger than or equal to 4) data is interleaved and multiplexed in each time slot on the transmitting side, the channels are separated. Depending on the timing at which the STM-1 # 1 to #N data is output, a channel shift occurs in which the data is output to the wrong channel.

In order to correct this, in the channel shift detector 514 shown in FIG. 9, the separated STM-1
The STM identification byte (C1 byte) of the data is monitored, the channel shift correction information 515 is output to the N frequency divider 57 according to the channel shift amount, and the operation of changing the frequency division timing of the N frequency divider 57 is performed. .

FIG. 10 shows a specific example in the case of one channel shift. The correct separation timing for expanding the input STM-N (N is greater than or equal to 4) data signal into an Nx8-bit STM-1 data signal and outputting it as STM-1 # 1 to #N data is 68. However, depending on the output timing of the frequency divider, one clock of the input clock 62 may be output earlier to cause one channel shift.
In this case, the STM-1 # N data is separated and output to the portion where the STM-1 # 1 data is originally separated and output,
STM-1 # 1 is separated and output in the portion where 1 # 2 is separated and output, and a shift occurs in the channels that are sequentially separated and output.

By changing the frequency division timing of the frequency divider according to the channel shift correction information and delaying the separation timing 69 by one clock of the input clock 62,
The separation timing is 68, and separate output can be performed at the correct timing.

Similarly, when a 2 to N-1 channel shift occurs, the separation timing becomes 68 by delaying the separation timing by 2 to N-1 clocks of the input clock 62 by the channel shift correction information, and the correct timing is obtained. Can be separated and output.

By the above operation, it is possible to separate the interleaved multiplexed STM-N (N is greater than or equal to 4) 8-bit parallel data signal into the STM-1 8-bit parallel data signal xN channels. Become.

[0038]

However, in the above-mentioned conventional communication device, the clock mask shown in FIG. 8 is performed in order to correct the bit shift and establish the frame synchronization, which is 22 in FIG. It changes the received STM-N clock.

Further, in order to correct the channel shift and establish the channel synchronization, the N frequency division counter 57 shown in FIG. 9 is used.
STM-
One clock 516 is also changed, and finally the frame length of STM-1 created by dividing these clocks is changed.

When the STM-1 frame length changes, a byte other than the frame sync byte is detected at the position where the original frame sync byte (A1, A2 bytes should be), and the frame sync being established is once lost. ,
The device must re-search for the frame sync byte,
As a result, there is a problem that the time required for establishing frame synchronization and channel synchronization is significantly extended.

The present invention solves such a conventional problem, and provides a communication apparatus which significantly reduces the time required for frame synchronization and channel synchronization.

[0042]

In order to solve the above problems, a synchronous multiplexing communication device according to the present invention is a communication device for transmitting a signal in which a plurality of frames of the same format are interleaved and synchronously multiplexed, Interleaved demultiplexing unit for demultiplexing multiple multiplexed frames and the demultiplexing unit for each frame are separately configured, and the interleaved demultiplexing unit detects the frame phase of the demultiplexing unit for each frame. It is characterized by having a function of setting a multiplexing boundary by information.

Further, in the communication apparatus, the interleave demultiplexing unit has (2x multiplexing unit-1) stages of delay means and selection means for taking out data of a correct multiplexing boundary from the output thereof. Is characterized by.

[0044]

The synchronous multiplex communication apparatus according to the present invention, as means for correcting the bit shift and the channel shift, does not shift the multiplexing unit and the separation timing in the time axis direction by changing the clock, but receives the received serial signal. Data is S /
With the P converter, {W (W is a multiplexing unit) × 2 × N (N
Is an interleaved multiplex number) -1} bit parallel data signal, and the demultiplexed clock received by this is latched by a clock divided by (WxN) to demultiplex in the unit of time and the time axis direction. Done at the same time,
Using the detected bit shift and channel shift information,
Data is selected by switching WxN (WxN-1) to 1 selectors, and correctly separated # 1 to #N frame data is output without changing the clock.

As described above, the synchronous multiplex communication apparatus according to the present invention does not change the clock to establish the frame synchronization and the channel synchronization, so that the frame length does not change and the established frame synchronization is temporarily lost. The phenomenon cannot occur. Therefore, it is possible to significantly reduce the time required to establish frame synchronization and channel synchronization.

[0046]

BEST MODE FOR CARRYING OUT THE INVENTION As an embodiment of a synchronous multiplexing communication apparatus according to the present invention, an STM-4 receiving section which is a communication apparatus compatible with SDH (New Synchronous Multiple Hierarchy) will be described. In this case, the above-mentioned multiplexing unit W = 8 bits and the interleave multiplexing number N = 4.

FIG. 1 shows the configuration of an embodiment of a synchronous multiplexing communication device according to the present invention. In FIG. 1, 81
Is the received STM-4 serial data, 82 is the received STM-4 clock (622.08 MHz), and 83 is an S that converts 81 into a 63-bit parallel signal.
Is a P / P converter, 84 is a frequency divider for dividing 82 by 32, 85 is an STM-1 clock (19.44 MHz) obtained by dividing 82 by 32, and 86 is a 63-bit signal. It is a latch.

Further, 87 is data of the first bit (hereinafter abbreviated as Q1) from the time when the S / P conversion is started, and 88 is S / P.
Data of the second bit from the time when P conversion is started (hereinafter referred to as Q
(Abbreviated as 2), 89 is Q31, 810 is Q32, 811 is Q62, 812 is Q63, and 8
Reference numerals 13 to 816 are 31 to 1 data selectors.

Further, 817 is a D7 bit data output of STM-1 # 1, 818 is a D6 bit data output of STM-1 # 1, and 819 is a D1 bit of STM-1 # 4.
Bit data output, 820 is D of STM-1 # 4
0 bit data output, 821 is a bit shift and channel shift amount detection unit, and 822 is the bit shift and channel shift correction information output by 821.

In FIG. 2, 823 is a time axis, and 8
Reference numeral 24 is the start point of S / P conversion, and 825 is the data length of 63 bits.

FIG. 3 shows the structure of the received STM-4 serial data. In FIG. 3, 91 is a time axis, 92 is the received STM-4 serial data,
93 is STM-1 # 1 data, and 94 is STM-1.
# 2 data, 95 is STM-1 # 3 data, 96 is STM-1 # 4 data, and 97 is a data length of 32 bits.

Reference numerals 98 to 912 are 93 detailed configurations.
98 is the most significant bit (M in one byte of STM-1 # 1.
SB) (hereinafter abbreviated as D7), 99 is D6,
910 is D5, 911 is D1, and 912 is the least significant bit (LSB) D0.

FIG. 4 is a timing chart when S / P conversion is performed on the received STM-4 serial data.
In FIG. 4, 101 is a time axis, 102 is received STM-4 serial data, and 103 is STM-.
1 # 1 is D7 bit, 104 is STM-1 # 1 D6 bit, 105 is STM-1 # 1 D5 bit, 106 is STM-1 # 4 D1 bit, and 107 is It is the D0 bit of STM-1 # 4 and is 10
8 is a data length of 32 bits.

Timings at which 109, 1011, 1013, 1014 perform S / P conversion, latch the expanded parallel data and output as STM-1 # 1 to # 4 data (hereinafter abbreviated as S / P conversion timing). And 10
10 is separated STM-1 in case of 109 # 1 to # 4
The data output timing is 1012 and the separated STM-1 # 1 to # 4 data output timing in the case of 1011 is.

Next, the operation of the above embodiment will be described.
In the configuration of FIG. 1, the input STM-4 serial data 81 is S / P converted by the S / P converter 83 using the STM-4 clock 82 which is also the input demultiplexing clock.

Here, as shown in FIG. 3, the input STM-4 serial data 92 is STM-1 # 1 to STM-1 # 1.
# 4 data is interleaved multiplexed and each STM-1
Since the data has a multiplexing unit W = 8 bits and the interleave multiplexing number N = 4, the data length 97 of WxN = 32 bits is one unit of STM-4 data. Therefore, S / P conversion of the STM-4 serial data 92 is performed from an arbitrary time point, and in order that the expanded parallel data always includes one unit of the STM-4 data, it is expanded to (2xWxN-1) bits. You can do it,
The S / P converter 83 develops a 63-bit parallel signal.

The 63-bit parallel signal thus obtained is used as a clock (S) for one unit of STM-4 data.
If the TM-4 clock is latched by the 63-bit latch 86 by using 85 which is a clock obtained by dividing W × N = 32 by 84), the outputs Q1 to Q63 of the latch 86 are S
A specific bit of a specific channel in TM-1 # 1 to # 4 data is always separated and output.

As shown in FIG. 4, there are 31 S / P conversion timings because one unit of STM-4 serial data has 32 bits.

Here, among the separated and output data, ST
D of STM-1 # 1 which is the first bit of M-4 data
Focusing on 7 bits, when STM1-1 # 1 to # 4 data is output at the S / P conversion timing 109, ST
The D7 bit of M-1 # 1 is output by the latch output Q1, the subsequent D6 bit is output by Q2, and so on. The D0 bit of the final bit STM-1 # 4 is output by Q31. It

Next, STM-1 # 1 to # 4 at 1013, which is the S / P conversion timing 1 bit before 109.
When data is output, the D7 bit of STM-1 # 1 is output in Q2, and the D0 bit of STM-1 # 4, which is the final bit, is output in Q32.

Next, at 1014, which is the S / P conversion timing before 30 bits from 109, STM-1 # 1 to # 1.
When 4 data is output, the D7 bit of STM-1 # 1 is output at Q30 and the final bit, STM-1 #
The D0 bit of 4 is output at Q62.

Finally, S / P of 31 bits before 109
At the conversion timing of 1011, STM-1 # 1 to
When # 4 data is output, the D7 bit of STM-1 # 1 is output at Q31 and the final bit, STM-1
The D0 bit of # 4 is output at Q63.

Therefore, S / P conversion is performed at any time,
Output 8 when STM-1 # 1 to # 4 data is output
In order to always obtain the D7 bit of STM-1 # 1 as 17, the 31 to 1 data selector 813 is used to input Q1 to Q31 as shown in FIG. It suffices to determine what number of data is selected by the information 822, switch the input, and output.

The D6 bit of STM-1 # 1 is D
When 7 bits are output to Q1, they are output at Q2, and when D7 bits are output to Q2, they are output at Q3. Therefore, as output 818, D6 of STM-1 # 1 is output.
To always get the bits, as shown in FIG.
Q2 to Q32 using the one-to-one data selector 814
Up to the same as the correction information 7 that obtains D7 bit
It suffices to switch the input and output according to 22.

Similarly, 32 31-to-1 data selectors are shifted one bit at a time to connect 32 selectors, and the correction information 82
2 to switch the inputs and output them STM-1
If the D7 bit of # 1 to the D0 bit of STM-1 # 4 are output, the STM-1 # 1 to # 41 with correct frame synchronization and channel synchronization can be obtained without changing the clock.
4 data can be obtained.

Thus, according to the operation of the above embodiment,
When the STM-4 serial data is separated into STM-1 # 1 to # 4 data, the STM-1 frame length is not changed, so that high-speed synchronization is established without losing the frame synchronization once established. It has the effect of being able to do.

In the above embodiment, STM-N (W =
8 and N = 4), the S / P conversion is performed on the input serial signal having the multiplexing unit W and the interleave multiplexing number N in the same configuration to obtain (2 × Wx
The data is expanded into (N-1) bit parallel data and latched by the (WxN) frequency-divided clock of the input STM-N clock. This output is (WxN) (WxN-1)
If the data is switched and output using the bit shift and channel shift correction information in the 1-to-1 data selector, the multiplexing unit is W, and # 1 to #N frames from the signal in which N identical frames are interleaved and multiplexed. Even when data is separated and output, correct frame data # 1 to #N can be obtained in both frame synchronization and channel synchronization.

[0068]

As is apparent from the above embodiment, the present invention separates serial data in which the multiplexing unit is W and N identical frames are interleaved and multiplexed into # 1 to #N frame data. Therefore, the data is expanded to (2xWxN-1) bit data, and the correct data is selected from both the frame synchronization and the channel synchronization, and the frame length of each separated frame is not changed. This has the effect that it is possible to establish frame synchronization and channel synchronization at high speed.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a multiplexing unit and an interleaved demultiplexer according to an embodiment of the present invention.

FIG. 2 is an operation timing chart of the apparatus of FIG.

FIG. 3 is a received STM-4 according to an embodiment of the present invention.
Serial data structure diagram

FIG. 4 is a diagram illustrating S / P for STM-4 serial data in FIG.
Timing diagram for conversion

FIG. 5 is an explanatory diagram of interleaved synchronous multiplexing.

FIG. 6 is a block diagram of a conventional multiplexing unit demultiplexer.

FIG. 7 is an explanatory diagram of separation timing shift in conventional multiplexing unit separation.

FIG. 8 is an operation timing chart in the conventional demultiplexing.

FIG. 9 is an explanatory diagram of a conventional interleaved demultiplexing operation.

FIG. 10 is a timing diagram of a conventional interleaved demultiplexing operation.

FIG. 11 is an explanatory diagram of a conventional interleaved synchronous multiplexing operation.

[Explanation of symbols]

81 STM-4 serial data received 82 STM-4 clock received (622.08MH
z) 83 serial-parallel (S / P) converter 84 frequency divider 85 STM-1 clock (19.44 MHz) 86 latch 87 1st bit data (Q1) 88 2nd bit data (Q2) 89 3rd bit Data (Q3) 810 32nd bit data (Q32) 811 62nd bit data (Q62) 812 63rd bit data (Q63) 813 to 816 31 to 1 data selector 817 STM-1 # 1 D7 bit data Output 818 D6 bit data output of STM-1 # 1 819 D1 bit data output of STM-1 # 4 820 D0 bit data output of STM-1 # 4 821 Bit shift and channel shift amount detection unit 822 Bit shift and channel shift correction information

Claims (2)

[Claims] 1. A communication device for transmitting a signal in which a plurality of frames of the same format are interleaved and synchronously multiplexed,
Interleaved demultiplexing unit for demultiplexing multiple multiplexed frames and the demultiplexing unit for each frame are separately configured, and the interleaved demultiplexing unit detects the frame phase of the demultiplexing unit for each frame. A synchronous multiplexing communication device having a function of setting a multiplexing boundary according to information. 2. The communication apparatus according to claim 1, wherein the interleave demultiplexing unit has (2 × multiplexing unit-1) stages of delaying means, and selecting means for extracting data of a correct multiplexing boundary from the output thereof. Item 2. The synchronous multiplexing communication device according to Item 1.