JPH08186105A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a method of manufacturing a semiconductor device capable of improving the degree of integration, which was limited by the dimension conversion difference. [Structure] The opening 6 of the region 4 is formed by the first thermal oxidation.
An element isolation insulating film 7 is formed on the substrate. Then, in the same way, area 5
The opening portion 8 is formed in the substrate and the second thermal oxidation is performed. At this time, the element isolation insulating film 9 is formed in the opening 8, and at the same time, the film thickness of the element isolation insulating film 7 already formed is increased. The bird's beak of the element isolation insulating film 7 having a large film thickness is large, and the bird's beak of the element isolation insulating film 9 having a small film thickness is small.
It is smaller than the size conversion difference of. A parasitic MOS transistor having a required threshold voltage of Vtf1 is provided in the region 4 in the region 5
The required threshold voltage is Vtf2 (Vtf1> Vtf
2) Form the parasitic MOS transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which element isolation is performed by using the LOCOS method.

[0002]

2. Description of the Related Art In recent years, the LOCOS method has been used in a method of manufacturing a semiconductor device such as a MOS transistor. The LOCOS method is widely used as an element isolation method in semiconductor devices. The LOCOS method will be described in the order of steps. For example, as shown in FIG. 7, a silicon oxide film 102 having a thickness of about 10 to 50 nm is deposited on a silicon substrate 101, and a silicon nitride film 103 is deposited on the silicon oxide film 102.
By photolithography and dry etching,
The opening 104 is formed in the silicon nitride film 103. In the figure, a indicates the width of the opening 104.

Next, as shown in FIG. 8, thermal oxidation is performed to form an element isolation insulating film 105 in the region of the opening 104. Then, the silicon nitride film 103 and the silicon nitride film 10 are wet-etched.
By removing the silicon oxide film 102 immediately below 3,
Element isolation is completed as shown in FIG. In FIG. 9, b is the width of the formed element isolation insulating film 105.

When the element isolation is performed, the element isolation insulating film 1
Original circuit elements (not shown) are formed in the element formation regions on both sides of 05, and electrode wirings and the like are formed on these circuit elements and the element isolation insulating film 105.
In this case, each circuit element is electrically insulated from each other by the element isolation insulating film 105.

[0005]

When the element isolation insulating film 105 is formed as described above, a so-called bird's beak 10 is formed at the end of the element insulating film 105 during thermal oxidation.
Due to 5a and 105b, a dimensional conversion difference ba occurs between the width a of the opening 104 and the width b of the element isolation insulating film 105. The size conversion difference b-a tends to increase as the element isolation insulating film 105 becomes thicker. On the other hand, the element isolation insulating film 105 also serves as a gate insulating film of the parasitic MOS transistor formed in the element isolation region. The thicker the gate insulating film, the higher the threshold voltage Vtf of the parasitic MOS transistor.

By the way, since the circuit element cannot be formed in the region of the width b of the element isolation insulating film 105, the LS
In order to improve the degree of integration of I, it is desirable to reduce this b and increase the area of the element formation region. However, since the width a of the opening 104 is determined by the exposure limit of photolithography, there is a limit in reducing the value of a under the same design rule. Further, in order to ensure electrical insulation between the circuit elements in the element formation region, it is necessary to secure a threshold voltage Vtf of the parasitic MOS transistor of a certain value or more.

On the other hand, the threshold voltage Vtf required for the parasitic MOS transistor may differ depending on whether it is formed in the P well or the N well. However, conventionally, a high threshold voltage Vtf
The element isolation insulating film 105 having a uniform thickness is formed on the basis of the parasitic MOS transistor which is required. For this reason, the originally required threshold voltage is low and the size conversion difference can be small. Therefore, the size conversion difference of the parasitic MOS transistor can be made equal to the size conversion difference of the element isolation insulating film having a large film thickness, and the element formation region can have a corresponding size conversion difference. There is a problem that the area is reduced and the improvement of the integration degree of the semiconductor device is hindered.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving the degree of integration, which was limited by the dimension conversion difference. is there.

[0009]

In order to achieve the above object, the present invention deposits a silicon oxide film on a substrate having a first region and a second region, and deposits a silicon nitride film thereon. And a step of partially removing a portion of the silicon nitride film corresponding to the first region to expose the silicon oxide film, and a step of oxidizing the silicon oxide film exposed by the step Forming an element isolation film, partially removing a portion of the silicon nitride film corresponding to the second region, and exposing the silicon oxide film; and the silicon oxide film exposed by this process. And forming a second element isolation film and oxidizing the first element isolation film.

[0010]

According to the present invention, the thickness of the second element isolation insulating film is smaller than the thickness of the first element isolation insulating film due to the above-described structure, and therefore the size of the bird's beak of the second element isolation insulating film is reduced. Since it is possible to reduce the size, it is possible to reduce the size conversion difference of the parasitic MOS transistor having the second element isolation insulating film as the gate insulating film. At this time, the threshold voltage of the parasitic MOS transistor having the first element isolation insulating film as the gate insulating film is higher than the threshold voltage of the parasitic MOS transistor having the second element isolation insulating film as the gate insulating film. Become.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 to 6 are schematic cross-sectional views of a semiconductor device showing the manufacturing method of this embodiment in the order of steps. In each of these figures, 1 is a silicon substrate, the left side of this silicon substrate 1 is a region 4, and the right side is a region 5.

First, as shown in FIG. 1, a silicon substrate 1
A silicon oxide film 2 is formed thereon, and a silicon nitride film 3 is further formed thereon. Here, a parasitic MOS transistor whose required threshold voltage is Vtf1 is provided in the region 4, and a parasitic MO transistor whose required threshold voltage is Vtf2 is provided in the region 5.
S-transistor is formed and V
It is assumed that there is a relationship of tf1> Vtf2.

With respect to the silicon substrate 1 of FIG. 1 on which the silicon oxide film 2 and the silicon nitride film 3 are deposited, in the region 4, the silicon nitride film 3 is patterned by photolithography and etching, and as shown in FIG.
The first opening 6 is formed. As a result, the silicon oxide film 2 is exposed at the bottom of the opening 6, as shown in FIG. Here, the width of the opening 6 is a ₁ . In this state, the first thermal oxidation is performed. By this oxidation, the exposed silicon oxide film 2 grows, and the element isolation insulating film 7 is formed as shown in FIG.

Next, for the region 5, the second opening 8 is formed by patterning the silicon nitride film 3 by photolithography and etching in the same manner as for the region 4, as shown in FIG. As shown, the silicon oxide film 2 is exposed. Here, the width of the opening 8 is a ₂ . In this state, the second thermal oxidation is performed. As a result, the opening 8
As shown in FIG. 5, a second element isolation insulating film 9 is formed on the. At this time, the already formed first element isolation insulating film 7 of the first opening 6 is also thermally oxidized at the same time, so that the element isolation insulating film 7 further grows and the film thickness increases.
Therefore, the final film thickness of the first element isolation insulating film 7 is determined by the total of the first and second thermal oxidations.

After the element isolation insulating films 7 and 9 are formed, as shown in FIG. 6, the silicon nitride film 3 and the silicon oxide film 2 immediately below the silicon nitride film 3 are sequentially removed. This completes the element isolation on the silicon substrate 1. Here, the width of the element isolation insulating film 7 is b ₁ and the width of the element isolation insulating film 9 is b ₂ . After that, circuit elements (not shown) such as desired transistors are formed in the regions 4 and 5. The circuit elements on the left and right of the region 4 thus formed are electrically isolated by the element isolation insulating film 7, and the circuit elements on the left and right of the region 5 are electrically isolated by the element isolation insulating film 9.

The element isolation insulating films 7 and 9 obtained by the above steps have different film thicknesses, as shown in FIG.
That is, the film thickness of the element isolation insulating film 7 subjected to the thermal oxidation twice is the same as that of the element isolation insulating film 9 subjected to the thermal oxidation only once.
Thicker than the film thickness. Therefore, the film thickness of each of the element isolation insulating films 7 and 9 can be arbitrarily controlled by appropriately adjusting the degree of the first and second thermal oxidations.

On the other hand, the size of the bird's beaks 7a, 7b and 9a, 9b generated at the end portions of the element isolation insulating films 7 and 9 depends on their respective film thicknesses, and the bird's beak of the thin element isolation insulating film 9 is ., Which is smaller than the bird's beak of the element isolation insulating film 7 having a large film thickness. Therefore, even when the width of the first opening 6 and the width of the second opening 8 are equal (a ₁ = a ₂ ), the dimensional conversion difference b ₂ -a
₂ can be set to a value smaller than the dimensional conversion difference b ₁ −a ₁ of the element isolation insulating film 7.

Conventionally, the required threshold voltage is Vtf1.
And Vtf2 (Vtf1> Vtf2)
When the S transistor is formed on the same substrate, the thickness of the element isolation insulating film is designed according to the high threshold voltage Vtf. Therefore, the bird's beak of the element isolation insulating film, which is supposed to be small in size conversion, becomes large, and the area of the element formation region on the silicon substrate is reduced accordingly, which hinders high integration of integrated circuits, especially memory elements. It was. However, as in the present embodiment, by individually controlling the film thickness of the element isolation insulating films 7 and 9 in accordance with the required threshold voltage, the size of the bird's beak can be minimized and a finer beak can be obtained. Different processing is possible, and the degree of integration can be improved more than before under the same design rule.

Therefore, for example, when a P well and an N well are formed on one silicon substrate and a MOS transistor for a circuit element and a parasitic MOS transistor are formed in each well, the parasitic MOS transistor formed in the P well is formed. The required threshold voltage may differ between the parasitic MOS transistors formed in the N-well and the N-well. Therefore, a parasitic MOS that requires a high threshold value
A transistor is formed by using the first element isolation insulating film, and a parasitic MOS transistor having a low threshold voltage is formed by using the second element isolation insulating film, thereby maintaining proper operating characteristics. Under the same design rule, a semiconductor device with a higher degree of integration can be obtained.

[0020]

As described above, according to the present invention,
For element isolation insulating films having different required threshold voltages, by setting the respective film thicknesses according to the threshold voltage, the dimensional conversion difference depending on the film thickness can be minimized. It is possible to provide a semiconductor device manufacturing method capable of improving the degree of integration of circuit elements under the same design rule.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a state in which a silicon oxide film and a silicon nitride film are sequentially deposited on a silicon substrate.

FIG. 2 is a schematic cross-sectional view showing a state in which a first opening is formed by removing a part of silicon nitride by etching.

FIG. 3 is a schematic cross-sectional view showing a state where an element isolation insulating film is formed in a first opening by thermal oxidation.

FIG. 4 is a schematic cross-sectional view showing a state in which a second opening is formed by further removing a part of silicon nitride by etching.

FIG. 5 is a schematic cross-sectional view showing a state in which an element isolation insulating film is formed in the second opening by thermal oxidation and the first element isolation insulating film is further oxidized.

FIG. 6 is a schematic cross-sectional view showing a state in which a silicon nitride film and a silicon oxide film are removed by etching and a device isolation process is completed.

FIG. 7 is a schematic cross-sectional view showing a state in which an opening is formed by sequentially depositing a silicon oxide film and a silicon nitride film on a silicon substrate and then removing a part of the silicon nitride by etching.

FIG. 8 is a schematic cross-sectional view showing a state in which an element isolation insulating film is formed in an opening by thermal oxidation.

FIG. 9 is a schematic cross-sectional view showing a state in which the silicon nitride film and the silicon oxide film are removed by etching and the element isolation process is completed.

[Explanation of symbols]

1, 101 Silicon substrate 2, 102 Silicon oxide film 3, 103 Silicon nitride film 4, 5 Region 6 First opening 7, 9, 105 Element isolation insulating film 8 Second opening 7a, 7b, 9a, 9b, 105a, 105b Birds beak

Claims (1)

[Claims] 1. A step of depositing a silicon oxide film on a substrate having a first region and a second region, and depositing a silicon nitride film on the silicon oxide film, which corresponds to the first region of the silicon nitride film. A part of the silicon oxide film exposed to expose the silicon oxide film; a step of oxidizing the silicon oxide film exposed by this process to form a first element isolation film; A step of partially removing a portion corresponding to the second region to expose the silicon oxide film, and a step of oxidizing the silicon oxide film exposed in this step to form a second element isolation film, and And a step of oxidizing the first element isolation film.