JPH0818964A - Image reduction circuit - Google Patents

Abstract

PURPOSE:To provide an inexpensive and fast image reduction circuit by using an image compression/expansion circuit as a filtering processing circuit for the prevention of folded distortion. CONSTITUTION:A filter processing circuit 11 for the prevention of folded distortion consists of a discrete cosine transformation(DCT) circuit 12 that is the compression/expansion block of JPEG, quantization circuits 13, 14, an inverse discrete cosine transformation (IDCT) circuit 15 and a quantization step value setting circuit 16. The quantization step value setting circuit 16 sets different quantization step values to be set in compression and expansion for a frequency area desired to attenuate for the prevention of the folded distortion. In this way, it is possible to operate the compression/expansion block (inexpensive one is provided recently) operated at high speed as the filter processing circuit and to inexpensively provide an image reduction circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image reducing circuit for obtaining a reduced image, and an image compressing / expanding circuit which has recently been sold at a low cost is used as a filtering processing circuit for preventing aliasing distortion. An object is to provide an inexpensive and high-speed image reduction circuit.

[0002]

2. Description of the Related Art When searching a recorded still image or recording a program title as a still image and displaying a program table of contents, the still image is made into a reduced image as a visual index display means. A method of displaying a plurality of images on one screen is used.

In the process of creating a reduced image, aliasing distortion occurs when a simple thinning process is performed. Therefore, a high-quality reduced image can be obtained by performing a filtering process for preventing aliasing and then performing a thinning process. (Although the original image of the reduced image has already been digitized, creating a reduced image means thinning out each sampling value, so the sampling frequency is equivalently low. If left as it is, so-called aliasing distortion occurs as much as the sampling frequency becomes low.)

FIG. 2 shows a conventional image reduction circuit for obtaining a high-quality reduced image. This image reduction circuit includes a filter (hereinafter referred to as an undersampling filter) processing circuit 1 for attenuating a high frequency component that causes aliasing distortion, and a thinning circuit 2. Since the reduced image is usually thinned out in the H (horizontal) direction and the V (vertical) direction, the undersampling filter processing circuit 1 is a two-dimensional filter. By thinning out the data subjected to the undersampling filter processing in accordance with a desired reduced image in the H direction and the V direction, a high-quality reduced image can be obtained.

Since the processing for obtaining the reduced image is not real-time processing, it does not require ultra-high-speed hardware, but when a certain processing speed is required, expensive dedicated high-speed hardware ( For example, JP-A-2-90867) is required. Although there is a method of processing the filtering process by software, it takes time, which causes deterioration of system response.

Further, in the case of a system that only displays a reduced image without performing image reduction processing, a required reduced image is created and recorded in another system in advance, and is read and used when displaying. There is also a method. In this method, since it is sufficient to record a high-quality reduced image at the time of recording, it is not necessary to prepare a reduced image creation block in the display system. However, the storage capacity is sacrificed.

If the above method cannot be applied, a reduced image is created by a simple thinning process, but the reduced image has a degraded image quality due to aliasing distortion.

[0008]

The thinning processing in the H direction and the V direction is a simple circuit, so there is no problem. However, in order to realize the undersampling filter processing by high-speed dedicated hardware, a large number of high-speed addition and integration circuits are required. Need. This high-speed addition and integration circuit has a large circuit scale and is expensive. Therefore, the undersampling filter processing circuit, which is an aggregate of the addition and integration circuits, becomes considerably expensive.

When software processing is performed by an arithmetic processing block (for example, CPU) in the system without preparing dedicated high-speed hardware, the undersampling filter processing for one image takes time, so that a reduced image is displayed. The time to get it will be much slower than a system with dedicated hardware. This time difference is
This leads to a decrease in the response of the entire system. The method of recording the reduced image in advance can be used only for the display system, and further, the storage capacity of the recording medium is reduced by the storage area of the reduced image.

An object of the present invention is to provide an inexpensive image reducing circuit which can obtain a high-quality reduced image at high speed.

[0011]

In order to solve the above problems, the present invention provides a filtering processing circuit which is supplied with a digitized video signal and performs a filtering process for preventing aliasing distortion, and the filtering process. An image reduction circuit comprising a thinning processing circuit for thinning out an output signal of the circuit and outputting a reduced image signal, wherein the filtering processing circuit is a discrete cosine transform circuit to which the digitized video signal is supplied, A first quantizer circuit to which the output signal of the discrete cosine transform circuit is supplied, a second quantizer circuit to which the output signal of the first quantizer circuit is supplied, and an output of the second quantizer circuit A signal is supplied to the decimation cosine transform circuit which supplies the signal to the decimation processing circuit, and a first quantization step value to the first quantization circuit. And a second quantization step value setting circuit for setting a second quantization step value in the second quantization circuit, wherein the quantization step value setting circuit is (1) In the digitizing circuit, a large first quantization step value is set for the frequency region to be attenuated to prevent aliasing distortion in the digitized video signal, and the first quantization step value is set to the non-attenuating frequency region. Set a small first quantization step value,
(2) In the second quantization circuit, a second quantization step value that is the same small value as the first quantization step value is set for the frequency region that is not attenuated, and the attenuation is performed. The present invention provides an image reduction circuit characterized in that a second quantization step value smaller than the first quantization step value is set in accordance with the amount of attenuation in the frequency domain to be set.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Recently, a discrete cosine transform (DC) has been used as dedicated hardware for efficiently compressing and expanding still images at high speed.
T) circuit, first and second quantization circuits, and an inverse discrete cosine transform (IDCT) circuit (for example, JPEG (Joint Potographic Expert Group))
Standard DCT system hardware) is supplied at low cost. The present inventor has considered that this dedicated hardware for compression / expansion can be used as an undersampling filter processing circuit, and a high-quality reduced image can be obtained at high speed.
Moreover, it is possible to realize an inexpensive image reduction circuit.

Here, the baseline process (essential function) of the DCT method, which is one of the compression methods of the JPEG algorithm described above, will be briefly described with reference to FIG.
(For details, refer to "Interface" published by CQ Publisher, 1991.
December issue: "International standard encoding method for color still images"
(See P160 to P167)

8 × 8 block image data, which is a digital video signal, is DCT processed, its output is quantized according to a quantization step value, and entropy coding is performed to perform compression processing, and vice versa. By doing so, the extension is performed. The 8 × 8 block DCT processing means that the data in the block is two-dimensionally frequency-decomposed, and the amount of information is reduced by performing the quantization processing according to the characteristics of human eyes. The data can be compressed by the encoding process of.

Linearly quantizing the data output from the DCT circuit with a step value defined by the Q table means that rUV = ROUND (SUV / QUV) ROUND: integerization to the nearest integer rUV: quantized Coefficients SUV: Coefficients output from DCT QUV: Quantization step values specified in the Q table U, V: DCT coefficient positions. In addition, the dequantization performed during expansion is

S'UV = rUV × QUV S'UV: Dequantized coefficient For example, if SUV = 126 and QUV = 5, then rUV = 25 and S'UV = 125. The values differ between SUV and S'UV, but they have returned to almost the same values. If this is subjected to IDCT (inverse DCT) processing, it is expanded into 8 × 8 blocks close to the original image. The difference between SUV and S'UV is the main factor that makes it impossible to completely reproduce the original image.
The baseline process of is included in the lossy compression process in this sense. Of course, the larger the quantization step, the larger the error.

Since the image cannot be separated from the original image by the compression / expansion process of the image, it is specified in JPEG that the same value is used for the QUV used for compression and the QUV used for expansion. There is. Further, since the compression ratio and the image quality at the time of expansion are determined by the value of the Q table, it is also specified that the value of the Q table can be arbitrarily set by the user.

Since the DCT process described above performs two-dimensional frequency decomposition, the inventor of the present invention is equivalent to the filter process if the IDCT process is performed by reducing the coefficient of the frequency to be attenuated. We have found that processing can be realized.

For example, the maximum value (8bi) that can set QUV
When t is set to 255), rUV becomes 0 or 1. When this is inversely quantized, it becomes 0 or 255. However, if the QUV value used in the inverse quantization is set to the minimum value, that is, 1 instead of the maximum value, the value obtained as a result of the inverse quantization becomes 0 or 1. This is equivalent to reducing the coefficient input to the IDCT process.

Therefore, the value of QUV in the frequency region to be attenuated by the undersampling filter process is set to a large value, and the value of QUV in the region not to be attenuated is set to a small value and compressed.
Q'UV used during expansion has the same value as in compression in the area where you do not want to attenuate it, and the amount of attenuation (Q'UV / QU in the area you want to attenuate it).
Set a value smaller than QUV according to V). The value of IDCT obtained by this processing is almost equal to the value obtained by undersampling filter processing.

As a result, it becomes possible to use an inexpensive and high-speed JPEG compression / expansion block as an undersampling filter processing block. By performing thinning processing on the data output from the JPEG compression / expansion block, a high-quality reduced image in which the undersampling filter processing is performed and the aliasing distortion is removed can be obtained.

FIG. 1 is a block diagram of the first embodiment of the present invention.
Shown in Undersampling filter processing circuit 11
Includes a discrete cosine transform (DCT) circuit 12, quantization circuits 13 and 14, an inverse discrete cosine transform (IDCT) circuit 15, and a quantization step value setting circuit 16, which are JPEG compression / expansion blocks.

The quantization step value setting circuit 16 supplies a large value QUV (quantization step value) to the quantization circuit 13 for performing quantization during compression for a frequency region to be attenuated by undersampling filter processing. Set and set a small value of QUV for the frequency range that you do not want to attenuate. In addition, the quantization step value setting circuit 16 instructs the quantization circuit 14 that performs inverse quantization at the time of expansion to the same value Q'UV (quantization step value) as that at the time of compression for the frequency region that is not desired to be attenuated. Is set, and Q'UV having a value smaller than QUV is set according to the amount of attenuation (Q'UV / QUV) for the frequency region to be attenuated.

By supplying the data output from the IDCT circuit 15 to the thinning-out processing circuit 2, as an output signal of the thinning-out processing circuit 2, a high-quality reduced image signal subjected to undersampling filter processing and aliasing distortion removed. Is obtained. In the example shown in FIG. 1, the quantizing circuits 13 and 14 are directly connected, but needless to say not be directly connected. For example, the output of the quantization circuit 13 is temporarily stored in a memory or the like via an entropy coding circuit (see FIG. 3), and the data read from the memory is quantized via an entropy decoding circuit (see FIG. 3). You may make it supply to the conversion circuit 14.

The reduced image obtained by the above method has high image quality, but two processes, compression and decompression, must be performed. The second embodiment described below is
The image signal that has already been JPEG compressed (compressed in the baseline process of the DCT method) is input, and a reduced image having a certain good image quality is obtained only by the expansion process.

It has already been mentioned that JPEG compression is lossy compression. In a sense, it can be said that this lossy compression provides a high compression rate. Since it is lossy compression, the original image cannot be completely reproduced even if it is expanded. However, if the difference from the original image is too clear for human eyes, it cannot be used in practice. Therefore, there is no choice but to make a difference from the original image where it is difficult for the human eye to detect it. Since the human eye has characteristics similar to a low-pass filter, the Q table (quantization step value table) used in the baseline process of the JPEG DCT method has a large step value at high frequencies. Often

Therefore, when decompressing the image data that has been once compressed and recorded, the QUV in the frequency region that is not desired to be attenuated uses the value indicated by the compressed data, and the QUV in the frequency region that is desired to be attenuated is as much as possible. Use a smaller value. By reducing the image data obtained from the decompression result, a reduced image can be obtained. Although this reduced image is an image that has been subjected to thinning processing after being attenuated to some extent, although the frequency component of the region causing folding back is not sufficient, the image quality is better than that of a simple thinned reduced image. .

The configuration of the second embodiment is obtained by removing the DCT circuit 12 and the quantization circuit 13 which are compression blocks from the first embodiment shown in FIG. Already JPEG compression (D
Compression in the CT baseline process)
A video signal (compressed data) that has undergone CT processing and quantization processing is supplied to the quantization circuit 14 of the decompression block. The quantization step value setting circuit 16 sets, in the quantization circuit 14, QUV having a value instructed by the supplied compressed data for the frequency region which is not desired to be attenuated, and for the frequency region which is desired to be attenuated. For this reason, set QUV as small as possible. The output of the quantization circuit 14 is supplied to the thinning processing circuit 2 via the IDCT circuit 15.

Although the image quality of the second embodiment is inferior to that of the first embodiment, the cost and size can be further reduced. Further, in the second embodiment, since the undersampling filter processing time is only the time corresponding to the expansion processing time,
It is possible to process even faster.

In recent years, JPE has been used as a system for handling still images.
Many have a G (DCT system baseline process) compression function, but if the present invention is used, a reduced image creation function can be achieved by simply adding thinning-out processing (software processing or hardware processing). Can be added.

[0031]

As described above, the image reducing circuit of the present invention has the following effects. (A) The present inventor has made it possible to use a low-cost circuit for performing compression / expansion at high speed as a filtering processing circuit for performing filtering processing (undersampling filter processing) for preventing aliasing distortion. ,
The image reducing circuit according to the first aspect can be realized at low cost, and high-quality reduced images can be obtained by high-speed processing.

(B) The image reducing circuit according to claim 2 is inferior in image quality to the image reducing circuit according to claim 1,
The cost and size can be further reduced, and good image quality can be obtained as compared with a reduced image that is simply thinned out without performing undersampling filter processing. Furthermore, this image reduction circuit can perform processing at a higher speed because the undersampling filter processing time only needs to correspond to the expansion processing time.

[Brief description of drawings]

FIG. 1 is a diagram showing a block configuration of a first embodiment.

FIG. 2 is a diagram showing a conventional example.

FIG. 3 is a diagram for explaining a DCT-based baseline process of the JPEG algorithm.

[Explanation of symbols]

 2 Decimation processing circuit 11 Undersampling filter processing circuit 12 Discrete cosine transform (DCT) circuit 13, 14 Quantization circuit 15 Inverse discrete cosine transform (IDCT) circuit 16 Quantization step value setting circuit

Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H04N 5/262

Claims (2)

[Claims] 1. A filtering processing circuit which is supplied with a digitized video signal and performs a filtering processing for preventing aliasing distortion, and a thinning processing for thinning an output signal of the filtering processing circuit and outputting a reduced image signal. An image reduction circuit comprising a circuit, the filtering processing circuit, a discrete cosine transform circuit to which the digitized video signal is supplied, and a first output signal from the discrete cosine transform circuit.
, A second quantizer circuit to which the output signal of the first quantizer circuit is supplied, an output signal of the second quantizer circuit, and a signal to the thinning processing circuit. An inverse discrete cosine transform circuit for setting a first quantization step value in the first quantization circuit and a second quantization step value in the second quantization circuit The quantization step value setting circuit comprises: (1) a frequency domain in the digitized video signal that is attenuated to prevent aliasing distortion with respect to the first quantization circuit; On the other hand, a large value of the first quantization step value is set, and a small value of the first quantization step value is set for the frequency domain that is not attenuated. (2) The second quantization step value Frequency not attenuated for the circuit A second quantization step value that is the same small value as the first quantization step value is set for the frequency band, and the first quantum value is set according to the amount of attenuation for the frequency region to be attenuated. An image reduction circuit characterized by setting a second quantization step value smaller than the quantization step value. 2. A digital video signal that has been subjected to a discrete cosine transform process and a first quantization process according to a first quantization step value is supplied, and a quantization process according to a second quantization step value is performed. A quantization circuit to perform, an inverse discrete cosine transform circuit to which an output signal of the quantization circuit is supplied, a quantization step value setting circuit to set the second quantization step value to the quantization circuit, the inverse circuit An output signal of the discrete cosine transform circuit is supplied, and a thinning processing circuit that performs thinning processing and outputs a signal for a reduced image is configured, and the quantization step value setting circuit prevents aliasing distortion in the digital video signal. For the frequency domain to be attenuated for, a second quantization step value smaller than the first quantization step value is set, and for the frequency domain not to be attenuated, Serial second image reduction circuit and setting the quantization step value of the first quantization step value and the same value.