JPH08194565A - ID controller - Google Patents

Abstract

(57) [Abstract] [Purpose] To reduce the power consumption of the input unit in an ID controller to which parallel signals are input. [Structure] The ID controller 10 is provided with a sampling output unit 13a for outputting a timing for inputting input data. Power is supplied to the input determination circuit 11 via the switch means 12 by the signal of the sampling output section 13a. Therefore, the power corresponding to the input signal is consumed only during this period, the input is discriminated, and the CPU 13 takes it.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ID controller, and more particularly to an ID controller characterized by its input circuit.

[0002]

2. Description of the Related Art Conventionally, it comprises a data carrier which is attached to an article or the like and holds data, and a writing / reading unit which writes and reads data to and from the data carrier when the data carrier is conveyed along a conveying path or the like. An identification system is used. In such identification systems, an ID controller is used to write and read data on the data carrier. The ID controller transmits a control signal and data via a read / write head so as to write or read data at a predetermined address of a data carrier.

Data to be written is given to such a conventional ID controller from a host computer such as a host programmable controller. FIG. 4 is a circuit diagram showing an example of the input circuit of this ID controller. In this figure, an open collector transistor Q1 is connected to the output side of the programmable controller 1, and the collector terminal is connected to the diode D in the ID controller 2.
It is connected to the midpoint of 1, D2. The diode D1 is a Zener diode that limits the collector voltage to a predetermined value, and its anode end is grounded. The cathode end is connected to the cathode end of the diode D2. The anode of the diode D2 is connected to the power supply via the resistor R1, and a current flows only in a predetermined direction. The voltage source is connected to the voltage dividing circuit of the resistors R2 and R3, and the non-inverting input terminal of the comparator 3 is connected to the midpoint thereof. The inverting input terminal of the comparator 3 is connected to the anode end of the diode D2. The output terminal of the comparator 3 is connected to C in the ID controller via the pull-up resistor R4.
It is connected to the input end of PU4.

The operation at the time of input of the ID controller having such an input circuit will be described with reference to FIG.
First, the transistor Q1 of the programmable controller 1
It is assumed that the base potential of 1 changes as shown in FIG. In this case, since the collector end of the transistor Q1 is inverted as shown in FIG. 5B, a current flows through the resistor R1 at the L level and the input terminal is held at the L level. Therefore, as a result, one input terminal of the comparator 3 changes and the other input terminal is constant, so that the input value can be discriminated and input to the input port in the CPU 4.

[0005]

However, according to such an input circuit, as shown in FIG. 5 (e), while the collector terminal of the transistor Q1 is at the L level, the power source always keeps a constant value through the resistor R1. A current I flows and power is consumed. Since such an input circuit consumes an input current for each bit when the inputs are connected in parallel, the power consumption of the interface circuit portion of the input increases and the power consumption of the entire ID controller increases. . For this reason, the temperature of the peripheral portion of the input circuit rises greatly, and the deterioration of the electronic circuit parts easily occurs. Further, there are drawbacks that the range of use of electronic parts used in the vicinity thereof is limited and the use temperature condition becomes severe.

The present invention has been made in view of the above-mentioned conventional problems, and the current flowing in the input circuit portion of the ID controller is switched so that the current flows only when the input is taken in. The purpose is to solve the problem.

[0007]

According to the invention of claim 1 of the present application, in an ID controller for transmitting data to a data carrier in a non-contact manner and receiving data from the data carrier, the timing of accepting an input to the ID controller is set. Sampling output section for outputting the sampling signal shown, input determining means for determining the input level of the parallel signal input to the ID controller from the host computer, and the input determining means only while the sampling signal is input from the sampling output section. And switch means for supplying power to.

Further, the invention of claim 2 of the present application includes address setting means for setting an address for writing / reading data to / from the data carrier, wherein the input determining means receives a 1-byte parallel signal as an input signal. It is a feature.

[0009]

According to the invention of claim 1 of the present application having such a feature, when a parallel input signal is input to the ID controller, the input determination means determines the input signal. At this time, a sampling signal is output at the timing when the ID controller receives an input, and power is supplied to the determination signal only during that time. Therefore, the power consumption in the ID controller can be significantly reduced. Further, according to the invention of claim 2 of the present application, this ID controller is applied to an ID controller which inputs and outputs in bit units. In this case, since a 1-bit parallel signal is given as an input signal, it is possible to reduce power consumption when determining the input signal.

[0010]

1 is a block diagram showing the overall construction of an ID controller according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the input circuit portion thereof. In the figure, the ID controller 10 has an input discriminating circuit 11 on the upper computer side.
Is connected. The input discriminating circuit 11 is supplied with power from the switch means 12 and is energized at the timing of receiving data to the microcomputer to discriminate the input and discriminate C
This is transmitted to the PU 13 side. A level holding means 14 is connected between the switch means 12 and the CPU 13. The level holding means 14 holds the input level to the input discrimination circuit 11 at the L level when the switch means 12 is off. Further, the ID controller 10 is provided with a display circuit 15 and a setting circuit 16 for setting the address of the data carrier and the like. Further, a transmission / reception circuit 18 for transmitting / receiving signals to / from the output circuit 17 and the separation sensor circuit is connected. Further, a power supply circuit 19 for supplying power to each part of the ID controller 10 is provided. A separate sensor circuit 20 is connected to the transmission / reception circuit 18. Separation sensor circuit 20
Is configured to include an antenna coil for both transmission and reception, and performs data transmission with the data carrier 21.
If the setting circuit 16 writes or reads data in 1-bit units in the data carrier, the read / write address is set. Further, an automatic mode for automatically transmitting and receiving when a data carrier approaches, a synchronous mode for transmitting data at regular intervals, a read mode, a write mode, etc. are set. Further, the display circuit 15 displays the operating state, the address written in the data carrier, and the input / output data in bit units.

FIG. 2 is a circuit diagram showing the input circuit section of the ID controller 10 of this embodiment. In this figure, the same parts as those of the conventional example described above are designated by the same reference numerals, and detailed description thereof is omitted. As shown in the figure, a plurality of output transistors are connected to the parallel output terminals of the host computer. In FIG. 2, only one of the output transistors Q1 is shown. Also in this embodiment, the output transistor Q1
A zener diode D1 and a diode D2 are connected to, and a load resistor R1 and a comparator 3 are further connected.
The middle point of the voltage dividing circuit of the resistors R2 and R3 is connected to the non-inverting input terminal of the comparator 3 to form the input discriminating circuit 11. Further, the CPU 13 has a sampling output unit 13a.
Is connected. The sampling output section 13a outputs an H level output to the switch means 12 and the level holding means 14 at the timing of sampling for fetching data. Now, the switch means 12 operates in accordance with the output of the sampling output means 13a, and operates as a switching F.
It is configured to include an ETQ2, a transistor Q3 that turns on and off at the same time as the FET Q2, and a resistor. FET Q2
Is a field effect transistor whose drain is connected to the base of the transistor Q2 and whose source is grounded. The transistor Q3 is a switching PNP transistor having an emitter connected to the power supply and a resistor R6 connected between the base and the emitter, and the load resistor R1 is connected to the collector side thereof. The switch means 12 energizes the resistor R1 only when the output of the sampling output section 13a is at the H level.

A transistor Q4 is connected to the output side of the sampling output section 13a via the inverter 22 of the level holding means 14. A resistor is connected between the base and emitter of the transistor, the emitter is grounded, and the collector is connected to the midpoint between the collector of the transistor Q3 and the resistor R1 via the resistor R9. The level holding means 14 holds the input terminal of the comparator 3 at the L level when the switching transistor Q3 is in the off state. In this embodiment, the input circuit for 1 bit is explained, but the switch means 12 and the level holding means 14 are common, and the input discriminating circuit 11 is the same as the number of inputs, that is, 8 inputs in case of 8-bit input. The discrimination circuit 11 is connected.

Next, the operation of this embodiment will be described with reference to a time chart. FIG. 3 is a time chart showing the operation of this embodiment, and (a) to (g) are a to g of FIG.
3 is a waveform diagram showing the waveform of each part of FIG. FIG. 3A shows the level of the base of the transistor Q1, and for example, times t _{1 to} t ₄
It becomes H level during. Independently of this, the sampling output unit 13 of the CPU 13 in the ID controller 10
As shown in FIG. 3B, the sampling signal is output from a during the time t ₂ to t ₃ . The switching transistors Q2 and Q3 are turned on only when the sampling signal is at the H level. Therefore, if the transistor Q1 of the programmable controller 1 is turned on while this signal is at the H level, current is supplied from the power supply through the resistor R1. In this state, the collector of the transistor Q1 becomes L level, and the resistor R1 consumes the electric power as shown in FIG. At this time, the output of the comparator 3 is at H level,
This signal is input to the CPU 13 between times t _{2 and} t ₃ .
Time t ₂ transistor Q2 between the previous and the time t ₃ ~t _5,
Since Q3 is in the off state, power is not consumed by the resistor R1 regardless of the state of the transistor Q1.

Now, suppose that the sampling signal becomes H level at time t ₅ . In this case, if the base voltage of the transistor Q1 is L level, its inverted output is obtained at the input terminal of the ID controller 10. In this case, almost no current flows through the resistor R1,
The voltage of the input terminal of the comparator 3 becomes H level. Therefore, an L level signal is input to the CPU 13. As described above, according to this embodiment, the current consumed by the resistor R1 is H when the sampling output of the data is H as shown in FIG.
This is the level, and the output of the host computer is limited to the H level. Therefore, the current consumption becomes t / T as compared with the conventional example, and the current consumption can be greatly reduced. Such an ID controller can be used as an ID controller that writes or reads data in 1-byte units, for example.

[0015]

As described in detail above, according to the present invention, the current consumption of the ID controller can be greatly reduced. Therefore, the ID controller itself can be downsized, and the deterioration of the electronic components can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of an ID controller according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an input portion of an ID controller of this embodiment.

FIG. 3 is a waveform diagram showing a waveform of each part of the ID controller of the present embodiment.

FIG. 4 is a circuit diagram showing an input portion of a conventional ID controller.

FIG. 5 is a waveform diagram showing a waveform of each part of a conventional ID controller.

[Explanation of symbols]

 1 Programmable Controller 10 ID Controller 11 Input Discrimination Circuit 12 Switch Means 13 CPU 13a Sampling Output Section 14 Level Holding Means 15 Display Circuit 16 Setting Circuit 17 Output Circuit 18 Transmitter / Receiver Circuit 19 Power Supply Circuit 20 Sensor Circuit Section 21 Data Carrier

Claims (2)

[Claims] 1. An ID controller for transmitting data to a data carrier in a non-contact manner and receiving data from the data carrier, comprising: a sampling output section for outputting a sampling signal indicating a timing of accepting an input to the ID controller; An input discriminating means for discriminating an input level of a parallel signal inputted from the computer to the ID controller; and a switch means for supplying power to the input discriminating means only while the sampling signal is inputted from the sampling output section. An ID controller characterized by being provided. 2. An address setting means for setting an address for writing / reading data to / from the data carrier, wherein the input determining means receives a 1-byte parallel signal as an input signal. Item I
D controller.