JPH0620201Y2 - Information writing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Industrial field B Outline of device C Conventional technology (Figs. 5 and 6) D Problems to be solved by device (Figs. 5 and 6) E Means for solving problems (Figs. 1 to 5) F action (Figs. 1 to 5) G embodiment (G1) First embodiment (Figs. 1 to 5) (G2) Other embodiments H Effect of invention A Industrial Field of Use The present invention relates to an information writing device, and is particularly suitable for being applied to an information card having a driving power supply which is a battery power supply.

B. Outline of the Invention The present invention enables an information writing apparatus to set a signal level of write information to be given to a data writing buffer circuit so as to be adapted to a threshold level of the data writing buffer circuit. As a result, the information can be written more reliably.

C Conventional Technology Conventionally, an electronic card such as an IC card having a built-in memory has been used as an information card of this kind, but when writing information to the memory of the information card, it is adapted to the type of battery power supply and the degree of wear. Thus, it is necessary to provide the information card with a write data signal having a signal level that exactly crosses the threshold level of each information card.

That is, as shown in FIG. 5, the write data signal DATA
, The potential condition is such that the threshold level V _{SH of} the information card is between the potentials V _H and V _L when the transition between the potential V _H or V _L of the logic “H” level or the logic “L” level is made. By doing so, the information card can write the write data signal DAT.
The potential of A is higher than the threshold level V _SH and is a high potential V
_When it becomes _H (or when it becomes a low potential _VL ), it is a logic "H" level (or a logic "L") as the write data signal DATA.
It is determined that the level) bit data has been supplied, and the logic "H" level (or logic "L" level) bit data is written in the memory.

As the information card which operates under such conditions, the information card having the structure shown in FIG. 6 can be applied.

That is, the information card 1 has an information data processing unit 2, an input / output circuit 3, and positive and negative side data input / output terminals P1P and P1N, and the negative side data input / output terminal P1N is grounded in the input / output circuit 3. ing.

The positive side input / output terminal P1P is
For example, it is connected to the ground through a data output switch circuit 4 formed of a field effect transistor (FET), and is also connected to a data write buffer circuit 5.

The information data processing unit 2 has an information data memory 7 in which information data is written or read out by a central control unit (CPU) 6, and a card power source V _CAD supplied from a card battery power source 8 is used. By operating, the write data D _IN supplied from the data write buffer circuit 5 is written in the information data memory 7 in the data write mode, and the read data D obtained from the information data memory 7 in the read mode. _OUT is applied to the gate of the data output switch circuit 4.

To write or read information data to or from the information card 1, by mounting the information card 1 on the information writing / reading device 11, the positive / negative data input / output terminals P1P and P1N of the information card 1 are written / read. The positive and negative side data input / output terminals P2P and P2N of the device 11 are brought into contact with each other. As a result, when the information data processing unit 12 shifts the potential between the positive and negative side data input / output terminals P2P and P2N to the potential V _H or V _L of the logic “H” or logic “L” level, The embedded reading device 11 executes a process of writing or reading data to or from the information card 1.

Here, the main power supply V _CC is supplied to the information data processing unit 12, and this main power supply V _CC is supplied to the positive electrode side data input / output terminal P2P through the output resistor 13, whereby the main power supply V _CC of the information writing / reading device 11 is supplied. Power is supplied from the _CC to the information card 1 through the output resistor 13 and the positive-side data input / output terminals P2P and P1P to reduce the consumption of the card battery power supply 8.

D Problem to be solved by the device D In the configuration of FIG. 6, in the information data read mode, the information data processing unit 2 of the information card 1 reads the read data according to the read data D _OUT read from the information data memory 7. By turning off (or on) the data output switch circuit 4 when D _OUT is logic “H” (or logic “L”), the potentials of the positive side data input / output terminals P1P and P2P are changed to those of the main power supply V _CC . The potential is maintained at the potential (or the ground potential), and a change in the potential generated at the positive electrode side data input / output terminal P2P at this time is taken into the information data processing device 12 as read data D _READ .

On the other hand, in the information data writing mode, the information data processing unit 12 of the information writing / reading device 11 sends the write data D _WRITE to the positive electrode side data input / output terminal P2P to inform the potential of the main power supply V _CC. It is applied to the data output switch circuit 4 through the positive side data input / output terminal P1P of the card 1.
As a result, the data output switch circuit 4 is set to a high impedance state, and the write data D _WRIET is taken into the data write buffer circuit 5.

The data writing buffer circuit 5 uses a threshold level V _SH of a predetermined potential (for example, a potential V _CAD / 2 which is about half of the card power V _CAD ) determined based on the card power V _CAD of the card power source 8. Then, the logical level of the information data DATA given to the information card 1 is judged and the write data D _IN is written in the information data memory 7 of the information data processing unit 2.

In the information data writing mode, the information data DA
If the logic “H” and “L” level potentials of TA are changed so as to exceed the threshold level V _SH of the data write buffer circuit 5, the data write buffer circuit 5 operates correctly and is the same. Thus, the write data D _IN whose logic level changes can be output.

However, based on the type of the battery power source 8 for the card mounted on the information card 1 or the consumption level thereof, the card power source V
_{As the CAD} value fluctuates, as shown in Fig. 5,
Threshold level V _{SH of} buffer circuit 5 for writing data
Changes to the potentials V _SHX1 and V _SHX2 as a result, the logic "H" of the information data DATA supplied from the information writing / reading device 11
When the potential V _H (or V _L ) of the (or “L”) level becomes lower (or higher) than the _{changed threshold} level V _SHX1 (or V _SHX2 ), the data write buffer circuit 5
Cannot correctly take in the write data signal DATA.

Further, as shown in FIG. 5, the threshold level V _{SH of the} data write buffer circuit 5 becomes a potential V _SHX3 , (or V _SHX4 ) close to the potential of the write data signal V _H (or V _L ). Then, the potential V _H (or V _L ) of the write data signal DATA,
Alternatively, even if the threshold levels V _SH of the data write buffer circuit 5 slightly change, the data write buffer circuit 5 cannot correctly take in the write data signal DATA.

The present invention has been made in consideration of the above points, and it seems that the potential of the card battery power supply differs depending on the type of information card, or the card battery power supply is consumed and the card power supply potential drops. Even in such a case, the present invention intends to propose an information writing device capable of surely reading information data into an information card.

E Means for Solving the Problems In order to solve the problems, in the first invention, the information writing is performed by inputting the information data signal S16 to the information data memory 32 through the data writing buffer circuit 26 of the information card 23. In the apparatus, operating point potential raising means (42, 44, 46, 47) for raising the operating point potential V _S of the information data signal S16 by a predetermined step potential ΔV,
The operating point potential V _S of the information data signal S16 exceeds the threshold level V _SH of the data writing buffer circuit 26, and the information data S3 can be written in the information data memory 32 through the data writing buffer circuit 26. The operating point potential setting means (42, 43, 44, 45) for stopping the rising operation of the operating point potential after confirming that it has been established is provided.

In addition to this, in the second invention, the operating point potential setting means (42, 43, 44, 45) includes the information data memory 3
When it is confirmed that the information data S4 can be written in 2, the operating point potential is raised by a predetermined number of steps, and then the stop operation is performed.

F action, the operating point potential of the information data signal S16, the information card 23
Since the setting can be made to adapt to the variation of the threshold level V _SH of the data writing buffer circuit 26 mounted in, it is possible that the power supply voltage of the information card 23 is different and the power supply voltage is lowered due to consumption. Also, the data write buffer circuit 26 can always be operated correctly and the information data S3 can be accurately written in the information data memory 34.

G Embodiment One embodiment of the present invention will be described below in detail with reference to the drawings.

(G1) First Embodiment In FIG. 1, reference numeral 21 indicates an information card writing system as a whole, which is an information writing device 22 and an information card 23.
By installing the information card 23, the positive and negative data input / output terminals P11P and P11N of the information card 23 are electrically contacted with the positive and negative data write terminals P12P and P12N of the information writing device 22, respectively. Data D
It is designed to be able to deliver ATA11.

In the case of this embodiment, the information card 23 has an input / output circuit 24 composed of a data output switch circuit 25 and a data write buffer circuit 26 of the FET structure in the same manner as described above with reference to FIG. At this time, if the write / read control circuit 31 controls the read operation state, the read information data S4 read from the information data memory 32 is applied to the information data output circuit 33 to form the read data D _OUT, and the read data D _OUT is formed. by controlling the Yotsute data output switching circuit 25 to the D _OUT, read data D _OUT
Can be supplied from the information card 23 to the information writing device 22 as the information data DATA11.

On the other hand, in the write mode, the information output device 22 sends the information data DATA11 so that the data output switch circuit 25 is set to a bias condition exhibiting a high impedance, and the data output switch circuit 25 is set.
The read data D _OUT is controlled so that it cannot be output. Thus, the data DATA11 supplied from the information writing device 22 is taken into the write code reading circuit 34 and the information data input circuit 35 of the information data processing unit 27 through the data writing buffer circuit 26.

The information data processing unit 27 is composed of a passive circuit which does not have a central processing unit (CPU), and the write code reading circuit 34 reads the write code signal S1 based on the write data D _IN and the write / read control circuit. When the data is supplied to 31, the information data memory 32 performs the write operation in synchronization with the clock signal S2 supplied from the clock signal generation circuit 36 to obtain the information data input circuit 35 based on the write data D _IN. The write information data S3 is written in the information data memory 32.

Here, the write / read control circuit 31 is adapted to set the information data memory 32 to a read operation in synchronization with the clock signal S2 whenever a write code signal is not applied, and the read thus read. Information data S
It is formed in the information data output circuit 33 on the basis of 4, on the data output switching circuit 25 in accordance with the logic level of the read data D _OUT, by off operation, information data DATA1 corresponding to the read data D _OUT
1 is the positive and negative side data input / output terminals P11P and P
11N can be sent to the information data processing unit 41.

When the information card 23 is inserted into the wearing state, the information writing device 22 detects this by the insertion detection element 40 and outputs the insertion detection signal S17 to the central processing unit (CPU) 42 of the information data processing unit 41. Give to. At this time, the CPU 42
As shown in FIG. 4, the operating point setting mode is set, and the operating point setting operation can be repeated a maximum of a predetermined number of times, for example, six times.

First, second, ..., Sixth operating point setting operation periods T1, T
2, ..., T6 are a write mode period MODE1 and a read mode period MODE2, respectively, and the CPU 42 controls the information card 23 to the write mode during the write mode period MODE1 to cause the information writing device 22 to write the information data DATA11. Is set so that the information card 23 is read in during the read mode period MODE2.
Is set to a read mode so that the information writing device 22 can read the information data DATA11.

In the write mode period MODE1, the CPU 42 supplies the write information data S11 to the data control circuit 44 by supplying the address signal S14 to the write data memory 43, and accordingly, the information data D formed of a time series data string.
ATA11 is connected to the positive and negative side data write terminals P12P
And from P12N.

Here, the write information data S11 includes write code data and write information data.

On the other hand, when the data control circuit 44 can receive the information data DATA11 sent from the information card 23 at the time of read data, the data control circuit 44 gives the input data S12 to the data discriminating circuit 45 to output the clock signal included in the input data S12. To detect.

The fact that the clock signal can be detected here means that the normal information data DATA11 has been sent from the information card 23, and at this time, the data discriminating circuit 45 supplies the data discriminating signal S13 to the CPU 42. .

Thus, in the CPU 42, the information card 23 is the information writing device 2
It can be recognized that the write data can be fetched from 2 and each operating point setting operation period T1
Determine whether to continue or interrupt T6.

That is, when the data discrimination signal S13 is not obtained in the read mode period MODE2 of the n-th operating point setting operation period Tn, the CPU 42 subsequently writes the (n + 1) th operating point setting operation period T (n + 1). The control of the write mode and the read mode is entered.

On the other hand, when the data determination signal S13 is obtained in the n-th operating point setting operation period Tn, the operating point determining operation mode is entered without entering the control of the next operating point setting operation period T (n + 1). .

The CPU 42 uses the writing mode MODE1 of the operating point setting mode.
In FIG. 4, as shown in FIG. 3, the write information data S11 is transferred from the data control circuit 44 to the information data DAT.
When sending out as A11, the control is performed such that the potentials V _S1 , V _S2 , ..., V _S6 of the operating point level Vs are reset while being increased step by step.

That is, operating point setting operation period T1, T2, ..., T6
In the writing mode MODE1 of the above, the CPU 42 supplies the operating point level data S15 designating the operating point levels V _S1 , V _S2 , ..., V _S6 to the operating point level control circuit 47 via the digital / analog conversion circuit 46. . At this time, the operating point level control circuit 47 outputs the output data signal S16 as shown in FIGS. 3 (A1), (A2) ... (A6).
The peak-to-peak voltage V _PP (potential difference between logic “H” and “L” levels) of the data transmitted as the information data DATA11 from the data control circuit 44 and its operating point potential (for example, the central potential of the peak-to-peak voltage V _PP ). V _S1 ,
Designate V _S2 , ..., V _S6 .

The data control circuit 44 uses the operating point potentials V _S1 , V _S2 , ..., V _S6 designated by the output data signal S16 as central potentials to generate potentials V _H and V _L of logic “H” and “L” levels. The data signal it has is converted into a logical data string corresponding to the write information data S11 and sent as information data DATA11.

The information card 23 is provided with an information card power supply 30, which executes writing, holding, and reading operations of the information data of the write data D _IN fetched from the data writing buffer circuit 26 into the information data memory 32. Let

In the above configuration, the information writing device 22 is the information card 2
When 3 is inserted, new data is written in the information data memory 32.

That is, the information writing device 22 detects, when the information card 23 is inserted, by the insertion detection element 40,
The insertion detection signal S17 is input to the CPU 42.

At this time, as shown in FIG. 4, the CPU 42 first enters the first operating point setting operation period T1 at the time point t ₁ and operates in the write mode period MODE1 to represent the first operating point potential V _S1. By transmitting the point potential level data S15, the digital / analog conversion circuit 46,
The data control circuit 44 is controlled by the output data signal S16 through the operating point level control circuit 47 in sequence to set the center potential of the information data DATA11 to the operating point potential V _S1 .

The CPU 42 uses this operating point potential MODE in the write mode period.
Information data DATA11 which is maintained for one hour and has a corresponding signal level is supplied to the input / output circuit 24 via the positive side data input / output terminal P11P of the information card 23.

Eventually, at the time point t ₂ when the first operating point setting operation period T1 has elapsed, the CPU 42 sets the operating point level data S1.
5 is switched to data designating the operating point potential V _S2 . As a result, the central potential of the output data signal S16 of the data control circuit 44 is switched to the operating point potential V _S2 which is higher by the potential difference ΔV for one step, as shown in FIG. 3 (A2).

Similarly, the CPU 42 operates the operating point setting operation period T
2, T3, T4, T5 elapses t ₃ , t ₄ , t ₅ ,
At every t ₆ , operating point level data S15 for sequentially designating operating point potentials V _s3 , V _s4 , V _s5 , and V _s6 is sent out, whereby the central potential of the output data signal S16 is incremented by one step difference ΔV. High operating point potentials V _s3 , V _s4 , V _s5 , V
_It continues to operate as if it was reset to _s6 .

However, under the control of the CPU 42 as described above, while the central potential of the information data DATA11 arriving at the data writing buffer circuit 26 of the information card 23 rises stepwise, the peak potential of the output data signal S16 (that is, When the potential V _H of the logic “H” level cannot exceed the threshold level V _SH (FIG. 5) of the data write buffer circuit 26, the data write buffer circuit 26 determines that the logic Since it cannot be determined that the "H" level data has arrived, the operation state cannot be taken in as the write data D _IN .

Until the peak potential of the output data signal S16 (that is, the potential V _H at the logic “H” level) exceeds the threshold level V _SH of the data write buffer circuit 26, the center potential of the output data signal S16 is reached. When but rises, data write for buffer circuit 26 in response to the potential V _H of the "H" level logic "H" level of the write data D
_It will be in a state where _IN is generated.

At this time, the write code reading circuit 34 outputs the write code signal S1.
Is generated to control the information data memory 32 in the write mode via the write / read control circuit 31.

Thus, in the write mode MODE1 (FIG. 4), the write data D _IN is taken in through the data write buffer circuit 26 and is written in the data section 32B of the information data memory 32 through the information data input circuit 35.

After that, the CPU 42 reads the read mode MODE2 (FIG. 4).
By switching to the data control circuit 44, the data control circuit 44 is controlled so as not to output the output data signal S16, whereby the read information data S4 read from the header section 32A and the data section 32B of the information data memory 32 is output as the information data output. The read data D _OUT is given to the data output switch circuit 25 via the circuit 33.

Thus, the information data DATA11 is read by the data control circuit 44 of the information writing device 22.

At this time, the data control circuit 44 gives the transmitted information data DATA11 to the data discriminating circuit 45 to judge whether or not this coincides with the write data sent to the information card 23 in the write mode MODE1.

When the data discriminating circuit 45 discriminates the coincidence and sends out the data discriminating signal S13, the CPU 42 switches the operating point level data S15 to the data for designating the operating point level higher by a predetermined number of steps, for example, two steps. Exit the operating point setting mode.

As a result, the data control circuit 44 outputs the output data signal S16.
When the potential V _H (see FIG. 3) of the logic "H" level of ## EQU1 ## exceeds the threshold level of the data write buffer circuit 26 for the first time, the operating point level is further increased by 2 steps. The signal level of the output data signal S16 is set to. As a result, the data write buffer circuit 26 is set to the bias condition so that the write operation can be surely performed thereafter.

According to the above configuration, the information card 23 used for the information card power source 30 having a different type of battery is worn, or the information card power source 37 is consumed and the power supply voltage is lowered, so that the data writing is performed. Even when the bias condition of the buffer circuit 26 changes, when writing information to the information card 23, the output data signal S16 having an operating point potential that adapts to the change of the power supply voltage is supplied to the information card 23. As a result, more accurate information can be written in the information card 23.

(G2) Other Embodiments (1) In the above embodiment, the input / output terminals P11P and P11N of the information card 23 are electrically contacted with the data write terminals P12P and P12N of the information writing device 22. However, the present invention is not limited to this, and may be applied to a non-contact type information card writing system such as an optical type or an electromagnetic type.

(2) In the above-mentioned embodiment, the case where the positive side data input / output terminal P11P is commonly used as the information card 23 to write and read information has been described, but instead of this, information writing is performed. Even if the data read terminal and the information read terminal are separately provided, the same effect as in the above case can be obtained.

(3) In the above-described embodiment, the case where the operating point level of the data writing buffer circuit 26 of the information card 23 is set has been described, but the present invention is not limited to this, and the information writing device 22 side can perform the information writing. It may be used to set the operating point level of the input circuit for fetching the data read from the card 23 into the data control circuit 44.

(4) In the above-described embodiment, after the peak potential of the output data signal S16, that is, the potential V _H of the logic "H" level exceeds the threshold level of the data write buffer circuit 26 for the first time, the output data signal Set the operating point potential of S16 to 2
Although the signal level of the output data signal S16 is set by raising it by the step, the point is not limited to this, and the point is that the step may be raised by one step or a plurality of steps as necessary.

(5) In the above embodiment, the present invention reads the information data of the information data memory 32 by changing the reflectance of the 1/2 wavelength dipole antenna, but the kind and configuration of the antenna may be changed. The present invention can be applied to various types of systems in which a received signal is once taken in, processed, and then re-emitted.

H Effect of the Invention As described above, according to the present invention, the signal level of the write data given to the data writing buffer circuit of the information card can be set by adapting it to the threshold level of the data writing buffer circuit. By doing so, it is possible to realize an information card writing device that can more accurately write information to the information card.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an information writing device according to the present invention, FIGS. 2 and 3 are signal waveform diagrams for explaining the operating point setting operation of FIG. 1, and FIG. 4 is its operation. FIG. 5 is a schematic diagram for explaining the point setting mode, FIG. 5 is a signal waveform diagram for explaining write data, and FIG. 6 is a block diagram showing a conventional information writing / reading device. 21 ... Information card writing system, 22 ... Information writing device, 23 ... Information card, 24 ... Input / output circuit, 25 ...
... switch circuit for data output, 26 ... buffer circuit for data writing, 27, 41 ... information data processing section, 42 ...
... CPU, 43 ... write data memory, 44 ... data control circuit, 45 ... data determination circuit, 47 ... operating point level control circuit.

Claims (2)

[Scope of utility model registration request] 1. An information writing device for inputting an information data signal to an information data memory through a data writing buffer circuit of an information card, in which an operating point potential of the information data signal is raised by a predetermined step potential. Point potential raising means and a state in which the operating point potential of the information data signal exceeds the threshold level of the data writing buffer circuit and information data can be written in the information data memory through the data writing buffer circuit. An information writing device, comprising: an operating point potential setting means for confirming that the operating point potential has risen and stopping the operation of raising the operating point potential. 2. When the operating point potential setting means confirms that information data can be written in the information data memory, the operating point potential is raised by a predetermined number of steps, and then the stop operation is performed. The information writing apparatus according to claim 1, wherein the utility model registration is performed.