JPH08201467A - Operation detecting circuit - Google Patents

Abstract

PURPOSE: To provide a circuit for detecting the operation of a signal generation means, e.g. a pattern generator. CONSTITUTION: The operation detecting circuit comprises a pattern generator 13, a frequency converting section 11, and a display 12. A test signal 1A, a reference timing signal 1B and a clear signal 2A are delivered from the pattern generator 13 to the frequency converting section 11 where the signals are converted into a constant frequency signal 10A. Operating state of the pattern generator 13 is then presented visually on the display 12 based on the constant frequency signal 10A.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operation detection circuit, and more particularly to an operation detection circuit for detecting the presence or absence of operation in a device or circuit that generates an arbitrary frequency signal.

[0002]

2. Description of the Related Art I for testing an IC under test, for example
The C tester uses a pattern generator for outputting a predetermined pattern to the IC under test. In this case, generally, the reference timing of the output signal from the pattern generator is programmable from high speed to low speed according to the purpose of use, that is, the frequency of the output of the signal changes depending on the pattern generation rate. .

[0003]

However, in the case of the signal generating means in which the frequency of the output signal changes like the above pattern generator, the presence or absence of the operation of the signal generating means, that is, the operating or stopped state thereof is detected. There is a problem that it is difficult to do. That is, when the frequency of the output signal is higher than the operating frequency of the computer device for detecting the operation, for example, the computer device cannot recognize the presence or absence of the output signal. Further, if this frequency is, for example, a rate higher than a predetermined blinking cycle in the display device for operation display, it becomes impossible to visually display the presence or absence of the output signal.

An object of the present invention is to provide an operation detecting circuit capable of detecting the presence / absence of an operation in a signal generating means such as a pattern generator.

[0005]

The operation detection circuit of the present invention has a frequency conversion section for converting a first frequency signal of an arbitrary frequency output from the signal generation means into a second frequency signal of a constant frequency. And the frequency conversion unit
First signal output means for generating a predetermined signal which is set by the frequency signal of and which is reset after a lapse of a required time from the end of the first frequency signal, and a reference corresponding to the frequency of the second frequency signal. It is configured to have timing generating means for outputting a clock signal and second signal outputting means for outputting the second frequency signal at the timing of the reference clock signal while the predetermined signal is in the set state.

The signal generating means is specifically, for example, an IC.
This is a pattern generator for testers. Further, the second frequency signal is input to a display device for recognizing a motion display, or is input to a computer device for motion recognition, for example.

[0007]

In the frequency conversion section constituting the operation detection circuit of the present invention, a predetermined frequency is set at the first clock of the first frequency signal of an arbitrary frequency and reset after a certain time has passed from the last clock. It is possible to generate a signal and output a second frequency signal having a constant frequency while the predetermined signal is in the set state (that is, is held active).

Then, using this second frequency signal,
An arbitrary frequency output from the signal generating means can be displayed on a display device, for example, by a lamp for visual confirmation, or can be recognized by a computer device.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an operation detecting circuit of an embodiment of the present invention will be described. The structure of the frequency conversion unit used in this operation detection circuit is shown in FIG. 1, and the time charts for explaining the operation are shown in FIGS.

2A is a reference timing signal 1B, and FIG. 2B is a test signal (testing flag signal).
1A, FIG. 2C shows a timing signal 1C which is a logical product of the reference timing signal 1B and the test signal 1A, FIG.
3A is a waveform diagram of the Q output signal 3A, FIG. 3B is a reference clock signal 4A, and FIG. 3C is a clock signal 5 which is a logical product of the Q output signal 3A and the reference clock signal 4A.
A, FIG. 3 (d) is a carry signal 6A, FIG. 3 (e) is a load signal 8A, FIG. 3 (f) is a reference clock signal 4B, and FIG.
(G) is a clock signal 7A which is a logical product of the Q output signal 3A and the reference clock signal 4B, FIG. 3 (h) is a counter output signal 9A, FIG. 3 (i) is a constant frequency signal 10A, and FIG.
(J) is a waveform diagram of the clear signal 2A, respectively. The time charts of FIGS. 2A to 2D and FIG.
The scale is different from the time charts of (a) to (j).

The frequency converter of the embodiment is the AND gate 1
・ 5/7/10, OR gate 2, flip-flop 3,
The timing generating circuit 4, the counter circuits 6 and 9, and the one-shot multivibrator 8 are included.

AND gate 1 receives test signal 1A and reference timing signal 1B and outputs timing signal 1C. That is, the AND gate 1 opens the gate to pass the reference timing signal 1B and outputs the timing signal 1C when the test signal 1A is active.
Then, the timing signal 1C having an arbitrary frequency is input to the set input S of the flip-flop 3 and the load input LO of the counter circuit 6, respectively. The OR gate 2 receives the clear signal 2A and the carry signal 6A of the counter circuit 6, and outputs the reset signal 2B to the flip-flop 3. The flip-flop 3 receives the timing signal 1C and the reset signal 2B and outputs a Q output signal 3A and a Q (-) output signal 3B. Here, the flip-flop 3 is
It is set by the first clock of the timing signal 1C and reset after a certain time has passed from the last clock. Then, the Q output signal 3A of the flip-flop 3
When is activated, the gates of AND gates 5, 7, and 10 respectively open.

Further, the timing generating circuit 4 always outputs the two reference clock signals 4A and 4B. Here, the reference clock signal 4A is the clock signal of the counter circuit 6, and the reference clock signal 4B is the clock signal of the counter circuit 9. The AND gate 5 receives the reference clock signal 4A and the Q output signal 3A, and outputs the clock signal 5A to the clock input CK of the counter circuit 6. The counter circuit 6 loads at the timing of the timing signal 1C, and counts with the clock signal 5A of the AND gate 5. When the counter circuit 6 overflows, it outputs a carry signal 6A, and the carry signal 6A
The flip-flop 3 is reset by A. Here, the counter circuit 6 functions as a timer for keeping the Q output signal 3A of the flip-flop 3 active for a fixed time from the last clock timing of the timing signal 1C.

The AND gate 7 has a reference clock signal 4B.
And the Q output signal 3A, and outputs the clock signal 7A to the clock input CK of the counter circuit 9. Further, the one-shot multivibrator 8 receives the Q (-) output signal 3B, and outputs the pulse load signal 8A to the load input LO of the counter 9 from the rising edge thereof. Here, the width of the pulse signal determined by the one-shot multivibrator 8 is set to one cycle or less of the reference clock signal 4B. As a result, the first clock of the clock signal 7A can be prevented from disappearing.

The counter circuit 9 loads at the timing of the load signal 8A, and performs counting operation by the clock signal 7A of the AND gate 7. Then, the counter circuit 9
Outputs a counter output signal 9A when the counting is completed, and is reset by a clear signal 2A. Therefore, the counter circuit 9 outputs a repetitive waveform having a constant frequency in synchronization with the timing of the reference clock 7A.

The AND gate 10 outputs the counter output signal 9
Upon receiving the A and Q output signals 3A, it outputs a constant frequency signal 10A. The constant frequency signal 10A outputs a repetitive waveform having a constant frequency while the Q output signal 3A of the flip-flop 3 is held.

In this case, the frequency conversion section converts the timing signal 1C, which is an output signal of an arbitrary frequency output from a pattern generator (not shown), into a constant frequency signal. A Q output signal 3A that is set at the first clock and that is reset after a certain time has elapsed from the last clock of the timing signal 1C is generated, and while the Q output signal 3A is held active, the counter output signal 3A is generated. 9A outputs a constant frequency signal 10A.

That is, referring to FIGS. 2 and 3, the reference timing signal 1B is gated by the test signal 1A to obtain the timing signal 1C (FIGS. 2A to 2C). The period t1 of the reference timing signal 1B is, for example, 200 ns, and the number T1 of clock signals in the timing signal 1C is, for example, 10 times.

In order to reliably recognize the timing signal 1C whose frequency fluctuates, this timing signal 1C
As a set signal for the flip-flop 3, and the carry signal 6A of the counter circuit 6 resets the flip-flop 3 after a lapse of a certain time from the last clock of the timing signal 1C. It should be noted that this fixed time is held only for a half period or more of the counter output signal 9A so that the fixed frequency signal 10A, which is the final output gate signal, can be reliably output even when the timing signal 1C has only one clock. It is set to a time that can be kept.

The counter output signal 9A of the counter circuit 9 is generated while the flip-flop 3 is held and active as described above. Since this signal is synchronized with the reference clock 4B having a constant frequency, it becomes a constant frequency signal, and the repetition cycle is determined by this frequency (FIGS. 3A to 3J). When the counters 6 and 9 are 4-bit counters, the cycle t2 of the reference clock signal 4A is, for example, 50 ns, the number T2 of clock signals in the clock signal 5A is, for example, 16 times, and the cycle t3 of the reference clock signal 4B. Is, for example, 300 ms.

Below, the cycle of the reference timing signal 1B,
The relationship between the cycle of the reference clock signal 4A and the cycle of the reference clock signal 4B is shown.

Maximum period of reference timing signal 1B> 2 × (period of reference clock signal 4A) Maximum period of reference timing signal 1B> 2 × (period of reference clock signal 4B) Period of reference clock signal 4A <reference clock signal 4B When the reference timing signal 1B is no longer input, the flip-flop 3 is reset by the carry signal 6A after a lapse of a fixed time from the last clock. Then, the Q output signal 3A of the flip-flop 3 is not held and the AND gate 10 is gated, so that the constant frequency signal 10A is not output.

Then, the converted constant frequency signal 10A
Indicates that the pattern generator or the like is in operation. Therefore, by checking the constant frequency signal 10A, it is possible to detect whether the pattern generator or the like is operating or stopped.

FIG. 4 shows an operation detection circuit of an embodiment constructed by using the above frequency conversion section. This operation detection circuit is composed of a pattern generator 13, a frequency converter 11, and a display device 12, and is a circuit for detecting the operating state of the pattern generator 13 and visually displaying it on the display device 12. .

In this operation detecting circuit, the pattern generator 1
The test signal 1A, the reference timing signal 1B, and the clear signal 2A from 3 are input to the frequency conversion unit 11. The frequency conversion unit 11 generates the constant frequency signal 10A as described above, and the constant frequency signal 10A is output to the display device 12.

Here, as the frequency of the constant frequency signal 10A, a reference clock signal having a frequency that allows the display device 12 to visually recognize the display of the operating state is appropriately selected. Therefore, the signal from the pattern generator 13 is converted into the constant frequency signal 10A which is visually recognized by the frequency conversion unit 11, and the operating state is displayed at the timing shown in FIG. 3 (i). The display device 12, for example, causes an LED or the like to emit light to display, and the blinking cycle is 0.
It has 6 seconds and a blinking interval of 0.3 seconds.

FIG. 5 shows an operation detecting circuit of another embodiment constructed by using the above frequency converting section. This operation detection circuit is composed of a pattern generator 13, a frequency conversion unit 11, and a CPU circuit unit 14 of a computer device. The operation state of the pattern generator 13 is checked by the CPU circuit unit 14.
It is a circuit to let the user recognize.

In this operation detection circuit, the frequency conversion section 11
The constant frequency signal 10A from is input to the CPU circuit unit 14. The CPU circuit unit 14 is an input circuit for making the CPU performing system control or the like recognize the operating state of the pattern generator 13. Here, the frequency of the constant frequency signal 10A in the operation detection circuit of FIG.
Is different from the case of. That is, the reference clock signal of the considered frequency is selected so that the CPU circuit unit 14 can recognize the operating state.

[0029]

According to the operation detecting circuit of the present invention, the first frequency signal having an arbitrary frequency output from the signal generating means can be converted into the second frequency signal having a constant frequency.
By using the second frequency signal, an arbitrary frequency output from the signal generating means is displayed on a display device or recognized by a computer device, whereby the presence or absence of an operation in the signal generating means can be detected.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of a frequency conversion unit that constitutes an operation detection circuit of the present invention.

FIG. 2 is a time chart of the frequency conversion unit in FIG.

FIG. 3 is a time chart of the frequency conversion unit in FIG.

FIG. 4 is a circuit diagram of an embodiment of an operation detection circuit of the present invention configured by using the frequency conversion unit of FIG.

5 is a circuit diagram of another embodiment of the operation detection circuit of the present invention configured by using the frequency conversion unit of FIG.

[Explanation of symbols]

 1 AND gate 2 OR gate 3 flip-flop 4 timing generation circuit 5 AND gate 6 counter circuit 7 AND gate 8 one-shot multivibrator 9 counter circuit 10 AND gate 11 frequency conversion unit 12 display device 13 pattern generator 14 CPU circuit unit

Claims (5)

[Claims] 1. A frequency conversion unit (1, 2, 3, 4, 5,) for converting a first frequency signal of an arbitrary frequency output from a signal generating means (13) into a second frequency signal of a constant frequency. 6,7,8,9,10), and the frequency conversion unit (1,2,3,4,5,6,7,8,9,10) is the first
First signal output means (1, 2, 3) for generating a predetermined signal which is set by the frequency signal of and which is reset after a lapse of a required time from the end of the first frequency signal, and the second frequency Timing generating means (4) for outputting a reference clock signal corresponding to the frequency of the signal, and second for outputting the second frequency signal at the timing of the reference clock signal while the predetermined signal is in the set state
And a signal output means (5, 6, 7, 8, 9, 10) of the above. 2. The operation detecting circuit according to claim 1, wherein the signal generating means (13) is a pattern generator (13) for an IC tester. 3. The motion detection circuit according to claim 1, wherein the second frequency signal is displayed by a display device (12). 4. The motion detection circuit according to claim 1, wherein the second frequency signal is recognized by a computer device (14). 5. A frequency converter (1, 2, 3, 4, 5,) for converting a first frequency signal of an arbitrary frequency output from the signal generating means (13) into a second frequency signal of a constant frequency. 6,7,8,9,10), the frequency conversion unit (1,2,3,4,5,6,7,8,9,10), the test signal (1A) and the reference The first AND gate (1) which inputs the timing signal (1B) and outputs the timing signal (1C), the clear signal (2A) and the carry signal (6A) of the first counter circuit (6) An OR gate (2) which inputs and outputs a reset signal (2B) to the flip-flop (3), and a flip-flop (3) which is set by the timing signal (1C) and reset by the reset signal (2B) A timing generating circuit (4) for generating the first and second reference clock signals (4A, 4B), the first reference clock signal (4A) and the Q output signal (3A) of the flip-flop (3). ) Enter The first clock signal and
A second AND gate (5) which outputs (5A), is loaded by the timing signal (1C) and reset by the clear signal (2A), and
The first counter circuit (6) using the clock signal (5A) of No. 2 as a reference clock and the Q (-) output signal (3B) of the flip-flop (3) are input to output a load signal (8A). Shot multivibrator (8), the second reference clock signal (4B) and the Q output signal (3A)
Input A to output the second clock signal (7A)
An ND gate (7) and a second counter circuit which is loaded by the load signal (8A) and reset by the clear signal (2A) and which uses the second clock signal (7A) as a reference clock.
(9), the counter output signal (9A) of the counter circuit (9) and the Q
An operation detection circuit comprising an AND gate (10) which receives an output signal (3A) and outputs a constant frequency signal (10A).