JPH08201480A - Signal processor - Google Patents

Abstract

(57) [Summary] [Object] To provide a signal processing device capable of testing a signal block corresponding to a plurality of ICs by using an existing test pattern when the plurality of ICs are combined into one IC. And In a signal processing device in which a plurality of integrated circuits are combined into one, a plurality of signal processing blocks 2 and 5 and a port provided between the plurality of signal processing blocks 2 and 5 and capable of inputting and outputting signals I / O cell 8 as an output terminal and an output terminal 11, and a plurality of signal processing blocks 2 by input / output of signals by the I / O cell 8 as a port and the output terminal 11.
Since the operation test of No. 5 is performed, the test can be performed by using the existing pattern, and the number of steps for combining a plurality of integrated circuits into one can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing apparatus suitable for use in, for example, a hybrid IC which combines a plurality of ICs into one.

[0002]

2. Description of the Related Art When a plurality of ICs are connected to form a circuit, each IC is individually subjected to an operation test in the circuit manufacturing process.

FIG. 6 is a bidirectional bus connection diagram when two conventional ICs are combined into one. In FIG. 6, one IC 60 has an I / O cell 63 that inputs and outputs signals. The I / O cell 63 is the tri-state buffer 6
1 and a buffer 62. The tri-state buffer 61 outputs an output signal from the terminal 64 when the test signal A is active. The buffer 62 also receives an input signal from the terminal 64.

The other IC 65 is an I / O for inputting / outputting signals.
It has an O cell 68. The I / O cell 68 is composed of a tri-state buffer 66 and a buffer 67. The tri-state buffer 66 uses the test signal A
^{When *} (A ^* is an inverted signal of A) is active, an output signal is output from the terminal 69. The buffer 67 also receives an input signal from the terminal 69.

The IC 60 on one side and the IC 65 on the other side are connected by a wiring pattern 70 at terminals 64 and 69. At this time, by activating the test signal A, the tri-state buffer 6 of one IC 60 is
A signal is supplied from 1 to the buffer 67 of the other IC 65 via the terminal 64, the wiring pattern 70, and the terminal 69. Thereby, it is possible to test the output operation of the signal of one IC 60 and the input operation of the signal of the other IC 65.

By activating the test signal B, the tristate buffer 6 of the other IC 65 is also activated.
A signal is supplied from 6 to the buffer 62 of one IC 60 via the terminal 69, the wiring pattern 70, and the terminal 64. Thereby, the output of the signal of the other IC 65 and the input operation of the signal of the one IC 60 can be tested.

FIG. 7 is a unidirectional connection diagram when two conventional ICs are combined into one. In FIG. 7, one IC
Reference numeral 71 has an I / O cell 72 for inputting / outputting signals. The I / O cell 72 is composed of a buffer 73. The buffer 73 outputs an output signal from the terminal 74. The other IC 75 is an I / O cell 7 that inputs and outputs signals.
Have six. The I / O cell 76 is composed of a buffer 77. The buffer 77 outputs an output signal from the terminal 78.

The IC 71 on one side and the IC 75 on the other side are connected by a wiring pattern 79 at terminals 74 and 78. At this time, a signal is supplied from the buffer 73 of one IC 71 to the buffer 77 of the other IC 75 via the terminal 74, the wiring pattern 79 and the terminal 78. As a result, the signal output from one IC 71 and the other IC 75
The input operation of the signal can be tested.

In this way, the operation test of each IC when two ICs are connected to one is performed.

On the market, however, there are demands for miniaturization of the entire device and simplification of the manufacturing process in the production line. Therefore, it is desirable to simplify the circuit system of the signal processing device except for the mechanical structure.

Further, in recent years, as semiconductor manufacturing technology has advanced, it has become possible to combine a plurality of ICs into one IC into a hybrid IC. By doing so, the circuit scale can be reduced,
It has become possible to speed up signal processing.

However, a plurality of such ICs are combined into one I
In the case of being summarized in C, it becomes impossible to carry out an operation test for each signal block inside the IC. Therefore, IC
In the manufacturing process of the IC, it is impossible to determine whether the connection is correct when a plurality of ICs are combined into one IC, and it is not possible to confirm the quality of the integrated IC as a product. I can no longer ship from the production line.

Further, since it takes an extra period of time for developing the test pattern to newly create and add a dedicated test pattern of the integrated IC, the integrated IC is integrated.
The manufacturing period will be extended.

[0014]

In such a conventional signal processing apparatus, when a plurality of ICs are integrated into one IC, it becomes impossible to carry out an operation test for each signal block inside the IC. There was an inconvenience.

The present invention has been made in view of the above points, and when combining a plurality of ICs into one IC, an existing test pattern is used to test the signal blocks corresponding to the plurality of ICs. An object of the present invention is to provide a signal processing device capable of

[0016]

As shown in FIGS. 1 to 5, a signal processing device of the present invention is a signal processing device in which a plurality of integrated circuits are integrated into one, and a plurality of signal processing blocks 2, 5, 31, 33 and a plurality of signal processing blocks 2,
5, 31, and 33, which are provided between ports 5, 31, and 33 and have ports 8, 11, 35, and 38 capable of inputting and outputting signals,
The operation test of the plurality of signal processing blocks 2, 5, 31, 33 is performed by inputting / outputting signals by 1, 35, 38.

Further, the signal processing apparatus of the present invention, as shown in FIGS.
Port control circuit 56 for supplying output control signals to 1, 53
Is provided and the ports 44, 46, 51, 53 are controlled by the output control signal of the port control circuit 56, and the operation test of the plurality of signal processing blocks 43, 48, 55 is performed.

Further, in the signal processing device of the present invention, as shown in FIGS. 1 to 5, in the above description, the plurality of signal processing blocks 2 and 5 transmit signals bidirectionally, and the ports 8 and 11 are connected. It is used as a test output terminal.

Further, in the signal processing apparatus of the present invention, as shown in FIGS. 1 to 5, in the above description, the plurality of signal processing blocks 31 and 33 are for transmitting signals in one direction, and the ports 35 and 38 are. It is designed to be used as a test output or input terminal.

[0020]

According to the present invention, in a signal processing device in which a plurality of integrated circuits are combined into one, a plurality of signal processing blocks 2, 5, 31, 33 and a plurality of signal processing blocks 2,
5, 31, and 33, which are provided between ports 5, 31, and 33 and have ports 8, 11, 35, and 38 capable of inputting and outputting signals,
Since the operation test of the plurality of signal processing blocks 2, 5, 31, 33 is performed by inputting / outputting the signals by 1, 35, 38, the existing pattern can be diverted and the test can be performed. It is possible to reduce the number of steps for integrating the integrated circuits into one.

Further, according to the present invention, in the above, a port control circuit 56 for supplying an output control signal to the ports 44, 46, 51, 53 is provided, and the ports 44, 46, Since the operation tests of the plurality of signal processing blocks 43, 48, 55 are controlled by controlling 51, 53, the plurality of signal processing blocks 4
It is possible to perform an operation test of the plurality of signal processing blocks 43, 48, 55 by simulating 3, 48, 55 with a test program and whether or not an expected value is output.

Further, according to the present invention, in the above description, the plurality of signal processing blocks 2 and 5 are for bidirectionally transmitting signals, and the ports 8 and 11 are used as test output terminals. By detecting the outputs of the plurality of signal processing blocks 2 and 5 that perform bidirectional signal transmission at the ports 8 and 11 as the test output terminals, the operation test of the plurality of signal processing blocks 2 and 5 can be performed. .

Further, according to the present invention, in the above description, the plurality of signal processing blocks 31 and 33 are for unidirectionally transmitting signals, and the ports 35 and 38 are used as test outputs or input terminals. Therefore, a plurality of signal processing blocks 31, 33 for performing unidirectional signal transmission at the ports 35, 38 as test input or output terminals.
It is possible to perform an operation test of the plurality of signal processing blocks 31 and 33 by detecting the output of or of inputting a signal.

[0024]

FIG. 1 shows a bidirectional bus connection diagram when two ICs of one embodiment of a signal processing device according to the present invention are combined. This example is an ADSP that performs acoustic signal processing.
Hybrid I that integrates ICs with multiple functions such as (audio digital signal processor) into one chip
It is about C.

In FIG. 1, the one-chip IC 1 is composed of a plurality of blocks. In this example, an example in which two blocks are connected is shown. One block 2 is composed of a tristate buffer 3 and a buffer 4. The tri-state buffer 3 outputs the input signal S ₁ to the other block 5 when the test signal A is active. Further, the buffer 4 receives the input signal S ₂ from the other block 5.

The other block 5 is composed of a tri-state buffer 6 and a buffer 7. The tri-state buffer 6 outputs the input signal S ₃ to one of the blocks 2 when the test signal B (B is a signal having a different logic depending on each test mode) is active. The buffer also receives the input signal S ₄ from one of the blocks 2.

The output side of the tristate buffer 3 of one block 2 and the output side of the tristate buffer 6 of the other block 5 are connected to each other. Also, the input side of the buffer 4 of one block 2 and the other block 5
The input side of the buffer 7 is connected to each other.

Further, the one-chip IC 1 has an existing I / O cell 8 for inputting / outputting signals. I / O cell 8
Is composed of a tri-state buffer 9 and a buffer 10. The tri-state buffer 9 outputs an output signal from the output terminal 11 when the test signal C is active. The buffer 10 also receives an input signal from the output terminal 11.

Further, the output side of the tristate buffer 3 of one block 2 and the input side of the tristate buffer 9 of the I / O cell 8 are connected to each other. Also,
Input side of buffer 4 of one block 2 and I / O cell 8
The output side of the buffer 10 is connected to each other.

In the one-chip IC 1 thus constructed, when testing one block 2, the test signal B of the other block 5 is made negative and the input signal S ₃ of the tri-state buffer 6 is changed to one block 2 Do not output to. On the contrary, when testing the other block 5, the test signal A of the one block 2 is made negative and the input signal S of the tri-state buffer 3 is set.
Do not output ₁ to the other block 5. Also,
The test of the wiring connecting the block 2 and the block 5 has been completed by testing the blocks 2 and 5. Further, the normal operation test can be performed by monitoring the output terminal 11.

In the above example, one block 2 is ADS.
Alternatively, the other block may be used as a memory and the bus may be used as a data line.

FIG. 2 is a diagram showing the control of the output control signal of an embodiment of the signal processing device according to the present invention.
In FIG. 2, modes indicate normal operation and test modes of the test block 2 and the test block 5. Signals are the test signal A of the tristate buffer 3 of the block 2 in FIG. 1, the test signal B of the tristate buffer 6 of the block 5, the test signal C of the tristate buffer 9 of the I / O cell 8, and the output terminal 11. Shows the output signal of.

2, in the normal operation test mode, the test signal A of the tristate buffer 3 of the block 2 in FIG. 1 is A, and the test signal B of the tristate buffer 6 of the block 5 is A ^* (however, A ^*
Is an inverted signal of A. ), And the test signal C of the tri-state buffer 9 of the I / O cell 8 is 0, the output signal of the output terminal 11 is S ₁ or S ₃ .

That is, in the normal operation test mode, either A or A ^* becomes active, so that either the tristate buffer 3 of block 2 or the tristate buffer 6 of block 5 in FIG. The input signal S ₁ or S ₃ is output. Since the test signal C is 0 and is always active, I
The tri-state buffer 9 of the / O cell 8 has an output terminal 11
The signal S ₁ or S ₃ is output to.

Where S₁Is output, the
From lock 2 tristate buffer 3 to block 5
Tri-state buffer of I / O cell 8 to buffer 7
9 through the buffer 10 and the signal S₁Is being output
It At this time, the signal S₁And S _FourAnd are the same signals. Well
S₃If is output, try block 5
From the state buffer 6 to the buffer 4 of the block 2, I
/ O cell 8 tristate buffer 9 and buffer 1
0 through the signal S₃Is being output. At this time,
No. S₁And S_FourAnd signal S₃And S₂Are the same signal.

In the test mode of the test block 2, the test signal A of the tristate buffer 3 of the block 2 in FIG. 1 is A, the test signal B of the tristate buffer 6 of the block 5 is 1, and the I / O cell. If the test signal C of the 8-state tristate buffer 9 is B, the output signal of the output terminal 11 is S ₁ .

That is, in the test mode of the test block 2, when A is active, the tristate buffer 3 of the block 2 in FIG. 1 is in a state of outputting its input signal S ₁ . Since the signal B is 1 and is always negative, the tristate buffer 6 of the block 5 is
Does not output signal S ₃ . When A is active, I /
The tristate buffer 9 of the O cell 8 outputs S ₁ to the output terminal 11, and the tristate buffer 3 of the block 2
From the input signal S ₁ to the buffer 7 of the block 5 via the tri-state buffer 9 and the buffer 10 of the I / O cell 8. At this time, the signals S ₁ and S ₄ are the same signal.

In the test mode of the test block 5, the test signal A of the tristate buffer 3 of the block 2 in FIG. 1 is 1, the test signal B of the tristate buffer 6 of the block 5 is B, and the I / O cell. If the test signal C of the 8-state tri-state buffer 9 is B, the output signal of the output terminal 11 is S ₃ .

That is, in the test mode of the test block 5, when the signal B is active, the tri-state buffer 6 of the block 5 in FIG.
₃ is output. Since the signal A is 1 and is always negative, the tristate buffer 3 of the block 2 does not output the signal S ₁ . When the signal B is active, the tristate buffer 9 of the I / O cell 8 outputs S ₃ to the output terminal 11, and the tristate buffer 6 of the block 5 outputs the tristate buffer 9 and the buffer 10 of the I / O cell 8. Through the buffer 4 of block 2
The input signal S ₃ is output to. At this time, the signals S ₃ and S
₂ is the same signal.

FIG. 3 is a unidirectional connection diagram when two ICs of another embodiment of the signal processing apparatus according to the present invention are combined into one. In FIG. 3, the one-chip IC 30 is composed of a plurality of blocks. In this example, an example in which two blocks are connected is shown. One block 31 is composed of a buffer 32. The buffer 32 outputs the input signal S ₁ to the other block 33. The other block 33 is composed of a buffer 34. The buffer 34 outputs the input signal S ₂ to the one block 23.

Further, the block 31 has an existing I / O cell 35 for inputting / outputting signals. I / O cell 35
Is composed of a tri-state buffer 36 and a buffer 37. The tri-state buffer 36 outputs an output signal from the input or output terminal 38 when the test signal A is active. Further, the buffer 37 inputs the input signal from the input or output terminal 38.

Further, the buffer 3 of one block 31
The output side of the I / O cell 35 and the input side of the tri-state buffer 36 of the I / O cell 35 are connected to each other. Also, the input side of the buffer 34 of one block 33 and the I / O cell 35
The output side of the buffer 37 is connected to each other.

One-chip IC 30 constructed in this way
In order to test one block 31 in
The test signal A of the tri-state buffer 36 of the / O cell 35 is activated to output the input signal S ₁ of the tri-state buffer 32 or to the input terminal 38. On the contrary, when testing the other block 33, the test signal A of the tri-state buffer 36 of the I / O cell 35 is made negative and the input signal S ₁ of the tri-state buffer 32 is not output or output to the input terminal 38. To do so. Then, enter the signal S ₂ to the output or input terminal 38, via the buffer 37 of the I / O cell 35, so as to output a signal S ₂ to the buffer 34 of the other block 33.

Further, the test of the wiring connecting the block 31 and the block 33 has been completed by testing the blocks 31 and 33. In addition, a test for normal operation is performed at the output or input terminal 38.
You can test by monitoring.

In the above example, one block 31 is AD
SP may be used, the other block 33 may be a memory, and a line connecting the two blocks may be used as an address line.

FIG. 4 is a diagram showing the control of the output control signal of another embodiment of the signal processing apparatus according to the present invention. In FIG. 4, modes indicate normal operation and test modes of the test block 31 and the test block 33. Further, the signal indicates the test signal A of the tri-state buffer 36 of the I / O cell 35 in FIG. 3, and the output or input signal of the output or input terminal 38.

4, in the normal operation test mode, assuming that the test signal A of the tristate buffer 36 of the I / O cell 35 in FIG. 3 is 0, the output signal S ₁ is output to the output or input terminal 38. Is output.

That is, in the normal operation test mode
Test signal A is 0, it is always active
Therefore, the buffer 32 of the block 31 in FIG.
Input signal S₁Is output. Block 31
From the buffer 32 to the tri-state buffer of the I / O cell 35.
The buffer of the block 33 is passed through the buffer 36 and the buffer 37.
Signal S to the buffer 34₁Is output. Also, output or input
The signal S is applied to the input terminal 38. ₁Is output. At this time, the signal
S₁And S₂Are the same signal.

Further, in the test mode of the test block 31, if the test signal A of the tristate buffer 36 of the I / O cell 35 in FIG. 3 is 0, the output or the output signal of the input terminal 38 becomes S _1. .

That is, the test mode of the test block 31 is
Mode, when A is active,
The buffer 32 of the clock 31 receives the input signal S₁Output
It becomes a state. Signal A is 0 and is always active
Therefore, the buffer 32 of the block 31 outputs the signal S₁Output
It The tri-state buffer 36 of the I / O cell 35 is output.
Force or S to input terminal 38₁Is output. Block 31
Buffer 32 of the I / O cell 35 tristate
Through the buffer 36 and the buffer 37, the block 33
To the buffer 34 of the input signal S₁Is output. This and
Signal S₁And S ₂And are the same signals.

In the test mode of the test block 33, if the test signal A of the tri-state buffer 36 of the I / O cell 35 in FIG. 3 is 1, the output or the input signal of the input terminal 38 is S _2. .

That is, the test mode of the test block 33 is
Mode, the buffer 32 of the block 31 in FIG.
Is the input signal S₁Is not output. Signal A is
1 and always negative, so the I / O cell 35
The tri-state buffer 36 of the output or input terminal 3
8 to S₁Is output. Buffer 32 of block 31
And the tri-state buffer 36 of the I / O cell 35 and
To the buffer 34 of the block 33 via the buffer 37
Signal S₁Is output. At this time, the signal S₁And S ₂What is
Same signal.

FIG. 5 is a connection diagram in the case where the ADSP, the microcomputer and the RAM of another embodiment of the signal processing device of the present invention are one chip. In this example, FIG.
An example in which the ADSP 48, the microcomputer 43, the RAM 55, and the output control signal controller 56 are integrated into a one-chip IC 40 as described with reference to FIG. In FIG. 5, the input signal supplied to the input terminal 41 is supplied to the microcomputer 43 via the buffer 42. The microcomputer 43 outputs an output signal such as a command based on the input signal. The output signal output from the microcomputer 43 is sent to the AD through the tristate buffer 45 and the buffer 47 of the existing I / O cell 44.
Supplied to SP48.

From the RAM 55, the existing I / O cells 51
Data necessary for signal processing is supplied to the ADSP 48 via the tri-state buffer 54 and the buffer 52. The ADSP 48 performs a predetermined signal processing, and then outputs an output signal to the output terminal via the buffer 49.

At this time, the output control signal A is supplied from the output control signal controller 56 to the tri-state buffer 45 of the I / O cell 44 connected between the microcomputer 43 and the ADSP 48. Also, ADSP48 and RAM
The output control signal B is supplied from the output control signal controller 56 to the tri-state buffer 54 of the I / O cell 51 connected to the I / O cell 51.

As a result, the test output signal of the microcomputer 43 or the ADSP 48 can be obtained from the test terminal 46 based on the output control signal A. Also, based on the output control signal B, from the test terminal 53 to the ADSP 48 or R
A test output signal of AM55 can be obtained. Regarding the control of the output control signal A or the output control signal B,
This can be similar to the control shown in FIGS. 2 and 4 described above.

According to the above example, as shown in FIGS. 1 and 3, in a signal processing device in which a plurality of integrated circuits are integrated into one,
It is provided between the plurality of signal processing blocks 2, 5, 31, 33 and the plurality of signal processing blocks 2, 5, 31, 33,
I / O cell 8, output terminal 11, I / O cell 35, output or input terminal 38 as a port capable of inputting and outputting signals
And an I / O cell 8 as a port and an output terminal 1
1, a plurality of signal processing blocks 2, 5, 3 by inputting / outputting a signal through the I / O cell 35, the output or the input terminal 38.
Since the operation test of Nos. 1 and 33 is performed, the test can be performed by diverting the I / O cells 8 and 35 as the existing pattern, and the number of steps for combining a plurality of integrated circuits into one can be reduced. You can

Further, according to the above example, in FIG. 5, the output as the port control circuit for supplying the output control signal to the I / O cell 44 as the port, the test terminal 46, the I / O cell 51 and the test terminal 53. A control signal controller 56 is provided, and the output control signal of the output control signal controller 56 as a port control circuit is used to control the I / O cell 4 as a port.
4, test terminal 46, I / O cell 51, test terminal 53
To control a plurality of signal processing blocks 43, 48, 55.
Since the operation test is performed, the plurality of signal processing blocks 43, 48, 55 are simulated by the test program to determine whether the expected value is output or not. 55 operational tests can be performed.

Further, according to the above example, in FIG. 1, the plurality of signal processing blocks 2 and 5 are for bidirectionally transmitting signals, and the I / O cell 8 as a port and the output terminal 11 are provided.
Is used as a test output terminal, the outputs of the plurality of signal processing blocks 2 and 5 that perform bidirectional signal transmission at the I / O cell 8 as a port as a test output terminal and the output terminal 11 are detected. By doing so, the operation test of the plurality of signal processing blocks 2 and 5 can be performed.

Further, according to the above example, in FIG. 3, the plurality of signal processing blocks 31, 33 are for unidirectionally transmitting signals, and the I / O cell 35 as a port and the output or input terminal 38 are Since it is used as a test output or input terminal, an I / O cell 35 indicating a port as a test input or output terminal, a plurality of signal processing blocks 31 for unidirectional signal transmission at an output or input terminal 38, By detecting the output of 33 or inputting a signal, an operation test of the plurality of signal processing blocks 31 and 33 can be performed.

In the above example, the microcomputer, the ADSP, and the memory are integrated into a single-chip IC. However, the invention is not limited to this, and a plurality of ICs having different functions can be integrated into a single-chip IC. It can be applied to all if present.

The control of the output control signal described in FIGS. 2 and 4 is not limited to this, and the operation of each block is simulated to provide a test pattern as to whether or not an expected value is output. Any program will do.

Further, in the above example, the example in which the test is performed for each block of each signal processing is shown, but the one-chip IC may be divided into some modules and the test may be performed for each module.

[0064]

According to the present invention, in a signal processing device in which a plurality of integrated circuits are integrated into one, it is provided between a plurality of signal processing blocks and a plurality of signal processing blocks, and signals can be input and output. Since the operation test of a plurality of signal processing blocks is performed by inputting and outputting a signal through the port, it is possible to divert an existing pattern to perform a test, and a plurality of integrated circuits can be used. It is possible to reduce the man-hours to be summarized in.

Further, according to the present invention, in the above, a port control circuit for supplying an output control signal to the port is provided,
Since the port is controlled by the output control signal of the port control circuit and the operation test of the plurality of signal processing blocks is performed, the expected value is output by simulating the plurality of signal processing blocks by the test program. Whether or not the plurality of signal processing blocks can be operated can be tested.

Further, according to the present invention, in the above description, the plurality of signal processing blocks transmit signals bidirectionally, and the port is used as the test output terminal. By detecting the outputs of the plurality of signal processing blocks that perform bidirectional signal transmission at the port, the operation test of the plurality of signal processing blocks can be performed.

Further, according to the present invention, in the above description, the plurality of signal processing blocks are for unidirectionally transmitting signals, and the ports are used as test outputs or input terminals. The operation test of the plurality of signal processing blocks can be performed by detecting the output of the plurality of signal processing blocks that perform unidirectional signal transmission at the port as the output terminal or by inputting the signals.

[Brief description of drawings]

FIG. 1 is a connection diagram of a bidirectional bus when two ICs are integrated into one in a signal processing device according to an embodiment of the present invention.

FIG. 2 is a diagram showing control of an output control signal of an embodiment of the signal processing device according to the present invention.

FIG. 3 is a second embodiment of the signal processing device according to the present invention.
It is a unidirectional connection diagram when two ICs are made into one.

FIG. 4 is a diagram showing control of an output control signal of another embodiment of the signal processing device according to the present invention.

FIG. 5A of another embodiment of the signal processing device according to the present invention
It is a connection diagram in case DSP, a microcomputer, and RAM are one chip.

FIG. 6 is a connection diagram of a bidirectional bus when two conventional ICs are combined into one.

FIG. 7 is a unidirectional connection diagram when two conventional ICs are combined into one.

[Explanation of symbols]

 1 one-chip IC 2 block 3 tri-state buffer 4 buffer 5 block 6 tri-state buffer 7 buffer 8 I / O cell 9 tri-state buffer 10 buffer 11 output terminal 30 one-chip IC 31 block 32 buffer 33 block 34 buffer 35 I / O Cell 36 Tri-state buffer 37 Buffer 38 Output or input terminal 40 One-chip IC 41 Input terminal 42 Buffer 43 Microcomputer 44 I / O cell 45 Tri-state buffer 46 Buffer 47 ADSP 49 Buffer 50 Output terminal 51 I / O cell 52 Buffer 53 Output Terminal 54 Tri-state buffer 55 RAM 56 Output control signal controller

Claims (4)

[Claims] 1. A signal processing device in which a plurality of integrated circuits are integrated into one, comprising a plurality of signal processing blocks and a port provided between the plurality of signal processing blocks and capable of inputting and outputting signals. A signal processing device, wherein an operation test of the plurality of signal processing blocks is performed by inputting and outputting a signal through the port. 2. The signal processing device according to claim 1, wherein a port control circuit for supplying an output control signal to the port is provided, and the port is controlled by an output control signal of the port control circuit to control the plurality of signals. A signal processing device characterized in that an operation test of a processing block is performed. 3. The signal processing device according to claim 1, wherein the plurality of signal processing blocks transmit signals bidirectionally, and the ports are used as test output terminals. Signal processing device. 4. The signal processing device according to claim 1, wherein the plurality of signal processing blocks are for unidirectionally transmitting signals, and the ports are used as test outputs or input terminals. Signal processing device.