JPH08201769A - Liquid crystal display - Google Patents

Abstract

(57) [Abstract] (Correction) [Purpose] A simple circuit is added without using a frame memory, and an inversion signal is written for each row pixel to a pixel with the same number of scanning lines as a television, and the resolution is degraded. Provided is a liquid crystal display device capable of displaying an image while suppressing the occurrence of flicker. [Structure] First, the reset transistor 17 is turned on to reset the data line 14 to the reference potential Vc. Next, the color signals (R, G, B) are directly written to the pixels on the L2 row, and at the same time, the color signal R is stored in the capacitor 18 of the storage circuit.
', G', B'are stored. The voltage written in the capacitor 18 is retained. In the next period, the reset transistor 17 is made conductive, the data line 14 is reset to the reference potential Vc, the transfer transistor 19 is made conductive, and the color signal R ′ stored in the capacitor 18 in the L1 row,
G ′ and B ′ are transferred and written in the pixel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device.

[0002]

2. Description of the Related Art Conventionally, a matrix type color liquid crystal display device has been known as a liquid crystal display device of this type. Figure 10
FIG. 6 is a block diagram showing a configuration of a conventional color liquid crystal display device. In the figure, 10a is a display pixel portion, 20a is a vertical scanning circuit of the display pixel portion 10a, 30a is a sampling circuit for sampling an image signal, and 40a is a horizontal scanning circuit for horizontally scanning the sampled image signal.

The unit pixel of the display pixel section 10a comprises a switching transistor 11a, a liquid crystal and a pixel capacitor 12a. The gate of the switching transistor 11a is connected to the vertical scanning circuit 20a via the gate line 13a,
The input terminal of the switching transistor 11a is connected to the sampling circuit 30a via the vertical data line 14a.

The other end of the pixel capacitor 12a is connected to the common electrode line 12A, and the common electrode voltage VLC is applied to the common electrode line 12A.

Color signals (red, blue, green) from the signal processing circuit 50a are supplied to the input of the sampling circuit 30a. The signal processing circuit 50a performs gamma processing in consideration of liquid crystal characteristics, inverted signal processing for extending the life of the liquid crystal, and the like.

FIG. 11 is a timing chart showing an image signal input to the signal processing circuit 50a. FIG. 12 is a timing chart showing the waveform of an image signal inverted every horizontal scanning period (1H). The inversion signal has a waveform in which the positive polarity signal (+) and the negative polarity signal (−) are repeated every 1H with the common electrode voltage VLC as an intermediate potential.

The control circuit 60a includes a vertical scanning circuit 20a,
The pulse signal is output to the horizontal scanning circuit 40a and the signal processing circuit 50a.

FIG. 13 is an explanatory diagram showing an equivalent circuit of the display pixel section 10a and the sampling circuit 30a. R,
The G and B pixels are arranged in a delta shape, and the data line 14a
Pixels in the row direction of the same color (hereinafter, “d1, d2, ...”)
Row pixels) are connected. Sampling circuit 3
0a is a switching transistor (sw1, sw2 ...)
And capacitance (parasitic capacitance and pixel capacitance of the data line 14a in the vertical direction). Switching transistor (s
The gates of w1, sw2 ...) are horizontal scanning circuits 40, respectively.
driven by the horizontal scanning pulse signals (h1, h2 ...) Of a, each color signal of the input signal line 16a is converted into the data line 14a.
It is transferred via (d1, d2 ...) And written in each pixel.

Selection of pixels in each row is controlled by vertical scanning pulse signals (¢ g1, ¢ g2 ...) From the vertical scanning circuit 20a.

FIG. 14 is an explanatory diagram showing interlaced (interlaced) scanning in a conventional television. Row pixels of the display pixel portion 10a are indicated by symbols (g1, g2 ...) Corresponding to the vertical scanning pulse signal. In the odd field, the signal of the horizontal scanning line odd1 is written in the row pixels g2 and g3, and similarly, the signal of the odd2 is written in the row pixels g4 and g5. The same applies to odd3 and later. In the even-numbered field, the scanning combination is shifted by one row, and the signal of even1 is written in the row pixels g1 and g2.

FIG. 15 is a timing chart showing the horizontal scanning pulse signals (h1, h2 ...) And the vertical scanning pulse signals (¢ g1, ¢ g2 ...) In the interlaced scanning shown in FIG. In odd1 of the odd field, the vertical scanning pulse signals ¢ g2 and ¢ g3 of the row pixels g2 and g3 become H level, and the transistors of the row pixels g2 and g3 become conductive. The image signals sampled sequentially by the sampling circuit 30a are written in the row pixels.

The sampling is performed during the H level period of the horizontal scanning pulse signals (h1, h2 ...). The odd-numbered field scans after odd2 are driven at the same timing. In such a two-line simultaneous driving method, the same sampling signal is written in pixels spatially separated by four pixels, so the driving method is simple, but the sampling frequency is not high and color moire occurs at low resolution. .

Further, the edge shift of the image is displayed in zigzag due to the row shift driving of the combination of the row pixels in the odd field and the even field.

FIG. 16 is an explanatory diagram showing the polarities of the signals written in each pixel. A positive voltage with respect to the common electrode voltage VLC is "+", and a negative voltage is "-", each field scanning period is shown in the horizontal direction, and row pixels are shown in the vertical direction. Focusing on one row pixel, in the two-line simultaneous drive system, the signal polarity is inverted every two fields (30 Hz). Therefore,
In NTSC, flickering, that is, flickering, occurs in the display at 15 Hz, which is 1/2 of that. The lower the frequency of flicker, the more noticeable and noticeable the human eye is.

Further, since a set of "+" or "-" in a certain field is shifted by one line in the next field and is shifted by one line each time the field further advances, it looks like stripes flow to the human eye (line). It is called crawl), and the display quality is poor.

As a conventional example for improving the above-mentioned decrease in resolution and occurrence of flicker, there is a double speed scanning method using a frame memory. FIG. 17 is a timing chart showing a vertical scanning pulse signal in the double speed scanning method using a frame memory. In the figure, image signal (sampling signal)
The frequency of the horizontal scanning pulse signal is doubled, and the signal in the two horizontal scanning periods (2H) is driven in one horizontal scanning period.

In this case, if an inverted signal is generated for each 1 / 2H and for each field, the signal polarity of each pixel can be changed for each field, and the flicker component can be improved to 30 Hz.

[0018]

However, the above-mentioned conventional examples have the following problems, and further improvements have been demanded. That is, in the two-line simultaneous driving method in which the driving circuit is simple, the resolution is lowered and flicker occurs as described above.

Further, the double speed scanning method as an improved example thereof requires a frame memory and a high-bandwidth signal processing IC, resulting in a very expensive display device with high power consumption.

Therefore, according to the present invention, an inversion signal is written for each row pixel to a pixel having the same number of scanning lines as a television by adding a simple circuit without using a frame memory.
It is an object of the present invention to provide a liquid crystal display device capable of displaying an image while suppressing a reduction in resolution and the occurrence of flicker.

[0021]

In order to achieve the above object, in a liquid crystal display device according to a first aspect of the present invention, pixels are arranged in a matrix, and an image signal is generated by inverting the polarity for each row pixel. In a liquid crystal display device for writing, a control unit for generating a control signal according to a horizontal scanning period, an inverting unit for inverting the image signal according to the control signal, and an inversion or non-inversion image signal for the inversion or non-inversion according to the control signal. First writing means for writing to the row pixels, storage means for storing the image signal having a polarity opposite to that of the image signal to be written at the same time as the writing, and the stored image signal according to the control signal. Second writing means for writing to the next row pixel.

According to a second aspect of the present invention, there is provided the liquid crystal display device according to the first aspect, wherein the inverting means inverts the image signal for each field period.

In a liquid crystal display device according to a third aspect, in the liquid crystal display device according to the first aspect, the first writing means writes in row pixels of odd rows and the second writing means writes in row pixels of even rows. It is characterized in that the writing procedure and the first writing means write to the row pixels of even rows and the second writing means alternately repeats the writing procedure to the row pixels of odd rows.

[0024]

In the liquid crystal display device according to the first aspect of the present invention, when the image signal is written by reversing the polarity for each row pixel, the control means generates a control signal according to the horizontal scanning period,
The inversion means inverts the image signal according to the control signal, the first writing means writes the inverted or non-inverted image signal in the row pixel according to the control signal, and the storage means writes the written image signal. The image signal having a polarity opposite to that of the
The writing means writes the stored image signal in the next row pixel in response to the control signal.

[0025]

EXAMPLES Examples of the liquid crystal display device of the present invention will be described.

[First Embodiment] FIG. 1 is a block diagram showing the arrangement of a liquid crystal display device according to the first embodiment. Liquid crystal display device 1
The display pixel section 10, the vertical scanning circuit 20, the sampling circuits 30A and 30B, the horizontal scanning circuits 40A and 40B, the signal processing circuit 50, the control circuit 60, the storage circuit 70, the amplifier 80, and the switch circuit 90.

The liquid crystal display device 1 of the present embodiment is characterized in that it has two image input means for the data lines 14 in the vertical direction. That is, one image input means is composed of the sampling circuit 30B and the horizontal scanning circuit 40B,
The other image input means is composed of a sampling circuit 30A, a horizontal scanning circuit 40A and a storage circuit 70. The color signals R, G, B (image signals) output from the signal processing circuit 50 are divided into a system that is directly guided to the sampling circuit 30B and a system that is guided to the sampling circuit 30A via the amplifier 80.

Since the storage circuit 70 is generally formed of a capacitance circuit, when the image signal from the storage circuit 70 is transferred to the pixel capacitance via the vertical data line 14, the vertical data line 14 is mainly generated. Although the signal amplitude decreases due to the parasitic capacitance of, the amplifier 80 amplifies the image signal to compensate for the decrease in signal amplitude.

Further, the vertical scanning circuit 20 is provided with a switch circuit 90 which is a switching means for row pixels.
FIG. 2 shows the display pixel section 10 and the sampling circuits 30A and 30A.
FIG. 9 is an explanatory diagram showing an equivalent circuit of B, a storage circuit 70, and a switch circuit 90.

As shown in FIG. 2, the vertical data line 1
4 for resetting 4 to the reference potential Vc, a capacitor 18 (cT) for temporarily storing the image signal sampled by the switching transistors (sw31, sw32 ...), and a vertical direction for the image signal temporarily stored in the capacitor 18. Transistor 19 for transferring to the data line 14 in the vertical direction, and the vertical gate pulse signal (g
Switching transistors (sw91, sw92) for selecting the row pixels according to 1, g2 ...

FIG. 3 is a timing chart showing drive signals of the liquid crystal display device 1. Each transistor becomes conductive during the H level period of the input pulse signal. FIG. 4 is a timing chart showing the output signals R, G, B from the signal processing circuit 50. The output signal R from the signal processing circuit 50,
G and B are signals that are inverted every horizontal scanning period as shown by S2 'in the figure.

As shown in FIG. 3, the reset transistor 17 is made conductive by the pulse signal ¢ c in the first T1 period of the horizontal scanning period, and the vertical data line 14 is reset to the reference potential Vc.

In the next T2 period, the horizontal scanning pulse signal ¢ H1
(H11, h12), the vertical gate pulse signal g1, and the row pixel selection pulse signal ¢ B, the color signal (R,
G and B) are directly written to the pixels in the L2 row. At this time, the horizontal scanning pulse signal H2 (h21, h2
According to 2), the color signals R ′, G ′, B ′ are stored in the capacitor 18 of the storage circuit 70. When the T2 period ends, the row pixel selection pulse signal ¢ B becomes L level, so that the pixel transistor SW92 of the row pixel becomes non-conducting and holds the written voltage.

In the T3 period, the reset transistor 17 is made conductive by the pulse signal ¢ c to remove the residual charge of the data line 14 in the vertical direction, and the data line 14 is set to the reference potential Vc.
Reset to. In the period T4, the transfer signal 19 is made conductive by the pulse signal ¢ T, and the pixel transistor SW91 of the row L1 is made conductive by the row selection pulse signal ¢ A, and the color signals R'and G stored in the capacitor 18 are stored.
′ And B ′ are transferred and written in the pixel. At this time, the signal level of the signal written in the pixel of the L1 row is lowered by the capacitance division, and becomes the same as the signal level written in the horizontal pixel row L2.

After resetting the vertical data line 14 to the reference voltage Vc by the pulse signal ¢ c in the next T5 period,
During the T6 period, the horizontal scanning pulse signal ¢ H1 (h11, h1
2), the vertical gate pulse signal g2, and the row pixel selection pulse signal ¢ A, the color signals R, G, and B are directly changed to L.
Written in pixels of three rows.

In the same operation as described above, the color signals R ', G', B'are simultaneously stored in the capacitor 18 of the storage circuit 70 by the horizontal scanning pulse signal H2 (h21, h22). When the T6 period ends, the row pixel selection pulse signal ¢ A
Goes to the L level and holds the written voltage.

After resetting the data line 14 to the reference voltage Vc by the pulse signal ¢ c in the period T7, the row pixel L4 is made conductive by the pulse signal ¢ T and the row pixel selection pulse signal ¢ B in the period T8, and the capacitor 18 The color signals R ′, G ′, B ′ accumulated in the pixel are transferred and written in the pixel.

As described above, two row pixels are generated at different timings for the color signals R, G, B and R ', G', B'from the signal processing circuit 50 by a series of pulse signals in one horizontal scanning period (1H). Written in.

Therefore, between the two row pixels, the sampling frequency of the pixel signal is doubled as compared with the conventional one, the resolution can be improved, and the color moire due to the aliasing distortion of the sampling can be reduced.

The shifts in the start timings of the pulse signals h11 and h12 of the pulse signal H1 and the h21 and h22 of the pulse signal H2 take into consideration the four pixel shift of the spatial arrangement of the same color signal between the two row pixels.

FIG. 5 is a block diagram showing a configuration of a signal processing circuit 50 for writing an inversion signal to pixels on a scanning line equivalent to that of a television. The signal processing circuit 50 is the gamma processing circuit 5.
With 0A. The gamma processing circuit 50A performs gamma processing for converting the input signals R, G, and B, which are television signals, into the input / output characteristics of the liquid crystal.

The signal S1 subjected to the gamma process (see FIG. 11) is converted by the inversion control circuit 50B controlled by the pulse signal ¢ FRP into the inversion signal S2 'for each horizontal scanning period and each field period. (Fig. 4).

The inverted signal S2 'is supplied to the sampling circuit 30B.
To the sampling circuit 30A after being inverted by the amplifier 80.

The output signal from the sampling circuit 30A is temporarily stored in the storage circuit 70 and then written into the row pixels in the blanking period.

When such a signal is input to the sampling circuits 30A and 30B, the polarities of the color signals R, G, and B in the first horizontal scanning period are "+", and thus the polarities of the L1 row. The polarity of the pixel is “−”, and the polarity of the pixel on the L2 row is “+”.

In the next horizontal scanning period, the color signals R,
Since the polarities of G and B are inverted and become "-", the polarities of the color signals R ', G', B'become "+". Therefore, L3
The polarities of the pixels in the row are “−”, and the polarities of the pixels in the row L4 are “+”.

By performing the writing as described above during two horizontal scanning periods and repeating this during the subsequent horizontal scanning period, the polarities of the pixels of adjacent rows are opposite to each other.

In the next field, the signal polarity is inverted (see FIG. 4), and the color signal R in the first horizontal scanning period,
Since the polarities of G and B are “−” and the polarities of the color signals R ′, G ′, and B ′ are “+”, the polarities of the pixels on the L1 row are “+”.
Therefore, the polarity of the pixel on the L2 row is "-".

In the next horizontal scanning period, the polarities of the color signals R, G, B are inverted and become "+", so that the polarities of the color signals R ', G', B'become "-". . Therefore,
The polarity of the pixels in the L3 row is “+”, and the polarity of the pixels in the L4 row is “−”.

As described above, the polarities of the signals written in the respective pixels are inverted for each row pixel and also for each field period.

[Second Embodiment] Next, a liquid crystal display device of a second embodiment will be described. FIG. 6 is a timing chart showing drive signals of the liquid crystal display device 1 of the second embodiment.
The same components as those in the first embodiment are designated by the same reference numerals.

In the second embodiment, the image signal is temporarily stored in the vertical data line 14 by the sampling circuit 30B in the period T2, and the image signal stored in the corresponding pixel by the pulse signal ¢ B in the period T3. Forward.

During the period T3 ', the data line 14 is supplied with the reference potential Vc.
Reset to pulse signals ¢ A 'and ¢ T during period T4.
The signal stored in the capacitor 18 is transferred to the corresponding pixel by ???.

Similarly, during the period T6, the sampling circuit 30
The image signal is temporarily stored in the vertical data line 14 at B, the image signal stored in the corresponding pixel is transferred by the pulse signal ¢ A 'during the period T7, and the data line 1 is transmitted during the period T7'.
After resetting 4 to Vc, pulse signal ¢ B
The signal stored in the capacitor 18 is transferred to the corresponding pixel by means of ‘and‘ T ’.

FIG. 7 is an explanatory diagram showing the buffer circuit 100B provided before the data line 14. By providing the buffer circuit 100B on the data line 14, it is possible to avoid a decrease in signal amplitude due to capacitance division, and it is possible to omit the amplifier 80 of the first embodiment. Further, by providing the buffer circuit 100A, it is possible to cancel a constant offset voltage between the buffer circuits.

Although the first and second embodiments are applied to the color pixel arrangement, the present invention is not particularly limited to this, and a monochrome pixel arrangement may be used. FIG. 8 is an explanatory diagram showing a monochrome pixel arrangement. The pixel arrangement connected to the data line 14 is a case of repeating two colors, but in this case, the same can be applied by changing the timing of the sampling circuit.

FIG. 9 shows the signal processing circuit 5 according to the second embodiment.
It is a block diagram which shows the structure of 0. Gamma processing circuit 50
The signal output from A is a two-system inversion control circuit 50B,
Input to 50C. In the inversion control circuits 50B and 50C, the image signal is inverted by the control signal ¢ FRP from the control circuit 60 and input to the sampling circuit 30A and the sampling circuit 30B, respectively.
The control signal inverted by the inverter 35 is input to B. Even with such a configuration, the same effect as that of the first embodiment can be obtained.

[0058]

According to the liquid crystal display device according to the first aspect of the present invention, when the image signal is written by reversing the polarity for each row pixel, the control means generates the control signal according to the horizontal scanning period. The image signal is inverted by the inverting means according to the control signal, the inverted or non-inverted image signal is written in the row pixel by the first writing means according to the control signal, and the image is written by the accumulating means. The image signal having the opposite polarity to the signal is stored at the same time,
The writing means writes the stored image signal to the next row pixel in response to the control signal. Therefore, the polarity of the input inversion signal is controlled by adding a simple circuit, and the horizontal scanning is performed to invert the polarity for each row pixel. The frequency can be increased and flicker can be suppressed.

Further, since it is not necessary to use the frame memory, the power consumption can be reduced, the circuit scale can be reduced, and the cost can be reduced.

According to the liquid crystal display device of the second aspect, since the inverting means inverts the image signal for each field period, flicker can be further suppressed and display quality can be improved.

According to the liquid crystal display device of the third aspect, the first writing means writes in the row pixels of odd rows and the second pixels
The writing means writes in the row pixels of even rows;
Since the writing means writes in the row pixels of even rows and the second writing means alternately repeats the procedure of writing in the row pixels of odd rows, the display quality can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a liquid crystal display device of a first embodiment.

2 shows a display pixel section 10, sampling circuits 30A, 3;
0B, an equivalent circuit of the storage circuit 70 and the switch circuit 90.

FIG. 3 is a timing chart showing drive signals of the liquid crystal display device 1.

FIG. 4 is a timing chart showing output signals R, G, B from a signal processing circuit 50.

FIG. 5 is a block diagram showing a configuration of a signal processing circuit 50 that writes an inversion signal to a pixel on a scanning line equivalent to that of a television.

FIG. 6 is a timing chart showing drive signals of the liquid crystal display device 1 of the second embodiment.

FIG. 7 is an explanatory diagram showing a buffer circuit 100B provided before the data line 14.

FIG. 8 is an explanatory diagram showing a monochrome pixel arrangement.

FIG. 9 is a block diagram showing a configuration of a signal processing circuit 50 according to a second embodiment.

FIG. 10 is a block diagram showing a configuration of a conventional color liquid crystal display device.

FIG. 11 is a timing chart showing an image signal input to the signal processing circuit 50a.

FIG. 12 is a timing chart showing a waveform of a signal which is inverted every horizontal scanning period (1H).

FIG. 13 shows a display pixel section 10a and a sampling circuit 3.
It is explanatory drawing which shows the equivalent circuit of 0a.

FIG. 14 is an explanatory diagram showing interlaced (interlaced) scanning in a conventional television.

15 is a timing chart showing horizontal scanning pulse signals (¢ h1, ¢ h2 ...) And vertical scanning pulse signals (¢ g1, ¢ g2 ...) In the interlaced scanning shown in FIG.

FIG. 16 is an explanatory diagram showing a polarity of a signal written in each pixel.

FIG. 17 is a timing chart showing a vertical scanning pulse signal in a double speed scanning method using a frame memory.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Liquid crystal display device 10 Display pixel part 14 Data line 20 Vertical scanning circuit 30A, 30B Sampling circuit 40A, 40B Horizontal scanning circuit 50 Signal processing circuit 60 Control circuit 70 Storage circuit

Claims (3)

[Claims] 1. In a liquid crystal display device in which pixels are arranged in a matrix and an image signal is written by inverting the polarity for each row pixel, a control means for generating a control signal according to a horizontal scanning period, and the control signal Therefore, inversion means for inverting the image signal, first writing means for writing the inverted or non-inverted image signal in the row pixels according to the control signal, and the image signal having a polarity opposite to the written image signal. And a second writing means for writing the stored image signal to the pixel in the next row according to the control signal. 2. The liquid crystal display device according to claim 1, wherein the inverting means inverts the image signal for each field period. 3. The procedure for the first writing means to write to row pixels of odd rows, the second writing means to write to the row pixels of even rows, and the first writing means to write to the row pixels of even rows. 2. The liquid crystal display device according to claim 1, wherein the writing and the second writing means alternately repeat the procedure of writing to the row pixels of odd rows.